Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399722
Evgeny Bolotin, A. Morgenshtein, I. Cidon, R. Ginosar, A. Kolodny
Efficient module integration in systems on chip (SoC) is a great challenge. We present a novel automated network on chip (NoC) centric integration method for large and complex SoCs. A quality of service NoC (QNoC) architecture and its design considerations are presented. Then, we describe a chain of design automation tools that allows fast and hardware-efficient SoC integration using the QNoC paradigm. The tool-chain receives a list of system modules and their inter-module communication requirements and results in complete system hardware and verification models for faster SoC fabrication and easier verification.
{"title":"Automatic hardware-efficient SoC integration by QoS network on chip","authors":"Evgeny Bolotin, A. Morgenshtein, I. Cidon, R. Ginosar, A. Kolodny","doi":"10.1109/ICECS.2004.1399722","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399722","url":null,"abstract":"Efficient module integration in systems on chip (SoC) is a great challenge. We present a novel automated network on chip (NoC) centric integration method for large and complex SoCs. A quality of service NoC (QNoC) architecture and its design considerations are presented. Then, we describe a chain of design automation tools that allows fast and hardware-efficient SoC integration using the QNoC paradigm. The tool-chain receives a list of system modules and their inter-module communication requirements and results in complete system hardware and verification models for faster SoC fabrication and easier verification.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84427397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399640
Ilya Obridko, R. Ginosar
Asynchronous circuits are often presented as a means to achieve low power operation. We investigate their suitability for low energy applications, where long battery life and delay tolerance is the principal design goal, and where performance is not a critical requirement. Three adder circuits are studied -two dynamic and one based on pass-transistor logic. All adders combine dual-rail and bundled-data circuits. The circuits are simulated at a wide supply-voltage range, down to their minimal operating point. Leakage energy (at 0.18 /spl mu/m) is found to be negligible. Transistor count is found to be an unreliable predictor of energy dissipation. Keepers in dynamic logic are eliminated when possible. The least amount of energy is dissipated by a modified version of a two-bit dynamic adder originally proposed by K.S. Chong et al. (see Int. Symp. Circuits and Systems, 2002).
{"title":"Low energy asynchronous adders","authors":"Ilya Obridko, R. Ginosar","doi":"10.1109/ICECS.2004.1399640","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399640","url":null,"abstract":"Asynchronous circuits are often presented as a means to achieve low power operation. We investigate their suitability for low energy applications, where long battery life and delay tolerance is the principal design goal, and where performance is not a critical requirement. Three adder circuits are studied -two dynamic and one based on pass-transistor logic. All adders combine dual-rail and bundled-data circuits. The circuits are simulated at a wide supply-voltage range, down to their minimal operating point. Leakage energy (at 0.18 /spl mu/m) is found to be negligible. Transistor count is found to be an unreliable predictor of energy dissipation. Keepers in dynamic logic are eliminated when possible. The least amount of energy is dissipated by a modified version of a two-bit dynamic adder originally proposed by K.S. Chong et al. (see Int. Symp. Circuits and Systems, 2002).","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88042806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399751
M. A. Domínguez, J. L. Ausín, G. Torelli, J. F. Duque-Carrillo
The paper presents an effective approach to the design of on-chip spectrum analyzers based on switched-capacitor (SC) techniques. High programmability resolution is obtained by using a non-uniform sampling scheme without modifying any capacitor value. As a result, capacitor spread and total capacitor area are reduced as compared to traditional solutions and, hence, test area overhead can be minimized. To prove the feasibility of the proposed approach, the design and the implementation of a 0.35 /spl mu/m CMOS SC spectrum analyzer are discussed. Simulation results confirm that high measurement accuracy can be achieved.
{"title":"On-chip area-efficient spectrum analyzer for testing analog IC","authors":"M. A. Domínguez, J. L. Ausín, G. Torelli, J. F. Duque-Carrillo","doi":"10.1109/ICECS.2004.1399751","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399751","url":null,"abstract":"The paper presents an effective approach to the design of on-chip spectrum analyzers based on switched-capacitor (SC) techniques. High programmability resolution is obtained by using a non-uniform sampling scheme without modifying any capacitor value. As a result, capacitor spread and total capacitor area are reduced as compared to traditional solutions and, hence, test area overhead can be minimized. To prove the feasibility of the proposed approach, the design and the implementation of a 0.35 /spl mu/m CMOS SC spectrum analyzer are discussed. Simulation results confirm that high measurement accuracy can be achieved.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87002804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399752
Joshua M. Lucas, R. Hoare, I. Kourtev, A. Jones
The paper proposes a technique for area-optimized FPGA technology mapping. The LURU algorithm maps a combinational circuit to a network of K-input lookup tables (LUTs). The LURU algorithm uses content addressable memory (CAM) to enable parallel pattern matching in a Boolean network. As a result, it is possible to perform global searches quickly within an entire Boolean network, thus increasing the quality of results compared to algorithms of local scope. To utilize CAM for the LURU algorithm, a circuit is described as a set of one dimensional text strings, each of which independently represents the topology of a portion of the circuit. The LURU algorithm was tested with specially partitioned circuits from the ISCAS'85 set of combinational benchmarks. These results are compared with results obtained from the mapping algorithms FlowMap and CutMap. It is demonstrated that using LURU leads to an average of 25% area improvement over both FlowMap and CutMap.
{"title":"LURU: global-scope FPGA technology mapping with content-addressable memories","authors":"Joshua M. Lucas, R. Hoare, I. Kourtev, A. Jones","doi":"10.1109/ICECS.2004.1399752","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399752","url":null,"abstract":"The paper proposes a technique for area-optimized FPGA technology mapping. The LURU algorithm maps a combinational circuit to a network of K-input lookup tables (LUTs). The LURU algorithm uses content addressable memory (CAM) to enable parallel pattern matching in a Boolean network. As a result, it is possible to perform global searches quickly within an entire Boolean network, thus increasing the quality of results compared to algorithms of local scope. To utilize CAM for the LURU algorithm, a circuit is described as a set of one dimensional text strings, each of which independently represents the topology of a portion of the circuit. The LURU algorithm was tested with specially partitioned circuits from the ISCAS'85 set of combinational benchmarks. These results are compared with results obtained from the mapping algorithms FlowMap and CutMap. It is demonstrated that using LURU leads to an average of 25% area improvement over both FlowMap and CutMap.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82976670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399734
Kio Kim, N. Intrator, N. Neretti
We introduce an algorithm for image registration and mosaicing on underwater sonar image sequences characterized by a high noise level, inhomogeneous illumination and low frame rate. For a planar surface viewed through a pinhole camera undergoing translational and rotational motion, registration can be obtained via a projective transformation. For an acoustic camera, we show that, under the same conditions, an affine transformation is a good approximation. We propose a novel image fusion, which maximizes the signal-to-noise ratio of the mosaic image. The full procedure includes illumination correction, feature based transformation estimation, and image fusion for mosaicing.
{"title":"Image registration and mosaicing of noisy acoustic camera images","authors":"Kio Kim, N. Intrator, N. Neretti","doi":"10.1109/ICECS.2004.1399734","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399734","url":null,"abstract":"We introduce an algorithm for image registration and mosaicing on underwater sonar image sequences characterized by a high noise level, inhomogeneous illumination and low frame rate. For a planar surface viewed through a pinhole camera undergoing translational and rotational motion, registration can be obtained via a projective transformation. For an acoustic camera, we show that, under the same conditions, an affine transformation is a good approximation. We propose a novel image fusion, which maximizes the signal-to-noise ratio of the mosaic image. The full procedure includes illumination correction, feature based transformation estimation, and image fusion for mosaicing.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81583603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399629
R. Barsky, I. Wagner
We define and investigate the problem of electromigration faults caused by spot defects during the VLSI manufacturing process. Analysis is given for a simple layout, and simulations are presented and discussed for a more complicated case. It is shown that in some cases, electromigration-dependent parametric faults can make a significant contribution to the total yield estimation.
{"title":"Electromigration-dependent parametric yield estimation","authors":"R. Barsky, I. Wagner","doi":"10.1109/ICECS.2004.1399629","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399629","url":null,"abstract":"We define and investigate the problem of electromigration faults caused by spot defects during the VLSI manufacturing process. Analysis is given for a simple layout, and simulations are presented and discussed for a more complicated case. It is shown that in some cases, electromigration-dependent parametric faults can make a significant contribution to the total yield estimation.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81734138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399699
J. Dobes, J. Míchal
An optimal pivoting strategy for the reduction algorithm transforming the general eigenvalue problem to the standard one is presented for both full- and sparse-matrix techniques. The method increases the precision of the semisymbolic analyses, especially for large-scale circuits. The accuracy of the algorithms is furthermore increased using longer numerical data. First, a long double precision sparse algorithm is compared with the double precision sparse and full-matrix ones. Further, the application of a suitable multiple-precision arithmetic library is evaluated. Finally, the use of longer numerical data to eliminate possible imprecision of the multiple eigenvalues is evaluated.
{"title":"Enhancement of the semisymbolic analysis precision using the variable-length arithmetic","authors":"J. Dobes, J. Míchal","doi":"10.1109/ICECS.2004.1399699","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399699","url":null,"abstract":"An optimal pivoting strategy for the reduction algorithm transforming the general eigenvalue problem to the standard one is presented for both full- and sparse-matrix techniques. The method increases the precision of the semisymbolic analyses, especially for large-scale circuits. The accuracy of the algorithms is furthermore increased using longer numerical data. First, a long double precision sparse algorithm is compared with the double precision sparse and full-matrix ones. Further, the application of a suitable multiple-precision arithmetic library is evaluated. Finally, the use of longer numerical data to eliminate possible imprecision of the multiple eigenvalues is evaluated.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82947928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399727
A. Jones, R. Hoare, I. Kourtev, Joshua Fazekas, D. Kusic, J. Foster, Sedric Boddie, Ahmed Muaydh
Current FPGA architectures are heterogeneous, containing tens of thousands of logic elements and hundreds of embedded multipliers and memory units. However, efficiently utilizing these resources requires hardware designers and complex computer aided design tools. The paper describes several multi-processor architectures implemented on an FPGA, including a 64-way single interface multiple data (SIMD) and a variable size very long instruction word (VLIW) architecture. The design and synthesis of the target architectures are presented and compared for scalability and achieving parallelism. The performance and chip utilization of a shared register file is examined for different numbers of VLIW processing elements. The associated compilation flow is described based on the Trimaran VLIW compiler which achieves explicitly parallel instructions from C code. Benchmarks from the Media-Bench suite are being used to test the performance of the parallelism of both the software and hardware components.
{"title":"A 64-way VLIW/SIMD FPGA architecture and design flow","authors":"A. Jones, R. Hoare, I. Kourtev, Joshua Fazekas, D. Kusic, J. Foster, Sedric Boddie, Ahmed Muaydh","doi":"10.1109/ICECS.2004.1399727","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399727","url":null,"abstract":"Current FPGA architectures are heterogeneous, containing tens of thousands of logic elements and hundreds of embedded multipliers and memory units. However, efficiently utilizing these resources requires hardware designers and complex computer aided design tools. The paper describes several multi-processor architectures implemented on an FPGA, including a 64-way single interface multiple data (SIMD) and a variable size very long instruction word (VLIW) architecture. The design and synthesis of the target architectures are presented and compared for scalability and achieving parallelism. The performance and chip utilization of a shared register file is examined for different numbers of VLIW processing elements. The associated compilation flow is described based on the Trimaran VLIW compiler which achieves explicitly parallel instructions from C code. Benchmarks from the Media-Bench suite are being used to test the performance of the parallelism of both the software and hardware components.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89478126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399766
A. Fish, Vladislav Mosheyev, Vitali Linkovsky, O. Yadid-Pecht
Various implementations of D-flip-flops (DFF) for shift register designs in CMOS image sensors are proposed. Driven by requirements of low-area and low-power dissipation, the presented FF allow implementation of power-efficient shift registers, used for signal readout control and windows of interest definition in CMOS image sensors and are optimized for operation at low frequencies. Power dissipation of the presented DFF is significantly reduced by leakage control using the stack effect. A variety of DFF and a shift-register, using the stacking effect approach, have been implemented in 0.18 /spl mu/m standard CMOS technology to compare the proposed DFF and shift-register structures with existing alternatives, showing an up to 63 % reduction in power dissipation of a shift-register at 30 Hz frequency. Operation of the proposed circuits is discussed and simulation results are reported.
{"title":"Ultra low-power DFF based shift registers design for CMOS image sensors applications","authors":"A. Fish, Vladislav Mosheyev, Vitali Linkovsky, O. Yadid-Pecht","doi":"10.1109/ICECS.2004.1399766","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399766","url":null,"abstract":"Various implementations of D-flip-flops (DFF) for shift register designs in CMOS image sensors are proposed. Driven by requirements of low-area and low-power dissipation, the presented FF allow implementation of power-efficient shift registers, used for signal readout control and windows of interest definition in CMOS image sensors and are optimized for operation at low frequencies. Power dissipation of the presented DFF is significantly reduced by leakage control using the stack effect. A variety of DFF and a shift-register, using the stacking effect approach, have been implemented in 0.18 /spl mu/m standard CMOS technology to compare the proposed DFF and shift-register structures with existing alternatives, showing an up to 63 % reduction in power dissipation of a shift-register at 30 Hz frequency. Operation of the proposed circuits is discussed and simulation results are reported.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83348180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399601
V. Ivanov, Junlin Zhou, I. Filanovsky
A CMOS operational amplifier that has a 100 dB CMRR (common mode rejection ratio) is described. This is achieved by combining the high output impedance tail current source with control of the drain-source voltage of the input transistors. The common-mode input signal range includes the negative rail voltage. This is obtained by applying the controlled bulk biasing of both input and cascoding transistors. The amplifier consists of two gain stages connected via cascoded current mirrors with voltage gain boost. The suppression of impact ionization current in the output stage improves the gain by more than 20 dB.
{"title":"A 100 dB CMRR CMOS operational amplifier with single-supply capability","authors":"V. Ivanov, Junlin Zhou, I. Filanovsky","doi":"10.1109/ICECS.2004.1399601","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399601","url":null,"abstract":"A CMOS operational amplifier that has a 100 dB CMRR (common mode rejection ratio) is described. This is achieved by combining the high output impedance tail current source with control of the drain-source voltage of the input transistors. The common-mode input signal range includes the negative rail voltage. This is obtained by applying the controlled bulk biasing of both input and cascoding transistors. The amplifier consists of two gain stages connected via cascoded current mirrors with voltage gain boost. The suppression of impact ionization current in the output stage improves the gain by more than 20 dB.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77839438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：