Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399707
S. Greenberg, Ido Bloch, M. Horwitz, A. Maman
Defining the optimal clock-distribution network in VLSI is one of the most important aspects of high-speed SoC design. The existing design flows for clock tree network implementation are manual based and require long development cycle time. This long and iterative design flow is not optimized in terms of: clock-skew, insertion delay, clock signal rise/fall time, power dissipation, route resources, sensitivity to technology/design variations and time to market. This paper demonstrates a new approach which uses preliminary HSPICE simulations and dramatically improves the clock tree performance. This is done by smartly choosing the following parameters: number of driver levels, driver size, wire width/space and wire length between levels. These parameters are used as inputs to an automatic clock tree synthesis tool in order to get better results by the automatic synthesis tool. This approach is applied to a chip level clock tree network of the new Freescale Semiconductor MSC8122 Quad Core DSP (500 MHz, 90 nm CMOS technology, 0.9686 cm/spl times/1.1792 cm die size). This results in saving 12% power dissipation and 15% route area without performance decreasing compared to the manual based flow.
{"title":"Optimization of chip level clock tree performance by using simultaneous drivers and wire sizing","authors":"S. Greenberg, Ido Bloch, M. Horwitz, A. Maman","doi":"10.1109/ICECS.2004.1399707","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399707","url":null,"abstract":"Defining the optimal clock-distribution network in VLSI is one of the most important aspects of high-speed SoC design. The existing design flows for clock tree network implementation are manual based and require long development cycle time. This long and iterative design flow is not optimized in terms of: clock-skew, insertion delay, clock signal rise/fall time, power dissipation, route resources, sensitivity to technology/design variations and time to market. This paper demonstrates a new approach which uses preliminary HSPICE simulations and dramatically improves the clock tree performance. This is done by smartly choosing the following parameters: number of driver levels, driver size, wire width/space and wire length between levels. These parameters are used as inputs to an automatic clock tree synthesis tool in order to get better results by the automatic synthesis tool. This approach is applied to a chip level clock tree network of the new Freescale Semiconductor MSC8122 Quad Core DSP (500 MHz, 90 nm CMOS technology, 0.9686 cm/spl times/1.1792 cm die size). This results in saving 12% power dissipation and 15% route area without performance decreasing compared to the manual based flow.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85824102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399621
N. Sommer, Itay Lusky, M. Miller
Communication systems that employ baseband transmission (i.e. signal spectrum centered around 0 Hz) may suffer from the baseline wander (BLW) phenomenon. This phenomenon occurs when the signal has to pass through a highpass filter element in the transmission path (e.g. a transformer in the line interface). A long sequence of symbols with constant value should generate a signal with constant level, but the signal will decay towards zero due to the highpass element. An example of a communication standard where baseband transmission is used with a DC-coupled channel is Ethernet. It can be shown that for baseband pulse amplitude modulation (PAM), the baseline wander phenomenon increases the dynamic range of the signal by a factor of 2, in worst case. This increases the cost of the receiver (for example, another bit may be needed in the analog to digital converter). However, the signal will reach its extreme values with very low probability, so it seems wasteful to design for worst case. It may be more economical to design for a smaller dynamic range, but then there must be a way to understand the probability that the signal will exceed this range. This can be done by using the probability distribution of the signal in the presence of BLW, which is calculated approximately in this paper.
{"title":"Analysis of the probability distribution of the baseline wander effect for baseband PAM transmission with application to gigabit Ethernet","authors":"N. Sommer, Itay Lusky, M. Miller","doi":"10.1109/ICECS.2004.1399621","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399621","url":null,"abstract":"Communication systems that employ baseband transmission (i.e. signal spectrum centered around 0 Hz) may suffer from the baseline wander (BLW) phenomenon. This phenomenon occurs when the signal has to pass through a highpass filter element in the transmission path (e.g. a transformer in the line interface). A long sequence of symbols with constant value should generate a signal with constant level, but the signal will decay towards zero due to the highpass element. An example of a communication standard where baseband transmission is used with a DC-coupled channel is Ethernet. It can be shown that for baseband pulse amplitude modulation (PAM), the baseline wander phenomenon increases the dynamic range of the signal by a factor of 2, in worst case. This increases the cost of the receiver (for example, another bit may be needed in the analog to digital converter). However, the signal will reach its extreme values with very low probability, so it seems wasteful to design for worst case. It may be more economical to design for a smaller dynamic range, but then there must be a way to understand the probability that the signal will exceed this range. This can be done by using the probability distribution of the signal in the presence of BLW, which is calculated approximately in this paper.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88919134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399649
T. A. Holz, J. Harris
We introduce the Freeman model - a nonlinear dynamic system proposed to model the operation of the cortex - and explain how its interconnected nature complicates physical realizations. We propose changing the Freeman model so that it is a spiking network in order to alleviate the implementation problems while preserving the important dynamic characteristics. We include simulation results showing that our modified spiking model demonstrates those dynamics. Finally, we show experimental results from a VLSI chip implementation of the spiking model as a proof-of-concept.
{"title":"Towards a spiking VLSI implementation of Freeman's olfactory model","authors":"T. A. Holz, J. Harris","doi":"10.1109/ICECS.2004.1399649","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399649","url":null,"abstract":"We introduce the Freeman model - a nonlinear dynamic system proposed to model the operation of the cortex - and explain how its interconnected nature complicates physical realizations. We propose changing the Freeman model so that it is a spiking network in order to alleviate the implementation problems while preserving the important dynamic characteristics. We include simulation results showing that our modified spiking model demonstrates those dynamics. Finally, we show experimental results from a VLSI chip implementation of the spiking model as a proof-of-concept.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74160628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399731
Eyal Segev, Sharon Goldshlager, H. Miller, Oren Shua, Olga Sher, S. Greenberg
Logic design has become very complex in term of logic functionality. System-on-chip (SOC) designs are an integration of multiple modules and cores. In many cases, SOC integration is a result of integrating a few chips together. Each piece (module or core) must be verified separately (stand alone) prior to chip level verification. Standalone logic verification of the design is one of the most important steps in the overall design effort. Following the increase of the amount of functionality at each module, the logic verification effort has become a very resource-consuming task. Two logic verification methods are commonly used when verifying a SOC, simulation based verification and formal based verification. The two methods are explored and compared with respect to the time required for setup and running the environment, ease of debugging the reported failures, power, coverage and confidence level. Our main goal is to establish criteria for optimal use of simulation based verification and formal based verification and implement both methods on a block for a PCMCIA interface card. We have derived important conclusions concerning the matching of these methods for the verification of blocks of a similar type.
{"title":"Evaluating and comparing simulation verification vs. formal verification approach on block level design","authors":"Eyal Segev, Sharon Goldshlager, H. Miller, Oren Shua, Olga Sher, S. Greenberg","doi":"10.1109/ICECS.2004.1399731","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399731","url":null,"abstract":"Logic design has become very complex in term of logic functionality. System-on-chip (SOC) designs are an integration of multiple modules and cores. In many cases, SOC integration is a result of integrating a few chips together. Each piece (module or core) must be verified separately (stand alone) prior to chip level verification. Standalone logic verification of the design is one of the most important steps in the overall design effort. Following the increase of the amount of functionality at each module, the logic verification effort has become a very resource-consuming task. Two logic verification methods are commonly used when verifying a SOC, simulation based verification and formal based verification. The two methods are explored and compared with respect to the time required for setup and running the environment, ease of debugging the reported failures, power, coverage and confidence level. Our main goal is to establish criteria for optimal use of simulation based verification and formal based verification and implement both methods on a block for a PCMCIA interface card. We have derived important conclusions concerning the matching of these methods for the verification of blocks of a similar type.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74034627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399618
A. Ascoli, P. Curran, O. Feely
Log-domain filters are an intriguing form of current-mode circuit in which the large-signal exponential current-voltage relationship of the bipolar junction transistor is used first to convert the input currents to logarithmic form, where the analog processing takes place, and then to map the output voltage waveforms back to the current domain at the end of the filtering process. The log-domain filter synthesis technique can be extremely useful in the design of chaotic oscillators suitable for low-power high-speed integrated circuit implementations. This paper presents a new third-order log-domain chaotic oscillator, which may be used in chaos-based communication systems. Although the design of the proposed oscillator stems from a known nonlinear dynamical system which may be subject to chaotic oscillations, its dynamics differ from those of the model and, as a result, are worth investigating.
{"title":"New chaotic third-order log-domain oscillator with tanh nonlinearity","authors":"A. Ascoli, P. Curran, O. Feely","doi":"10.1109/ICECS.2004.1399618","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399618","url":null,"abstract":"Log-domain filters are an intriguing form of current-mode circuit in which the large-signal exponential current-voltage relationship of the bipolar junction transistor is used first to convert the input currents to logarithmic form, where the analog processing takes place, and then to map the output voltage waveforms back to the current domain at the end of the filtering process. The log-domain filter synthesis technique can be extremely useful in the design of chaotic oscillators suitable for low-power high-speed integrated circuit implementations. This paper presents a new third-order log-domain chaotic oscillator, which may be used in chaos-based communication systems. Although the design of the proposed oscillator stems from a known nonlinear dynamical system which may be subject to chaotic oscillations, its dynamics differ from those of the model and, as a result, are worth investigating.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77756622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399713
Simon R. Cooper, A. Kuperman, R. Rabinovici
This paper presents a motion control system which employs a load decoder, capable of analyzing the load value and changes, applied to the motor's rotor, decoding them into an instruction set for the controller input. The system is implemented in a field programmable gate array (FPGA) device, which have recently become affordable for implementing complicated motion control algorithms. All motion control logic is implemented in hardware (no software at all) and executes functions by the dedicated hardware logic. In such a case execution time becomes inherently fast and deterministic. This complicates the design, compared to the rather simple solution in software on DSP but offers reduced control system price which is essential for mass production applications. Moreover it can be easily transformed into ASIC for further cost reduction.
{"title":"Controlling an electrical motion system by a load instruction decoding algorithm using FPGA","authors":"Simon R. Cooper, A. Kuperman, R. Rabinovici","doi":"10.1109/ICECS.2004.1399713","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399713","url":null,"abstract":"This paper presents a motion control system which employs a load decoder, capable of analyzing the load value and changes, applied to the motor's rotor, decoding them into an instruction set for the controller input. The system is implemented in a field programmable gate array (FPGA) device, which have recently become affordable for implementing complicated motion control algorithms. All motion control logic is implemented in hardware (no software at all) and executes functions by the dedicated hardware logic. In such a case execution time becomes inherently fast and deterministic. This complicates the design, compared to the rather simple solution in software on DSP but offers reduced control system price which is essential for mass production applications. Moreover it can be easily transformed into ASIC for further cost reduction.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77934564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399720
O. Cohen, A. Shai, Y. Nemirovsky
In this paper, we present a novel scheme for designing and fabricating a base chip, which is an approximation of a pyramid shape, and is not limited by the natural slope of 54.7/spl deg/ obtained with wet anisotropic etching of silicon. The application for such a pyramid shape, in our case, is for a single axis scanning micro mirror. The paper presents the methodology for designing and fabricating a surface with an arbitrary slope, as required by the application. In our case, it is an approximation of a desired very moderate slope. The moderate slope serves as an electrostatic actuator with relatively low operating voltage. On top of the base, we bond a mirror chip that includes the opposite side of the actuator, the reflector of the mirror, the mechanical structure of the mirror and the hinges. We present in this paper the motivation to use a pyramidal shaped base. The design is simple and requires knowledge of etch rates in several crystal planes, which can be easily measured. The fabrication tools and methods used herein are based on wet etching of silicon wafers. There is no need for DRIE processes or SOI wafers.
{"title":"A novel design and fabrication method of a pyramidal shape chip for scanning micro mirror","authors":"O. Cohen, A. Shai, Y. Nemirovsky","doi":"10.1109/ICECS.2004.1399720","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399720","url":null,"abstract":"In this paper, we present a novel scheme for designing and fabricating a base chip, which is an approximation of a pyramid shape, and is not limited by the natural slope of 54.7/spl deg/ obtained with wet anisotropic etching of silicon. The application for such a pyramid shape, in our case, is for a single axis scanning micro mirror. The paper presents the methodology for designing and fabricating a surface with an arbitrary slope, as required by the application. In our case, it is an approximation of a desired very moderate slope. The moderate slope serves as an electrostatic actuator with relatively low operating voltage. On top of the base, we bond a mirror chip that includes the opposite side of the actuator, the reflector of the mirror, the mechanical structure of the mirror and the hinges. We present in this paper the motivation to use a pyramidal shaped base. The design is simple and requires knowledge of etch rates in several crystal planes, which can be easily measured. The fabrication tools and methods used herein are based on wet etching of silicon wafers. There is no need for DRIE processes or SOI wafers.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78232256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399737
D. Abookasis, Joseph Rosen
A new method of synthesizing computer-generated holograms of 3D objects is proposed. Several projections of the 3D object are numerically processed to yield a 2D complex function, which is then encoded as a computer-generated hologram. When this hologram is illuminated by a plane wave, a 3D real image of the object is reconstructed. Although the hologram initially belongs to the type of Fourier holograms, Fresnel and image holograms are also generated by computing the propagation of the wave front from the Fourier plane to any other desired plane. Computer and optical constructions of 3D objects, both of which show the feasibility of the proposed approach, are presented herein.
{"title":"Computer aided design using CGH of a three-dimensional objects","authors":"D. Abookasis, Joseph Rosen","doi":"10.1109/ICECS.2004.1399737","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399737","url":null,"abstract":"A new method of synthesizing computer-generated holograms of 3D objects is proposed. Several projections of the 3D object are numerically processed to yield a 2D complex function, which is then encoded as a computer-generated hologram. When this hologram is illuminated by a plane wave, a 3D real image of the object is reconstructed. Although the hologram initially belongs to the type of Fourier holograms, Fresnel and image holograms are also generated by computing the propagation of the wave front from the Fourier plane to any other desired plane. Computer and optical constructions of 3D objects, both of which show the feasibility of the proposed approach, are presented herein.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85768271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399607
S. Levantino, A. Bonfanti, L. Romanò, C. Samori, A. Lacaita
The adoption of differential tuning in oscillators provides cancellation of common-mode disturbances, and thus, it is expected to lower phase noise and power supply pulling. However, the direct application of differential tuning increases the capacitor nonlinearity, and in turn, it can raise the flicker-induced phase noise. This upconversion mechanism, based on non-linearities, is quantitatively assessed and a modified configuration circumventing this phenomenon is proposed and applied to the design of a 1.8-GHz LC oscillator in 0.35-/spl mu/m CMOS technology. The simulated 1/f/sup 3/, phase noise is reduced by 20 dB, without impairing the tuning range and supply pulling.
{"title":"Differential tuning oscillators with reduced flicker noise upconversion","authors":"S. Levantino, A. Bonfanti, L. Romanò, C. Samori, A. Lacaita","doi":"10.1109/ICECS.2004.1399607","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399607","url":null,"abstract":"The adoption of differential tuning in oscillators provides cancellation of common-mode disturbances, and thus, it is expected to lower phase noise and power supply pulling. However, the direct application of differential tuning increases the capacitor nonlinearity, and in turn, it can raise the flicker-induced phase noise. This upconversion mechanism, based on non-linearities, is quantitatively assessed and a modified configuration circumventing this phenomenon is proposed and applied to the design of a 1.8-GHz LC oscillator in 0.35-/spl mu/m CMOS technology. The simulated 1/f/sup 3/, phase noise is reduced by 20 dB, without impairing the tuning range and supply pulling.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86074859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399685
B. G. Salomon, H. Ur
Signal decomposition with an overcomplete dictionary is nonunique. Computation of the best approximation is known to be NP-hard problem. The matching pursuit (MP) algorithm is a popular iterative greedy algorithm that finds a sub-optimal approximation, by picking at each iteration the vector that best correlates with the present residual. Choosing approximation vectors by optimizing a correlation inner product can produce a loss of time and frequency resolution. We propose a modified MP, based on a post processing step applied on the resulting MP approximation, using the backward greedy algorithm, to achieve higher resolution than the original MP.
{"title":"Sparse approximations with a high resolution greedy algorithm","authors":"B. G. Salomon, H. Ur","doi":"10.1109/ICECS.2004.1399685","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399685","url":null,"abstract":"Signal decomposition with an overcomplete dictionary is nonunique. Computation of the best approximation is known to be NP-hard problem. The matching pursuit (MP) algorithm is a popular iterative greedy algorithm that finds a sub-optimal approximation, by picking at each iteration the vector that best correlates with the present residual. Choosing approximation vectors by optimizing a correlation inner product can produce a loss of time and frequency resolution. We propose a modified MP, based on a post processing step applied on the resulting MP approximation, using the backward greedy algorithm, to achieve higher resolution than the original MP.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89929155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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