Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399675
C.L. Rogers, J. Harris
This paper discusses a low-power spike detection circuit, which reduces bandwidth from neural recordings by only outputting a short pulse at each neural spike time. Communication bandwidth is dramatically reduced to the number of spikes. The principal idea is to use two low pass filters, one with a higher cutoff frequency to remove high frequency noise and the other with a lower cutoff frequency to create a local average. When the difference between the signal and the local average rises above a threshold, a spike is detected. The circuit uses subthreshold CMOS to keep the power consumption low enough for integration of many channels in an implanted device. This spike detection method shows promising results towards a robust and unsupervised algorithm that is lower power and more compact than existing spike detection methods.
{"title":"A low-power analog spike detector for extracellular neural recordings","authors":"C.L. Rogers, J. Harris","doi":"10.1109/ICECS.2004.1399675","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399675","url":null,"abstract":"This paper discusses a low-power spike detection circuit, which reduces bandwidth from neural recordings by only outputting a short pulse at each neural spike time. Communication bandwidth is dramatically reduced to the number of spikes. The principal idea is to use two low pass filters, one with a higher cutoff frequency to remove high frequency noise and the other with a lower cutoff frequency to create a local average. When the difference between the signal and the local average rises above a threshold, a spike is detected. The circuit uses subthreshold CMOS to keep the power consumption low enough for integration of many channels in an implanted device. This spike detection method shows promising results towards a robust and unsupervised algorithm that is lower power and more compact than existing spike detection methods.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"17 1","pages":"290-293"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80722642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399698
Michal Silbermintz, Amir Sahar, Itay Peled, M. Anschel, Emil Watralov, H. Miller, E. Weisberger
The paper introduces a system-on-chip (SOC) modeling methodology that enables the use of a single model for multiple purposes throughout a project's life cycle, starting from the architectural definition phase, continuing with the microarchitectural optimization and ending with the software development and optimization phase. These different purposes are served by enabling multiple approaches for modeling applications, providing capabilities for configuring and refining the hardware model and reaching a high accuracy level while maintaining a good simulation speed.
{"title":"SOC modeling methodology for architectural exploration and software development","authors":"Michal Silbermintz, Amir Sahar, Itay Peled, M. Anschel, Emil Watralov, H. Miller, E. Weisberger","doi":"10.1109/ICECS.2004.1399698","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399698","url":null,"abstract":"The paper introduces a system-on-chip (SOC) modeling methodology that enables the use of a single model for multiple purposes throughout a project's life cycle, starting from the architectural definition phase, continuing with the microarchitectural optimization and ending with the software development and optimization phase. These different purposes are served by enabling multiple approaches for modeling applications, providing capabilities for configuring and refining the hardware model and reaching a high accuracy level while maintaining a good simulation speed.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"1993 1","pages":"383-386"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82393053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399736
L. Sudakov-Boreysha, A. Morgenshtein, U. Dinnar, Y. Nemirovsky
This work presents the main challenges in ISFET encapsulation. It analyzes SU8 drawbacks as an encapsulant and presents a novel flip-chip bonding packaging concept.
{"title":"ISFET CMOS compatible design and encapsulation challenges","authors":"L. Sudakov-Boreysha, A. Morgenshtein, U. Dinnar, Y. Nemirovsky","doi":"10.1109/ICECS.2004.1399736","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399736","url":null,"abstract":"This work presents the main challenges in ISFET encapsulation. It analyzes SU8 drawbacks as an encapsulant and presents a novel flip-chip bonding packaging concept.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"30 1","pages":"535-538"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89535711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399674
V. Varshavsky, I. Levin, V. Marakhovsky, A. Ruderman, N. Kravchenko
The functional completeness of a summing amplifier with saturation in an arbitrary value multi-valued logic, proven in previous works, gives a theoretical background for analog implementation of fuzzy devices. Practical design techniques for multi-valued analog fuzzy controllers still have to be developed. Compared with the traditional approach, analog CMOS fuzzy controller implementation has the advantages of higher speed, lower power consumption, smaller die area and more. This paper introduces some special design techniques and provides design examples for an industrial fuzzy controller implementation confirmed by SPICE simulations.
{"title":"Fuzzy decision diagram realization by analog CMOS summing amplifiers","authors":"V. Varshavsky, I. Levin, V. Marakhovsky, A. Ruderman, N. Kravchenko","doi":"10.1109/ICECS.2004.1399674","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399674","url":null,"abstract":"The functional completeness of a summing amplifier with saturation in an arbitrary value multi-valued logic, proven in previous works, gives a theoretical background for analog implementation of fuzzy devices. Practical design techniques for multi-valued analog fuzzy controllers still have to be developed. Compared with the traditional approach, analog CMOS fuzzy controller implementation has the advantages of higher speed, lower power consumption, smaller die area and more. This paper introduces some special design techniques and provides design examples for an industrial fuzzy controller implementation confirmed by SPICE simulations.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"173 1","pages":"286-289"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77495498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399626
L. Hernández, P. Rombouts, E. Prefasi, S. Patón, Mario Garcia, C. Lopez
This work presents a prototype low pass continuous time sigma delta modulator which uses transmission lines in its loop filter rather than capacitive integrators. As has been shown in prior theoretical work, such a structure allows us to desensitize the modulator against clock jitter and excess loop delay. The prototype single-bit modulator was designed for an oversampling ratio of 128. Clocked at 53.7 MHz it achieves a peak SNR of 67 dB. In an experiment with an excessive clock jitter of 1% of the clock period, the SNDR is degraded by only 5dB compared to the case without jitter. This is 15dB better than an equivalent modulator with capacitive integrators.
{"title":"A jitter insensitive continuous-time /spl Sigma//spl Delta/ modulator using transmission lines","authors":"L. Hernández, P. Rombouts, E. Prefasi, S. Patón, Mario Garcia, C. Lopez","doi":"10.1109/ICECS.2004.1399626","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399626","url":null,"abstract":"This work presents a prototype low pass continuous time sigma delta modulator which uses transmission lines in its loop filter rather than capacitive integrators. As has been shown in prior theoretical work, such a structure allows us to desensitize the modulator against clock jitter and excess loop delay. The prototype single-bit modulator was designed for an oversampling ratio of 128. Clocked at 53.7 MHz it achieves a peak SNR of 67 dB. In an experiment with an excessive clock jitter of 1% of the clock period, the SNDR is degraded by only 5dB compared to the case without jitter. This is 15dB better than an equivalent modulator with capacitive integrators.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"84 1","pages":"109-112"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79942561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399724
A. Telli, S. Demir, M. Askar
Inductors are essential elements for RF design. For RFIC design, bondwires, planar solenoidal and planar spiral inductors are available. Due to some limitations of bondwires and planar solenoidal inductors, planar spiral inductors are the most popular ones. Designers try to get accurate lumped element models for planar spiral inductors in order to be able to simulate the circuit performance correctly before the integrated circuit is manufactured. Planar spiral inductor measurement methods are discussed, and the comparison between lumped element model simulation results and experimental measurement results are given. The results of this study show that it is possible to model planar spiral inductors with lumped element circuit models, parameters of which can be calculated by basic, but accurate, expressions.
{"title":"Practical performance of planar spiral inductors","authors":"A. Telli, S. Demir, M. Askar","doi":"10.1109/ICECS.2004.1399724","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399724","url":null,"abstract":"Inductors are essential elements for RF design. For RFIC design, bondwires, planar solenoidal and planar spiral inductors are available. Due to some limitations of bondwires and planar solenoidal inductors, planar spiral inductors are the most popular ones. Designers try to get accurate lumped element models for planar spiral inductors in order to be able to simulate the circuit performance correctly before the integrated circuit is manufactured. Planar spiral inductor measurement methods are discussed, and the comparison between lumped element model simulation results and experimental measurement results are given. The results of this study show that it is possible to model planar spiral inductors with lumped element circuit models, parameters of which can be calculated by basic, but accurate, expressions.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"90 1","pages":"487-490"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87285668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399666
Sanghoon Hwang, Minkyu Song
A 10-b 500 MSPS current-steering CMOS digital-to-analog converter with internal termination resistors is presented. In order to improve the device-mismatching problem of internal termination resistors, a self-calibrated current bias circuit is designed. With the self-calibrated current bias circuit, the gain error of the output voltage swing is reduced within 0.5%. Further, for the purpose of reducing glitch noise, a novel current switch based on a deglitching circuit is proposed. A 10-b CMOS DAC has been fabricated with a 3 V, 0.35 /spl mu/m technology, and it consumes 45 mW. The measured SFDR (spurious free dynamic range) is about 65 dB, when the input signal is about 8 MHz at 500 MHz clock frequency.
{"title":"A 10-b 500 MSPS current-steering CMOS D/A converter with a self-calibrated current biasing technique","authors":"Sanghoon Hwang, Minkyu Song","doi":"10.1109/ICECS.2004.1399666","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399666","url":null,"abstract":"A 10-b 500 MSPS current-steering CMOS digital-to-analog converter with internal termination resistors is presented. In order to improve the device-mismatching problem of internal termination resistors, a self-calibrated current bias circuit is designed. With the self-calibrated current bias circuit, the gain error of the output voltage swing is reduced within 0.5%. Further, for the purpose of reducing glitch noise, a novel current switch based on a deglitching circuit is proposed. A 10-b CMOS DAC has been fabricated with a 3 V, 0.35 /spl mu/m technology, and it consumes 45 mW. The measured SFDR (spurious free dynamic range) is about 65 dB, when the input signal is about 8 MHz at 500 MHz clock frequency.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"24 1","pages":"254-257"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73575890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399636
A. Fish, A. Belenky, O. Yadid-Pecht
A novel low power global shutter CMOS active pixel sensor (APS) with ultra-high dynamic range is presented. Incorporating a sample-and-hold element in each pixel, the sensor enables imaging of fast moving objects in the field of view. An adaptive exposure time is automatically applied to each pixel, according to the local illumination intensity level, significantly increasing the dynamic range of the sensor. Driven by low-power dissipation requirements, the proposed pixel is operated by low voltage supply (1.8V). System architecture and operation are discussed and simulation results in a standard 0.35 /spl mu/m CMOS technology are presented.
提出一种具有超高动态范围的低功耗全局快门CMOS有源像素传感器(APS)。在每个像素中加入一个采样保持元件，传感器可以对视场中快速移动的物体进行成像。自适应曝光时间自动应用于每个像素，根据当地的照明强度水平，显著增加传感器的动态范围。在低功耗需求的驱动下，所提出的像素采用低电压供电(1.8V)。讨论了系统的结构和工作原理，并给出了在标准0.35 /spl μ m CMOS工艺下的仿真结果。
{"title":"Low power global shutter CMOS active pixel image sensor with ultra-high dynamic range","authors":"A. Fish, A. Belenky, O. Yadid-Pecht","doi":"10.1109/ICECS.2004.1399636","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399636","url":null,"abstract":"A novel low power global shutter CMOS active pixel sensor (APS) with ultra-high dynamic range is presented. Incorporating a sample-and-hold element in each pixel, the sensor enables imaging of fast moving objects in the field of view. An adaptive exposure time is automatically applied to each pixel, according to the local illumination intensity level, significantly increasing the dynamic range of the sensor. Driven by low-power dissipation requirements, the proposed pixel is operated by low voltage supply (1.8V). System architecture and operation are discussed and simulation results in a standard 0.35 /spl mu/m CMOS technology are presented.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"17 1","pages":"149-152"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75150425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399706
D. Velenis, Ramyashree Sundaresha, E. Friedman
Controlling the delay of a signal in the presence of various noise sources, process parameter variations, and environmental effects represents a fundamental problem in the design of high performance synchronous circuits. The effects of device parameter variations on the signal propagation delay of a CMOS buffer are described in this paper. It is shown that delay uncertainty is introduced due to variations in the current flow through a buffer. In addition, the variations in the parasitic resistance and capacitance of an interconnect line also affect the buffer delay. A design methodology that reduces the delay uncertainty of signals propagating along buffer-driven interconnect lines is presented. The proposed methodology increases the current flow sourced by a buffer to reduce the sensitivity of the delay on device and interconnect parameter variations.
{"title":"Buffer sizing for delay uncertainty induced by process variations","authors":"D. Velenis, Ramyashree Sundaresha, E. Friedman","doi":"10.1109/ICECS.2004.1399706","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399706","url":null,"abstract":"Controlling the delay of a signal in the presence of various noise sources, process parameter variations, and environmental effects represents a fundamental problem in the design of high performance synchronous circuits. The effects of device parameter variations on the signal propagation delay of a CMOS buffer are described in this paper. It is shown that delay uncertainty is introduced due to variations in the current flow through a buffer. In addition, the variations in the parasitic resistance and capacitance of an interconnect line also affect the buffer delay. A design methodology that reduces the delay uncertainty of signals propagating along buffer-driven interconnect lines is presented. The proposed methodology increases the current flow sourced by a buffer to reduce the sensitivity of the delay on device and interconnect parameter variations.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"105 1","pages":"415-418"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76418128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399734
Kio Kim, N. Intrator, N. Neretti
We introduce an algorithm for image registration and mosaicing on underwater sonar image sequences characterized by a high noise level, inhomogeneous illumination and low frame rate. For a planar surface viewed through a pinhole camera undergoing translational and rotational motion, registration can be obtained via a projective transformation. For an acoustic camera, we show that, under the same conditions, an affine transformation is a good approximation. We propose a novel image fusion, which maximizes the signal-to-noise ratio of the mosaic image. The full procedure includes illumination correction, feature based transformation estimation, and image fusion for mosaicing.
{"title":"Image registration and mosaicing of noisy acoustic camera images","authors":"Kio Kim, N. Intrator, N. Neretti","doi":"10.1109/ICECS.2004.1399734","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399734","url":null,"abstract":"We introduce an algorithm for image registration and mosaicing on underwater sonar image sequences characterized by a high noise level, inhomogeneous illumination and low frame rate. For a planar surface viewed through a pinhole camera undergoing translational and rotational motion, registration can be obtained via a projective transformation. For an acoustic camera, we show that, under the same conditions, an affine transformation is a good approximation. We propose a novel image fusion, which maximizes the signal-to-noise ratio of the mosaic image. The full procedure includes illumination correction, feature based transformation estimation, and image fusion for mosaicing.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"1 1","pages":"527-530"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81583603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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