Semiconductor technology has known an exponential evolution during last decades, being the key for the further evolution of micro- and nanoelectronics and the commercial breakthrough of state-of-the-art innovative and sometimes disruptive applications. Microelectronics is fully integrated in different areas of everyday life, such as healthcare, automotive, communication, safety and security, smart energy, smart cities, retail business, etc. This evolution implies extensive research towards new materials (gate dielectrics, metallization, III-V materials, wide bandgap approaches, etc.), alternative device architectures (e.g., FinFETs, TFETs, negative capacitance, gate-all-around, nanowires, nanosheets in both horizontal or vertical configurations, SOI approaches) and optimized system functionality and density (3D integration, through silicon vias, sequential integration, SOC, and others). Besides advanced 2- and 3D transistors, also solar cells, bio-devices, organic devices are of great importance. Also the operation field of the devices, including frequency range, noise performance and temperature range, has to be optimized in function of the envisaged digital or analog application. The state-of-the-art, trends and challenges encountered during the fabrication and operation of different emerging technologies are reviewed in this special issue. Much attention is given to the excellent research being performed by different research groups at Brazilian universities and international research centers.
{"title":"Guest Editors' Words","authors":"C. Claeys, J. Martino","doi":"10.29292/jics.v17i2.634","DOIUrl":"https://doi.org/10.29292/jics.v17i2.634","url":null,"abstract":"Semiconductor technology has known an exponential evolution during last decades, being the key for the further evolution of micro- and nanoelectronics and the commercial breakthrough of state-of-the-art innovative and sometimes disruptive applications. Microelectronics is fully integrated in different areas of everyday life, such as healthcare, automotive, communication, safety and security, smart energy, smart cities, retail business, etc. This evolution implies extensive research towards new materials (gate dielectrics, metallization, III-V materials, wide bandgap approaches, etc.), alternative device architectures (e.g., FinFETs, TFETs, negative capacitance, gate-all-around, nanowires, nanosheets in both horizontal or vertical configurations, SOI approaches) and optimized system functionality and density (3D integration, through silicon vias, sequential integration, SOC, and others). Besides advanced 2- and 3D transistors, also solar cells, bio-devices, organic devices are of great importance. Also the operation field of the devices, including frequency range, noise performance and temperature range, has to be optimized in function of the envisaged digital or analog application. The state-of-the-art, trends and challenges encountered during the fabrication and operation of different emerging technologies are reviewed in this special issue. Much attention is given to the excellent research being performed by different research groups at Brazilian universities and international research centers.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48507740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ariana Lacorte Caniato Serrano, Gustavo Marcati, Igor Abe, Gustavo Palomino, G. Rehder
This paper intends to make a brief presentation of in integrated circuits’ developments and efforts towards new wireless applications at the millimeter-wave frequencies band. Considering low-cost applications for the consumer market, it is shown that using only one technology is not desirable for cost and size reasons. The 3D integration becomes a necessity for the new applications in such frequencies, pushing forward alternative technologies and new 3D interconnection techniques.
{"title":"Millimeter-wave Wireless Integrated Systems: what to expect for future solutions","authors":"Ariana Lacorte Caniato Serrano, Gustavo Marcati, Igor Abe, Gustavo Palomino, G. Rehder","doi":"10.29292/jics.v17i2.627","DOIUrl":"https://doi.org/10.29292/jics.v17i2.627","url":null,"abstract":"This paper intends to make a brief presentation of in integrated circuits’ developments and efforts towards new wireless applications at the millimeter-wave frequencies band. Considering low-cost applications for the consumer market, it is shown that using only one technology is not desirable for cost and size reasons. The 3D integration becomes a necessity for the new applications in such frequencies, pushing forward alternative technologies and new 3D interconnection techniques.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44030724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To meet low power requirements for Internet of Things (IoT) applications, the power dissipation of RF transceivers must be very low. As the Low Noise Amplifier (LNA) is one of the most energy consuming parts of an RF receiver, its power optimization is necessary for modern IoT devices. This work presents a 170 $mu$W LNA capable of operating at 2.4 GHz when powered by a 0.4 V source. It is based on an inverter-based amplifier with improved gate bias voltage and automatic forward bulk biasing to operate at the moderated channel inversion level. A biasing metric is explored to analyze the best dimensions and bulk bias voltages for the NMOS transistor. Post-layout simulation results shown a 2.8 dB noise and competitive specification values compared to the state-of-the-art low-voltage LNAs.
{"title":"0.4 V Active Biased LNA for 2.4 GHz Low Energy RF Receivers","authors":"Giovana Ceolin, Lucas Compassi Severo","doi":"10.29292/jics.v17i2.559","DOIUrl":"https://doi.org/10.29292/jics.v17i2.559","url":null,"abstract":"To meet low power requirements for Internet of Things (IoT) applications, the power dissipation of RF transceivers must be very low. As the Low Noise Amplifier (LNA) is one of the most energy consuming parts of an RF receiver, its power optimization is necessary for modern IoT devices. This work presents a 170 $mu$W LNA capable of operating at 2.4 GHz when powered by a 0.4 V source. It is based on an inverter-based amplifier with improved gate bias voltage and automatic forward bulk biasing to operate at the moderated channel inversion level. A biasing metric is explored to analyze the best dimensions and bulk bias voltages for the NMOS transistor. Post-layout simulation results shown a 2.8 dB noise and competitive specification values compared to the state-of-the-art low-voltage LNAs.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47497432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tulio Pereira Bitencourt, Fábio Luís Livi Ramos, S. Bampi
With the increasing demand for video transmission through the Internet, video coding has become a key technology to allow this market's growth at a reduced cost. Moreover, with the inception of higher video resolutions (e.g., 4K, 8K) and their impact on video size, new video coding standards must tackle this issue to reduce video traffic demand on the global internet infrastructure. The AV1, a recently released royalties-free video coding format created by the Alliance for Open Media (AOMedia), reaches great compression rates but cannot accomplish real-time execution on software-only implementations due to its high complexity. This paper presents and analyzes AE-AV1, a high-performance 4-stage pipelined architecture to accelerate the AV1 arithmetic encoding process (part of the entropy encoder block) and make it capable of real-time execution. For the analysis, this work aims to rely on fully open-source Electronic Design Automation (EDA) tools and Package Design Kits (PDKs).
{"title":"AV1 Arithmetic Encoder Design on Open-Source EDA","authors":"Tulio Pereira Bitencourt, Fábio Luís Livi Ramos, S. Bampi","doi":"10.29292/jics.v17i2.564","DOIUrl":"https://doi.org/10.29292/jics.v17i2.564","url":null,"abstract":"With the increasing demand for video transmission through the Internet, video coding has become a key technology to allow this market's growth at a reduced cost. Moreover, with the inception of higher video resolutions (e.g., 4K, 8K) and their impact on video size, new video coding standards must tackle this issue to reduce video traffic demand on the global internet infrastructure. The AV1, a recently released royalties-free video coding format created by the Alliance for Open Media (AOMedia), reaches great compression rates but cannot accomplish real-time execution on software-only implementations due to its high complexity. This paper presents and analyzes AE-AV1, a high-performance 4-stage pipelined architecture to accelerate the AV1 arithmetic encoding process (part of the entropy encoder block) and make it capable of real-time execution. For the analysis, this work aims to rely on fully open-source Electronic Design Automation (EDA) tools and Package Design Kits (PDKs).","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45902024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The present study proposes a new nonisolated DC-DC high step-up converter for solar PV power plant applications using the voltage boosting technique. The output voltage gain of this converter is high and the voltage stress on the switch and diodes is acceptable. The proposed converter has a switch for easier control. Moreover, to achieve higher reliability, the converter uses a common ground between the load and source. Voltage stress analysis, proper component selection, and converter evaluation are performed in continuous conduction mode (CCM). Simulation results verify the theoretical concept.
{"title":"A Novel Topology of Nonisolated DC-DC High Step up Converters for Solar PV Power Plants","authors":"S. Hosseinikavkani, R. Sedaghati, A. Ghaedi","doi":"10.29292/jics.v17i2.604","DOIUrl":"https://doi.org/10.29292/jics.v17i2.604","url":null,"abstract":"The present study proposes a new nonisolated DC-DC high step-up converter for solar PV power plant applications using the voltage boosting technique. The output voltage gain of this converter is high and the voltage stress on the switch and diodes is acceptable. The proposed converter has a switch for easier control. Moreover, to achieve higher reliability, the converter uses a common ground between the load and source. Voltage stress analysis, proper component selection, and converter evaluation are performed in continuous conduction mode (CCM). Simulation results verify the theoretical concept.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42886069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Agopian, J. Martino, E. Simoen, R. Rooyackers, C. Claeys
In this work different generations of field effect tunneling transistor (TFET) are evaluated through DC digital and analog figures of merits. For TFET devices the main digital figure of merit is the subthreshold slope (SS), while for analog application the intrinsic voltage gain (AV) is the most important one. For the early generations, that are based on silicon, the SS does not reach values smaller than 60mV/dec at room temperature, however, the AV reaches values up to 80 dB, showing to be promising for analog applications. As the TFETs were being optimized for digital applications and consequently presenting better switching performance, the intrinsic voltage gain moves in the opposite direction. This opposite trend is related to which transport mechanism is predominant for each type of device. While III-V TFETs are more dependent on Band to Band Tunneling (BTBT), silicon devices are more relying on Trap-Assisted Tunneling (TAT). While BTBT allows for faster switching, TAT is less dependent on the drain electric field, so the former favors SS while the latter favors AV. Based on the good analog behavior of silicon channel TFETs, a two-stage operational transconductance amplifier (OTA) was designed with different TFET technologies and the compared results were discussed.
{"title":"Tunnel-FET Evolution and Applications for Analog Circuits","authors":"P. Agopian, J. Martino, E. Simoen, R. Rooyackers, C. Claeys","doi":"10.29292/jics.v17i2.631","DOIUrl":"https://doi.org/10.29292/jics.v17i2.631","url":null,"abstract":"In this work different generations of field effect tunneling transistor (TFET) are evaluated through DC digital and analog figures of merits. For TFET devices the main digital figure of merit is the subthreshold slope (SS), while for analog application the intrinsic voltage gain (AV) is the most important one. For the early generations, that are based on silicon, the SS does not reach values smaller than 60mV/dec at room temperature, however, the AV reaches values up to 80 dB, showing to be promising for analog applications. As the TFETs were being optimized for digital applications and consequently presenting better switching performance, the intrinsic voltage gain moves in the opposite direction. This opposite trend is related to which transport mechanism is predominant for each type of device. While III-V TFETs are more dependent on Band to Band Tunneling (BTBT), silicon devices are more relying on Trap-Assisted Tunneling (TAT). While BTBT allows for faster switching, TAT is less dependent on the drain electric field, so the former favors SS while the latter favors AV. Based on the good analog behavior of silicon channel TFETs, a two-stage operational transconductance amplifier (OTA) was designed with different TFET technologies and the compared results were discussed.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44368668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Stucchi-Zucchi, Marcos Vinicius Puydinger dos Santos, Fernando César Rufino, José Alexandre Diniz
The silicon nanowire (SiNW) is poised to become an industry standard on the upcoming technological nodes. It presents improved current drive and modulation, minimized footprint, stackability, and a host of different beneficial characteristics. The last few years of research have focused on solving the last remaining challenges of SiNW fabrication as they roll into commercial usage. Now, novel devices, as well as channel and device stacking for 3D VLSI applications is being studied. As well as how can the SiNW geometry can be harnessed for More Than Moore materials and applications. In this review, we present a sample of the range of devices, techniques and applications of SiNW structures, alongside novel developments in the research carried out at University of Campinas. Demonstrations of JLFETs fabricated using Ga+-FIB, e-beam lithography, silicon etching in NH4OH solution, FinFETs fabricated using Ga+ lithography and strained silicon structures are shown. Promising future developments in VLSI and More Than Moore applications such as vertically stacked nanowire geometries, graphene nanoribbon devices, and MagFETs are also presented.
硅纳米线(SiNW)有望成为即将到来的技术节点的行业标准。它具有改进的电流驱动和调制，最小的占地面积，可堆叠性和许多不同的有益特性。过去几年的研究集中在解决SiNW制造的最后遗留挑战，因为它们进入商业用途。目前，3D VLSI应用的新型器件以及通道和器件堆叠正在研究中。以及如何将SiNW几何结构用于More Than Moore材料和应用。在这篇综述中，我们展示了SiNW结构的一系列设备、技术和应用的样本，以及在坎皮纳斯大学进行的研究中的新进展。展示了采用Ga+-FIB、电子束光刻、NH4OH溶液中硅蚀刻、Ga+光刻和应变硅结构制备的finfet。展望VLSI和More Than Moore应用的未来发展，如垂直堆叠纳米线几何形状，石墨烯纳米带器件和磁体效应管。
{"title":"Silicon Nanowire Technologies: brief review, home-made solutions and future trends","authors":"L. Stucchi-Zucchi, Marcos Vinicius Puydinger dos Santos, Fernando César Rufino, José Alexandre Diniz","doi":"10.29292/jics.v17i2.614","DOIUrl":"https://doi.org/10.29292/jics.v17i2.614","url":null,"abstract":"The silicon nanowire (SiNW) is poised to become an industry standard on the upcoming technological nodes. It presents improved current drive and modulation, minimized footprint, stackability, and a host of different beneficial characteristics. The last few years of research have focused on solving the last remaining challenges of SiNW fabrication as they roll into commercial usage. Now, novel devices, as well as channel and device stacking for 3D VLSI applications is being studied. As well as how can the SiNW geometry can be harnessed for More Than Moore materials and applications. In this review, we present a sample of the range of devices, techniques and applications of SiNW structures, alongside novel developments in the research carried out at University of Campinas. Demonstrations of JLFETs fabricated using Ga+-FIB, e-beam lithography, silicon etching in NH4OH solution, FinFETs fabricated using Ga+ lithography and strained silicon structures are shown. Promising future developments in VLSI and More Than Moore applications such as vertically stacked nanowire geometries, graphene nanoribbon devices, and MagFETs are also presented.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47397265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Kawabata, Edgard W. Costa, L. Pinto, R. Jakomin, M. Pires, D. Micha, P. Lustoza de Souza
In this review article solar cells based on III-V materials are addressed, starting by a brief description of their operation principle, including key materials’ issues. Subsequently, the different types of III-V solar cells are presented, together with their state-of-the-art performance. Various approaches to reduce their costs are then discussed, and an outlook of the research in this field concludes the paper.
{"title":"III-V SOLAR CELLS","authors":"R. Kawabata, Edgard W. Costa, L. Pinto, R. Jakomin, M. Pires, D. Micha, P. Lustoza de Souza","doi":"10.29292/jics.v17i2.618","DOIUrl":"https://doi.org/10.29292/jics.v17i2.618","url":null,"abstract":"In this review article solar cells based on III-V materials are addressed, starting by a brief description of their operation principle, including key materials’ issues. Subsequently, the different types of III-V solar cells are presented, together with their state-of-the-art performance. Various approaches to reduce their costs are then discussed, and an outlook of the research in this field concludes the paper.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49375748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rafael Da Silva, Vinicius dos Santos, F´abio Petkowicz, Rafael Calc¸ada, R. Reis
It is presented the design flow of an ASIC version of STEEL, a RISC-V microprocessor developed at UFRGS. The microprocessor core called STEEL implements the RV32I and Zicsr instruction sets of the RISC-V specifications. The whole process entails logical and physical synthesis, using the X-Fab 180 nm, which relies on the Cadence EDA framework. The ASIC circuit operates with a maximum frequency of 19.61 MHz and the estimates obtained from the physical synthesis indicates a power consumption of 10.09 mW.
{"title":"Synthesis of Steel-ASIC, a RISC-V Core","authors":"Rafael Da Silva, Vinicius dos Santos, F´abio Petkowicz, Rafael Calc¸ada, R. Reis","doi":"10.29292/jics.v17i2.548","DOIUrl":"https://doi.org/10.29292/jics.v17i2.548","url":null,"abstract":"It is presented the design flow of an ASIC version of STEEL, a RISC-V microprocessor developed at UFRGS. The microprocessor core called STEEL implements the RV32I and Zicsr instruction sets of the RISC-V specifications. The whole process entails logical and physical synthesis, using the X-Fab 180 nm, which relies on the Cadence EDA framework. The ASIC circuit operates with a maximum frequency of 19.61 MHz and the estimates obtained from the physical synthesis indicates a power consumption of 10.09 mW.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47698096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ana Paula Princival Machado, V. Nypwipwy, C. Franca, E. G. Lima
Power amplifiers (PAs) are electronic devices commonly used in telecommunications that need to transmit information with high energetic efficiency. For this, it is necessary to use data manipulation methods that assist in the linearization of the output signal. Our previous conference paper presented two codes constructed based on the Group Method of Data Handling (GMDH) and which differ in their way of selecting the best coefficients to be used in the calculations of the neural network. The first method, called Embracing, assumes greater availability of data, while the second, called Selective, selects information from the beginning of the code. This work extends the previous GMDH models by expanding the PA inputs into Laguerre basis functions with a single real pole. The comparison among the different approaches employs experimental data collected from a GaN HEMT class AB PA and a Si LDMOS class AB. The most selective and computationally more complex structure, when searching for identification since from the first layers, expresses minor errors and the best results in the output for both Conventional and Expanded GMDH models, becoming a reasoned option for use in PAs. A normalized mean square error (NMSE) of -35.44 dB was obtained by Expanded GMDH with Selective algorithm and 5 inputs when using the GaN PA, whereas a NMSE of -40.35 dB was obtained by the Expanded GMDH with Selective algorithm and 4 inputs when calculated with the Si LDMOS PA data.
{"title":"Selective Algorithm for Expanded Group Method of Data Handling Applied to Power Amplifier Modeling","authors":"Ana Paula Princival Machado, V. Nypwipwy, C. Franca, E. G. Lima","doi":"10.29292/jics.v17i2.544","DOIUrl":"https://doi.org/10.29292/jics.v17i2.544","url":null,"abstract":"Power amplifiers (PAs) are electronic devices commonly used in telecommunications that need to transmit information with high energetic efficiency. For this, it is necessary to use data manipulation methods that assist in the linearization of the output signal. Our previous conference paper presented two codes constructed based on the Group Method of Data Handling (GMDH) and which differ in their way of selecting the best coefficients to be used in the calculations of the neural network. The first method, called Embracing, assumes greater availability of data, while the second, called Selective, selects information from the beginning of the code. This work extends the previous GMDH models by expanding the PA inputs into Laguerre basis functions with a single real pole. The comparison among the different approaches employs experimental data collected from a GaN HEMT class AB PA and a Si LDMOS class AB. The most selective and computationally more complex structure, when searching for identification since from the first layers, expresses minor errors and the best results in the output for both Conventional and Expanded GMDH models, becoming a reasoned option for use in PAs. A normalized mean square error (NMSE) of -35.44 dB was obtained by Expanded GMDH with Selective algorithm and 5 inputs when using the GaN PA, whereas a NMSE of -40.35 dB was obtained by the Expanded GMDH with Selective algorithm and 4 inputs when calculated with the Si LDMOS PA data.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46479649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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