Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.582661
A. Khashman, K. M. Curtis
The use of Neural Networks for edge detection is in its infancy, and has not as yet been applied in Multiscale analysis. Multiscale edge detection offers a very effective solution to a wide range of feature extraction problems. The work so far reported has focused on region extraction and edge detection of 2-Dimensional objects. Here the noise and illumination effects on the images are less than would be found in the case of a 3-Dimensional object. In the work reported in this paper both the quality of the detected edges and the introduction of the noise and illumination effects due to the third dimension will be considered. This paper reports on investigations into the use of scale space analysis for 3-Dimensional object recognition. The results are then used to form the basis for the use of a Neural Network to carry out Automatic Edge detection, by defining the correct scale at which to apply the Fast Laplacian of the Gaussian operator, during scale space analysis.
{"title":"Neural networks arbitration for automatic edge detection of 3-dimensional objects","authors":"A. Khashman, K. M. Curtis","doi":"10.1109/ICECS.1996.582661","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582661","url":null,"abstract":"The use of Neural Networks for edge detection is in its infancy, and has not as yet been applied in Multiscale analysis. Multiscale edge detection offers a very effective solution to a wide range of feature extraction problems. The work so far reported has focused on region extraction and edge detection of 2-Dimensional objects. Here the noise and illumination effects on the images are less than would be found in the case of a 3-Dimensional object. In the work reported in this paper both the quality of the detected edges and the introduction of the noise and illumination effects due to the third dimension will be considered. This paper reports on investigations into the use of scale space analysis for 3-Dimensional object recognition. The results are then used to form the basis for the use of a Neural Network to carry out Automatic Edge detection, by defining the correct scale at which to apply the Fast Laplacian of the Gaussian operator, during scale space analysis.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123531767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.582928
R. Lauwereins, M. Adé, S. Note
The paper describes the RETIDES design flow and building blocks which allow for fast and cost-effective prototyping of complete DSP systems on heterogeneous re-usable hardware platforms consisting of general purpose DSP processors, core processors and field programmable gate arrays. Early experiences with two classes of industrial audio and speech applications are reported.
{"title":"Real-time emulation of DSP applications on programmable DSPs and FPGAs","authors":"R. Lauwereins, M. Adé, S. Note","doi":"10.1109/ICECS.1996.582928","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582928","url":null,"abstract":"The paper describes the RETIDES design flow and building blocks which allow for fast and cost-effective prototyping of complete DSP systems on heterogeneous re-usable hardware platforms consisting of general purpose DSP processors, core processors and field programmable gate arrays. Early experiences with two classes of industrial audio and speech applications are reported.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123633508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.584499
J. Melander, T. Widhe, L. Wanhammar
Important issues in designing ASICs are short design time, flexibility, reuse of building blocks, and reliability. These factors can be met by using automatic design tools and standard-cell design. The major drawback with this approach is the attainable circuit performance. In this paper we present an efficient design approach which combines the short design time and flexibility of the standard-cell approach and the high performance of the unconstrained cell layout style. A 128-point FFT/IFFT chip aimed at OFDM applications has successfully been designed using this approach. Further, a modular architecture is proposed that is scalable with respect to the throughput requirements. The throughput scaling can also be utilized to reduce power consumption.
{"title":"Design of an 128-point FFT processor for OFDM applications","authors":"J. Melander, T. Widhe, L. Wanhammar","doi":"10.1109/ICECS.1996.584499","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584499","url":null,"abstract":"Important issues in designing ASICs are short design time, flexibility, reuse of building blocks, and reliability. These factors can be met by using automatic design tools and standard-cell design. The major drawback with this approach is the attainable circuit performance. In this paper we present an efficient design approach which combines the short design time and flexibility of the standard-cell approach and the high performance of the unconstrained cell layout style. A 128-point FFT/IFFT chip aimed at OFDM applications has successfully been designed using this approach. Further, a modular architecture is proposed that is scalable with respect to the throughput requirements. The throughput scaling can also be utilized to reduce power consumption.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125523158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.584447
J. M. Galvez, M. Fonseca
A major difficulty in multivariable control design is the cross-coupling between inputs and outputs which obscures the effects of a specific controller on the overall behavior of the system. This paper considers the application of neural networks in decoupling multivariable output feedback controllers. Simulation results are presented to show the feasibility of the proposed technique.
{"title":"Neural network based decoupling control for multivariable systems","authors":"J. M. Galvez, M. Fonseca","doi":"10.1109/ICECS.1996.584447","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584447","url":null,"abstract":"A major difficulty in multivariable control design is the cross-coupling between inputs and outputs which obscures the effects of a specific controller on the overall behavior of the system. This paper considers the application of neural networks in decoupling multivariable output feedback controllers. Simulation results are presented to show the feasibility of the proposed technique.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130564733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.582911
W. Colmenares, E. Granado, O. Pérez, K. Garrido
In this note we propose a strategy for the synthesis of dynamic regulators for uncertain systems. The controller might be calculated so that some performance requirements (pole placement) are satisfied in any, fixed, point of the uncertain domain. Once the (quadratic) controller is calculated, its robustness is evaluated by means of a simple linear programming approach.
{"title":"Synthesis and robustness evaluation of dynamic controllers for uncertain systems","authors":"W. Colmenares, E. Granado, O. Pérez, K. Garrido","doi":"10.1109/ICECS.1996.582911","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582911","url":null,"abstract":"In this note we propose a strategy for the synthesis of dynamic regulators for uncertain systems. The controller might be calculated so that some performance requirements (pole placement) are satisfied in any, fixed, point of the uncertain domain. Once the (quadratic) controller is calculated, its robustness is evaluated by means of a simple linear programming approach.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129615291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.584540
A. Sartori, M. Gottardi, F. Maloberti, A. Simoni, G. Torelli
The use of CMOS technology allows the monolithic integration of photosensor arrays together with analog-to-digital (A/D) conversion circuits. The structure of the array can be exploited to increase the connectivity between the sensor and the converter, which are in close coupling. Both single-converter per array and multiple-converter per array approaches are therefore possible. This paper presents a comparative study of different A/D conversion architectures incorporated in intelligent optical systems. The presented schemes have been validated by experimental evaluations.
{"title":"Analog-to-digital converters for optical sensor arrays","authors":"A. Sartori, M. Gottardi, F. Maloberti, A. Simoni, G. Torelli","doi":"10.1109/ICECS.1996.584540","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584540","url":null,"abstract":"The use of CMOS technology allows the monolithic integration of photosensor arrays together with analog-to-digital (A/D) conversion circuits. The structure of the array can be exploited to increase the connectivity between the sensor and the converter, which are in close coupling. Both single-converter per array and multiple-converter per array approaches are therefore possible. This paper presents a comparative study of different A/D conversion architectures incorporated in intelligent optical systems. The presented schemes have been validated by experimental evaluations.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128487108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.582854
L. Milic, M. Lutovac
In this paper, a new design method for IIR digital filters which provides the implementation of a half of multiplication constants with few shifters and adders is proposed. The transfer function is developed from an elliptic minimal Q-factors analog prototype and the realization is based on the parallel connection of two allpass networks. In all second order sections of the parallel branches, the digital filter has one common constant independent of the filter order and transition bandwidth. The value of the constant depends only on the frequency for which the filter attenuation is 3 dB and may be adjusted according to the predetermined number of shift-and-add operations.
{"title":"Design of elliptic IIR filters with a reduced number of shift-and-add operations in multipliers","authors":"L. Milic, M. Lutovac","doi":"10.1109/ICECS.1996.582854","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582854","url":null,"abstract":"In this paper, a new design method for IIR digital filters which provides the implementation of a half of multiplication constants with few shifters and adders is proposed. The transfer function is developed from an elliptic minimal Q-factors analog prototype and the realization is based on the parallel connection of two allpass networks. In all second order sections of the parallel branches, the digital filter has one common constant independent of the filter order and transition bandwidth. The value of the constant depends only on the frequency for which the filter attenuation is 3 dB and may be adjusted according to the predetermined number of shift-and-add operations.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127559977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.584519
O. Woywode, B. Pejcinovic
There is a great deal of interest in operating semiconductor devices in large-signal, high frequency mode and the Heterojunction Bipolar Transistor (HBT) possesses some unique properties that make it suitable for such applications. Unexpectedly, it has very good linear properties. In this paper we examine the fundamental reasons for such good performance of HBTs, compare various models and the influence of different parameters, such as emitter resistance, base-collector capacitance and time delay of current gain. In particular, we examine the cancellation of second harmonic currents in the base emitter junction in great detail. The method of nonlinear currents was used to develop a set of analytical expressions for equivalent circuits of varying complexity. It was found that the emitter resistance R/sub ee/ linearizes the HBT at low frequencies by providing negative feedback and by bringing the phase difference of the second order currents closer to 180/spl deg/. At high frequencies the base collector capacitance C/sub bc/ dominates. The inherent nonlinearity of C/sub bc/ degrades the cancellation of second order currents in the base emitter junction. We have also found a connection between two different current gain models that makes them equivalent under certain conditions.
{"title":"Second order distortion modeling in HBTs","authors":"O. Woywode, B. Pejcinovic","doi":"10.1109/ICECS.1996.584519","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584519","url":null,"abstract":"There is a great deal of interest in operating semiconductor devices in large-signal, high frequency mode and the Heterojunction Bipolar Transistor (HBT) possesses some unique properties that make it suitable for such applications. Unexpectedly, it has very good linear properties. In this paper we examine the fundamental reasons for such good performance of HBTs, compare various models and the influence of different parameters, such as emitter resistance, base-collector capacitance and time delay of current gain. In particular, we examine the cancellation of second harmonic currents in the base emitter junction in great detail. The method of nonlinear currents was used to develop a set of analytical expressions for equivalent circuits of varying complexity. It was found that the emitter resistance R/sub ee/ linearizes the HBT at low frequencies by providing negative feedback and by bringing the phase difference of the second order currents closer to 180/spl deg/. At high frequencies the base collector capacitance C/sub bc/ dominates. The inherent nonlinearity of C/sub bc/ degrades the cancellation of second order currents in the base emitter junction. We have also found a connection between two different current gain models that makes them equivalent under certain conditions.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126714500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.584654
H. Altun, K. M. Curtis
The articulatory speech synthesiser is likely to be the ultimate solution to the synthesis of natural sounding, intelligible speech. Yet, the problem of estimating articulatory parameters, from a given speech signal, remains a challenge although remarkable attempts have been reported within the literature towards this end. This paper presents a new technique for the accurate estimation of articulatory parameters through the use of "pseudo formants" and their corresponding amplitudes.
{"title":"Estimation of articulatory synthesiser parameters from pseudo-formants","authors":"H. Altun, K. M. Curtis","doi":"10.1109/ICECS.1996.584654","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584654","url":null,"abstract":"The articulatory speech synthesiser is likely to be the ultimate solution to the synthesis of natural sounding, intelligible speech. Yet, the problem of estimating articulatory parameters, from a given speech signal, remains a challenge although remarkable attempts have been reported within the literature towards this end. This paper presents a new technique for the accurate estimation of articulatory parameters through the use of \"pseudo formants\" and their corresponding amplitudes.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114315825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.584513
G. Theodoridis, S. Theoharis, D. Soudris, O. Koufopavlou, C. Goutis
A new approach for implementing two-level logic circuits, which exhibit minimal power dissipation, is presented. Switching activity reduction of the logic network nodes is achieved by adding in specific gates additional input signals. By using the statistical properties of the primary inputs, a new concept for grouping the input variables with similar features is presented. An efficient synthesis algorithm for generating the set of all classes of the variables and for solving the minimum covering problem for each class is introduced. The comparison of the results, produced by the proposed method, and those from ESPRESSO shows that a significant power reduction can be achieved for the two-level logic circuits.
{"title":"A novel approach for reducing the switching activity in two-level logic circuits","authors":"G. Theodoridis, S. Theoharis, D. Soudris, O. Koufopavlou, C. Goutis","doi":"10.1109/ICECS.1996.584513","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584513","url":null,"abstract":"A new approach for implementing two-level logic circuits, which exhibit minimal power dissipation, is presented. Switching activity reduction of the logic network nodes is achieved by adding in specific gates additional input signals. By using the statistical properties of the primary inputs, a new concept for grouping the input variables with similar features is presented. An efficient synthesis algorithm for generating the set of all classes of the variables and for solving the minimum covering problem for each class is introduced. The comparison of the results, produced by the proposed method, and those from ESPRESSO shows that a significant power reduction can be achieved for the two-level logic circuits.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"28 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114126815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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