M. Sauer, Stefan Kupferschmid, A. Czutro, S. Reddy, B. Becker
Test pattern generation for sequential circuits benefits from scanning strategies as these allow the justification of arbitrary circuit states. However, some of these states may be unreachable during normal operation. This results in non-functional operation which may lead to abnormal circuit behaviour and result in over-testing. In this work, we present a versatile approach that combines a highly adaptable SAT-based path-enumeration algorithm with a model-checking solver for invariant properties that relies on the theory of Craig interpolants to prove the unreachability of circuit states. The method enumerates a set of longest sensitisable paths and yields test sequences of minimal length able to sensitise the found paths starting from a given circuit state. We present detailed experimental results on the reach ability of sensitisable paths in ITC 99 circuits.
{"title":"Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation","authors":"M. Sauer, Stefan Kupferschmid, A. Czutro, S. Reddy, B. Becker","doi":"10.1109/VLSID.2012.101","DOIUrl":"https://doi.org/10.1109/VLSID.2012.101","url":null,"abstract":"Test pattern generation for sequential circuits benefits from scanning strategies as these allow the justification of arbitrary circuit states. However, some of these states may be unreachable during normal operation. This results in non-functional operation which may lead to abnormal circuit behaviour and result in over-testing. In this work, we present a versatile approach that combines a highly adaptable SAT-based path-enumeration algorithm with a model-checking solver for invariant properties that relies on the theory of Craig interpolants to prove the unreachability of circuit states. The method enumerates a set of longest sensitisable paths and yields test sequences of minimal length able to sensitise the found paths starting from a given circuit state. We present detailed experimental results on the reach ability of sensitisable paths in ITC 99 circuits.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126482577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wireless Sensor Nodes (WSNs) require a frequency calibration unit for correcting the spectral mask errors in its Radio Frequency (RF) front-end, which is caused by process, voltage and temperature (PVT) variations of the RF oscillator. In WSN applications, the conditions dictate such a frequency calibration unit to be energy efficient (i.e. both low power and having a fast settling time). In this paper, we propose an on-chip, fully embedded frequency calibration methodology, the corresponding algorithm and the hardware architecture, which are suitable for ultra-low power WSNs that use Frequency Shift Keying (FSK) as its modulation scheme. The architecture is based on computation of the fraction-phase of an RF oscillator frequency, when the former is divided by a reference frequency value. The proposed technique, though analogous to a fraction-N frequency synthesizer, requires no phase-locking mechanism and, therefore, requires no Phase Locked Loop (PLL). Simulation results have been presented showing the improved performance metrics over the state-of-the-art frequency calibration techniques used in WSNs.
{"title":"An Energy Efficient Oscillator Frequency Calibration Methodology Using Fraction Phase Computation","authors":"Amitava Ghosh, Isha Das, Achintya Halder","doi":"10.1109/VLSID.2012.51","DOIUrl":"https://doi.org/10.1109/VLSID.2012.51","url":null,"abstract":"Wireless Sensor Nodes (WSNs) require a frequency calibration unit for correcting the spectral mask errors in its Radio Frequency (RF) front-end, which is caused by process, voltage and temperature (PVT) variations of the RF oscillator. In WSN applications, the conditions dictate such a frequency calibration unit to be energy efficient (i.e. both low power and having a fast settling time). In this paper, we propose an on-chip, fully embedded frequency calibration methodology, the corresponding algorithm and the hardware architecture, which are suitable for ultra-low power WSNs that use Frequency Shift Keying (FSK) as its modulation scheme. The architecture is based on computation of the fraction-phase of an RF oscillator frequency, when the former is divided by a reference frequency value. The proposed technique, though analogous to a fraction-N frequency synthesizer, requires no phase-locking mechanism and, therefore, requires no Phase Locked Loop (PLL). Simulation results have been presented showing the improved performance metrics over the state-of-the-art frequency calibration techniques used in WSNs.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131794388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Subhadip Kundu, S. Chattopadhyay, I. Sengupta, R. Kapur
Diagnosis is the methodology to identify the reason behind the failure of manufactured chips. This is particularly important from the yield enhancement viewpoint. The primary focus of a diagnosis algorithm is to accurately narrow down the list of suspected candidates. But for any diagnosis algorithm, the effectiveness will depend on the test set in use. If the test set used is not good enough to distinguish between fault pairs, the diagnosis algorithm can never be able to distinguish between a good number of faults. This problem leads us to find a metric which can characterize test sets in terms of their diagnostic power. In literature, several methods have been proposed for assessment of the diagnostic power of a test set. Though the methods are accurate in nature, the bottleneck is the space and time complexity. Thus, given a number of test sets (with same fault coverage) for a circuit, it is very difficult to select one of them for better diagnosis. In this paper, we have proposed a probability based approach to find out a metric to describe diagnostic power of a test set. We call this metric, the diagnosibility of the test set for a given circuit. Our method uses almost 99% less space compared to the proposed methods and is well accurate.
{"title":"A Diagnosability Metric for Test Set Selection Targeting Better Fault Detection","authors":"Subhadip Kundu, S. Chattopadhyay, I. Sengupta, R. Kapur","doi":"10.1109/VLSID.2012.110","DOIUrl":"https://doi.org/10.1109/VLSID.2012.110","url":null,"abstract":"Diagnosis is the methodology to identify the reason behind the failure of manufactured chips. This is particularly important from the yield enhancement viewpoint. The primary focus of a diagnosis algorithm is to accurately narrow down the list of suspected candidates. But for any diagnosis algorithm, the effectiveness will depend on the test set in use. If the test set used is not good enough to distinguish between fault pairs, the diagnosis algorithm can never be able to distinguish between a good number of faults. This problem leads us to find a metric which can characterize test sets in terms of their diagnostic power. In literature, several methods have been proposed for assessment of the diagnostic power of a test set. Though the methods are accurate in nature, the bottleneck is the space and time complexity. Thus, given a number of test sets (with same fault coverage) for a circuit, it is very difficult to select one of them for better diagnosis. In this paper, we have proposed a probability based approach to find out a metric to describe diagnostic power of a test set. We call this metric, the diagnosibility of the test set for a given circuit. Our method uses almost 99% less space compared to the proposed methods and is well accurate.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"376 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133013639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a hardware efficient architecture for generating sine and cosine waves based on the CORDIC (Coordinate Rotation Digital Computer) algorithm. In its original form the CORDIC suffers from major drawbacks like scale-factor calculation, latency and optimal selection of micro-rotations. The proposed algorithm overcomes all these drawbacks. We use leading-one bit detection technique to identify the micro-rotations. The scale-free design of the proposed algorithm is based on Taylor series expansion of the sine and cosine waves. The 16-bit iterative architecture achieves approximately 4.5% and 6.7% lower slice-delay product as compared to the other existing designs. The algorithm design and its VLSI implementation are detailed.
{"title":"Hardware Efficient Architecture for Generating Sine/Cosine Waves","authors":"Supriya Aggarwal, K. Khare","doi":"10.1109/VLSID.2012.46","DOIUrl":"https://doi.org/10.1109/VLSID.2012.46","url":null,"abstract":"This paper presents a hardware efficient architecture for generating sine and cosine waves based on the CORDIC (Coordinate Rotation Digital Computer) algorithm. In its original form the CORDIC suffers from major drawbacks like scale-factor calculation, latency and optimal selection of micro-rotations. The proposed algorithm overcomes all these drawbacks. We use leading-one bit detection technique to identify the micro-rotations. The scale-free design of the proposed algorithm is based on Taylor series expansion of the sine and cosine waves. The 16-bit iterative architecture achieves approximately 4.5% and 6.7% lower slice-delay product as compared to the other existing designs. The algorithm design and its VLSI implementation are detailed.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122282664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D TSV-SICs with two chips and 3D TSV-SICs with an arbitrary number of chips. We have implemented our techniques and experiments show significant reduction of test cost.
{"title":"Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias","authors":"B. SenGupta, Urban Ingelsson, E. Larsson","doi":"10.1109/VLSID.2012.111","DOIUrl":"https://doi.org/10.1109/VLSID.2012.111","url":null,"abstract":"Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D TSV-SICs with two chips and 3D TSV-SICs with an arbitrary number of chips. We have implemented our techniques and experiments show significant reduction of test cost.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123470053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. Packaging has become one of the critical areas of the SoC design flow in recent years. Miniaturization of package with the ever increasing interface speeds and massive integration have opened up a lot of challenges for packaging engineers. This talk will cover different popular packages available in the industry and recent package trends. Traditionally, package design and analysis always followed SoC design, but it is becoming more and more imperative to design die and package in conjunction. Designing the die and package together in the loop to optimize die and package design and closure is popularly referred to as die package co-design. This talk will focus on the key aspects of co-design flow, package modeling/analysis aspects specifically for high performance designs. This talk will also cover some key issues and challenges from practical designs.
{"title":"Embedded Tutorial ET3: Packaging Trends, Die Package Co-Design Flow and Challenges","authors":"Siva Kothamasu","doi":"10.1109/VLSID.2012.40","DOIUrl":"https://doi.org/10.1109/VLSID.2012.40","url":null,"abstract":"Summary form only given. Packaging has become one of the critical areas of the SoC design flow in recent years. Miniaturization of package with the ever increasing interface speeds and massive integration have opened up a lot of challenges for packaging engineers. This talk will cover different popular packages available in the industry and recent package trends. Traditionally, package design and analysis always followed SoC design, but it is becoming more and more imperative to design die and package in conjunction. Designing the die and package together in the loop to optimize die and package design and closure is popularly referred to as die package co-design. This talk will focus on the key aspects of co-design flow, package modeling/analysis aspects specifically for high performance designs. This talk will also cover some key issues and challenges from practical designs.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115173973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Goel, D. Evans, Richard Stephani, V. Reddy, Dharmendra Rai, V. Chary, N. Sathisha
Reducing the leakage power in embedded SRAM memories is critical for low-power applications. Raising the source voltage of SRAM cells through diode transistor in standby mode reduces the leakage currents effectively. However, in order to preserve the state of the cell in standby mode, the source voltage cannot be raised beyond a certain level. To achieve that, the size of the required diode transistor becomes larger, as the supply voltage shrinks in the nano-CMOS technologies. In this work, an area efficient power gating technique with capability of post-silicon trimming of the voltage across SRAM cell is presented. Proposed interchangeable on transistor and diode scheme reduces the area overhead by 40% compared to conventional schemes, when applied to a 16Kb SRAM macro at 28nm CMOS technology at 0.85V supply voltage. Trimmable power gating scheme provides many options to trim the SRAM source voltage (ranging from 50mV to 150 mV in steps of approx. 25mV) with approx. 3% area overhead and more flexibility over conventional schemes.
{"title":"An Area Efficient Diode and On Transistor Interchangeable Power Gating Scheme with Trim Options for Low Power SRAMs","authors":"A. Goel, D. Evans, Richard Stephani, V. Reddy, Dharmendra Rai, V. Chary, N. Sathisha","doi":"10.1109/VLSID.2012.50","DOIUrl":"https://doi.org/10.1109/VLSID.2012.50","url":null,"abstract":"Reducing the leakage power in embedded SRAM memories is critical for low-power applications. Raising the source voltage of SRAM cells through diode transistor in standby mode reduces the leakage currents effectively. However, in order to preserve the state of the cell in standby mode, the source voltage cannot be raised beyond a certain level. To achieve that, the size of the required diode transistor becomes larger, as the supply voltage shrinks in the nano-CMOS technologies. In this work, an area efficient power gating technique with capability of post-silicon trimming of the voltage across SRAM cell is presented. Proposed interchangeable on transistor and diode scheme reduces the area overhead by 40% compared to conventional schemes, when applied to a 16Kb SRAM macro at 28nm CMOS technology at 0.85V supply voltage. Trimmable power gating scheme provides many options to trim the SRAM source voltage (ranging from 50mV to 150 mV in steps of approx. 25mV) with approx. 3% area overhead and more flexibility over conventional schemes.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121069817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Praveen Salihundam, Mohammed Asadullah Khan, Shailendra Jain, Y. Hoskote, Satish Yada, Shasi Kumar, V. Erraguntla, S. Vangal, N. Borkar
A reconfigurable on-die Traffic Generator (TG) is proposed to test the packet switched 2D-mesh network of a 48 iA-32 core Single-chip Cloud Computer. The Single-chip Cloud Computer (SCC) is an experimental processor created by Intel Labs. The 24-tile Network-on-Chip (NoC) consists of a Traffic Generator per tile which can be programmed to generate deterministic and random traffic patterns. It also consists of reconfigurable activity control, (non)-cacheable reads and writes, message class and route control bits to feed synthetic traffic to the network to investigate NoC functional, protocol issues and to measure the key power-performance metrics. In this paper, we present the architecture and design details of the Traffic Generator, operating modes, re-configurability and the testing procedures. This semi-custom design has a transistor count of 54K, which is 0.1% of tile transistor count, and occupies 0.3mm2 area which is 0.9% of tile area. The estimated power consumption is only 23mW at 1.1V and at 500C, 0.02% of the total chip power in 45nm high-K nine metal CMOS process.
{"title":"A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip","authors":"Praveen Salihundam, Mohammed Asadullah Khan, Shailendra Jain, Y. Hoskote, Satish Yada, Shasi Kumar, V. Erraguntla, S. Vangal, N. Borkar","doi":"10.1109/VLSID.2012.86","DOIUrl":"https://doi.org/10.1109/VLSID.2012.86","url":null,"abstract":"A reconfigurable on-die Traffic Generator (TG) is proposed to test the packet switched 2D-mesh network of a 48 iA-32 core Single-chip Cloud Computer. The Single-chip Cloud Computer (SCC) is an experimental processor created by Intel Labs. The 24-tile Network-on-Chip (NoC) consists of a Traffic Generator per tile which can be programmed to generate deterministic and random traffic patterns. It also consists of reconfigurable activity control, (non)-cacheable reads and writes, message class and route control bits to feed synthetic traffic to the network to investigate NoC functional, protocol issues and to measure the key power-performance metrics. In this paper, we present the architecture and design details of the Traffic Generator, operating modes, re-configurability and the testing procedures. This semi-custom design has a transistor count of 54K, which is 0.1% of tile transistor count, and occupies 0.3mm2 area which is 0.9% of tile area. The estimated power consumption is only 23mW at 1.1V and at 500C, 0.02% of the total chip power in 45nm high-K nine metal CMOS process.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123205528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Manohar, V. Somasundar, R. Venkatasubramanian, P. Balsara
Level shifter circuits are used to interface multiple voltage islands in many modern ICs or Systems-on-Chip (SoCs). Single-supply level shifters are being used to reduce the power routing resources and minimize the routing congestion at the chip level. A single-supply bidirectional level shifter aimed at low voltage which offers a wide voltage range (SS-WVRLS) is designed using standard commercial 90nm CMOS process. The proposed level shifter uses analog and digital circuit techniques to provide full voltage shifting range for any combination of supply voltages (VDDIN = VDD,VDDIN <; VDD or VDDIN >; VDD) in any step size (paper shows 25mv step) with no requirement for special low-Vτ or high-Vτ devices, thus reducing the process cost. Post layout SPICE simulation comparison results show that proposed circuit is functional for full core supply voltage range (0.6V - 1.32V) compared to other published level shifters. The circuit was tested for robustness under process mismatch conditions by 1000 point global and local Monte Carlo simulations.
{"title":"Bidirectional Single-Supply Level Shifter with Wide Voltage Range for Efficient Power Management","authors":"S. Manohar, V. Somasundar, R. Venkatasubramanian, P. Balsara","doi":"10.1109/VLSID.2012.58","DOIUrl":"https://doi.org/10.1109/VLSID.2012.58","url":null,"abstract":"Level shifter circuits are used to interface multiple voltage islands in many modern ICs or Systems-on-Chip (SoCs). Single-supply level shifters are being used to reduce the power routing resources and minimize the routing congestion at the chip level. A single-supply bidirectional level shifter aimed at low voltage which offers a wide voltage range (SS-WVRLS) is designed using standard commercial 90nm CMOS process. The proposed level shifter uses analog and digital circuit techniques to provide full voltage shifting range for any combination of supply voltages (VDDIN = VDD,VDDIN <; VDD or VDDIN >; VDD) in any step size (paper shows 25mv step) with no requirement for special low-Vτ or high-Vτ devices, thus reducing the process cost. Post layout SPICE simulation comparison results show that proposed circuit is functional for full core supply voltage range (0.6V - 1.32V) compared to other published level shifters. The circuit was tested for robustness under process mismatch conditions by 1000 point global and local Monte Carlo simulations.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126378496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Damodaran, T. Anderson, S. Agarwala, R. Venkatasubramanian, M. Gill, Dhileep Gopalakrishnan, A. Hill, A. Chachad, D. Balasubramanian, Naveen Bhoria, Jonathan Tran, Duc Bui, Mujibur Rahman, S. Moharil, Matthew D. Pierson, Steven Mullinnix, Hung Ong, D. Thompson, Krishna Gurram, O. Olorode, Nuruddin Mahmood, Jose Flores, A. Rajagopal, Soujanya Narnur, Daniel Wu, Alan Hales, Kyle Peavy, Robert Sussman
The next-generation C66x DSP integrated fixed and floating-point DSP implemented in TSMC 40nm process is presented in this paper. The DSP core runs at 1.25GHz at 0.9V and has a standby power consumption of 800mW. The core transistor count is 21.5 million. The DSP core features 8-way VLIW floating point Data path and a two level memory system and delivers 40 GMACS or 10 GFLOPS floating point MAC performance at 1.25GHz.
{"title":"A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS","authors":"R. Damodaran, T. Anderson, S. Agarwala, R. Venkatasubramanian, M. Gill, Dhileep Gopalakrishnan, A. Hill, A. Chachad, D. Balasubramanian, Naveen Bhoria, Jonathan Tran, Duc Bui, Mujibur Rahman, S. Moharil, Matthew D. Pierson, Steven Mullinnix, Hung Ong, D. Thompson, Krishna Gurram, O. Olorode, Nuruddin Mahmood, Jose Flores, A. Rajagopal, Soujanya Narnur, Daniel Wu, Alan Hales, Kyle Peavy, Robert Sussman","doi":"10.1109/VLSID.2012.85","DOIUrl":"https://doi.org/10.1109/VLSID.2012.85","url":null,"abstract":"The next-generation C66x DSP integrated fixed and floating-point DSP implemented in TSMC 40nm process is presented in this paper. The DSP core runs at 1.25GHz at 0.9V and has a standby power consumption of 800mW. The core transistor count is 21.5 million. The DSP core features 8-way VLIW floating point Data path and a two level memory system and delivers 40 GMACS or 10 GFLOPS floating point MAC performance at 1.25GHz.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126743767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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