Optimization techniques are widely used in embedded systems design to improve overall area, performance and energy requirements. Dynamic cache reconfiguration (DCR) is very effective to reduce energy consumption of cache subsystems. Finding the right reconfiguration points in a task and selecting appropriate cache configurations for each phase are the primary challenges in phase-based DCR. In this paper, we present a novel intra-task dynamic cache reconfiguration technique using a detailed cache model, and tune a highly-configurable cache on a per-phase basis compared to tuning once per application. Experimental results demonstrate that our intra-task DCR can achieve up to 27% (12% on average) and 19% (7% on average) energy savings for instruction and data caches, respectively, without introducing any performance penalty.
{"title":"Intra-Task Dynamic Cache Reconfiguration","authors":"Hadi Hajimiri, P. Mishra","doi":"10.1109/VLSID.2012.109","DOIUrl":"https://doi.org/10.1109/VLSID.2012.109","url":null,"abstract":"Optimization techniques are widely used in embedded systems design to improve overall area, performance and energy requirements. Dynamic cache reconfiguration (DCR) is very effective to reduce energy consumption of cache subsystems. Finding the right reconfiguration points in a task and selecting appropriate cache configurations for each phase are the primary challenges in phase-based DCR. In this paper, we present a novel intra-task dynamic cache reconfiguration technique using a detailed cache model, and tune a highly-configurable cache on a per-phase basis compared to tuning once per application. Experimental results demonstrate that our intra-task DCR can achieve up to 27% (12% on average) and 19% (7% on average) energy savings for instruction and data caches, respectively, without introducing any performance penalty.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132017364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Reverse Engineering (RE) has been historically considered as a powerful approach to understand electronic hardware in order to gain competitive intelligence or accomplish piracy. In recent years, it has also been looked at as a way to authenticate hardware intellectual properties in the court of law. In this paper, we propose a beneficial role of RE in post-silicon validation of integrated circuits (IC) with respect to IC functionality, reliability and integrity. Unlike traditional destructive RE approaches, we propose a fast non-destructive side-channel analysis approach that can hierarchically extract structural information from an IC through its transient current signature. Such a top-down side-channel analysis approach is capable of reliably identifying pipeline stages and functional blocks. It is also suitable to distinguish sequential elements from combinational gates. For extraction of random logic structures (e.g. control blocks and finite state machines) we combine side-channel analysis with logic testing based Boolean function extraction. The proposed approach is amenable to automation, scalable, and can be applied as part of post-silicon validation process to verify that each IC implements exclusively the functionality described in the specification and is free from malicious modification or Trojan attacks. Simulation results on a pipelined DLX processor demonstrate the effectiveness of the proposed approach.
{"title":"SCARE: Side-Channel Analysis Based Reverse Engineering for Post-Silicon Validation","authors":"Xinmu Wang, S. Narasimhan, A. Krishna, S. Bhunia","doi":"10.1109/VLSID.2012.88","DOIUrl":"https://doi.org/10.1109/VLSID.2012.88","url":null,"abstract":"Reverse Engineering (RE) has been historically considered as a powerful approach to understand electronic hardware in order to gain competitive intelligence or accomplish piracy. In recent years, it has also been looked at as a way to authenticate hardware intellectual properties in the court of law. In this paper, we propose a beneficial role of RE in post-silicon validation of integrated circuits (IC) with respect to IC functionality, reliability and integrity. Unlike traditional destructive RE approaches, we propose a fast non-destructive side-channel analysis approach that can hierarchically extract structural information from an IC through its transient current signature. Such a top-down side-channel analysis approach is capable of reliably identifying pipeline stages and functional blocks. It is also suitable to distinguish sequential elements from combinational gates. For extraction of random logic structures (e.g. control blocks and finite state machines) we combine side-channel analysis with logic testing based Boolean function extraction. The proposed approach is amenable to automation, scalable, and can be applied as part of post-silicon validation process to verify that each IC implements exclusively the functionality described in the specification and is free from malicious modification or Trojan attacks. Simulation results on a pipelined DLX processor demonstrate the effectiveness of the proposed approach.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130892187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents power aware hardware implementation of multiclass Support Vector Machine on FPGA using systolic array architecture. It uses Partial reconfiguration schemes of XILINX for power optimal implementation of the design. Systolic array architecture provides efficient memory management, reduced complexity, and efficient data transfer mechanisms. Multiclass support vector machine is used as classifier for facial expression recognition system, which identifies one of six basic facial expressions such as smile, surprise, sad, anger, disgust, and fear. The extracted parameters from training phase of the SVM are used to implement testing phase of the SVM on the hardware. In the architecture, vector multiplication operation and classification of pair wise classifiers is designed. A data set of Cohn Kanade database in six different classes is used for training and testing of proposed SVM. This architecture is then partially reconfigured using difference based approach with the help of XILINX EDA tools. For feature classification power reduction is achieved using reconfiguration.
{"title":"Power Aware Hardware Prototyping of Multiclass SVM Classifier Through Reconfiguration","authors":"R. A. Patil, G. Gupta, V. Sahula, A. S. Mandal","doi":"10.1109/VLSID.2012.47","DOIUrl":"https://doi.org/10.1109/VLSID.2012.47","url":null,"abstract":"This paper presents power aware hardware implementation of multiclass Support Vector Machine on FPGA using systolic array architecture. It uses Partial reconfiguration schemes of XILINX for power optimal implementation of the design. Systolic array architecture provides efficient memory management, reduced complexity, and efficient data transfer mechanisms. Multiclass support vector machine is used as classifier for facial expression recognition system, which identifies one of six basic facial expressions such as smile, surprise, sad, anger, disgust, and fear. The extracted parameters from training phase of the SVM are used to implement testing phase of the SVM on the hardware. In the architecture, vector multiplication operation and classification of pair wise classifiers is designed. A data set of Cohn Kanade database in six different classes is used for training and testing of proposed SVM. This architecture is then partially reconfigured using difference based approach with the help of XILINX EDA tools. For feature classification power reduction is achieved using reconfiguration.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121399834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Due to the increasing trend toward greater processor power density and computationally intensive applications, Dynamic Thermal Management (DTM) has become an essential technique in modern processors. Among many DTM techniques, Dynamic Voltage Scaling (DVS) is widely used because of its chief virtue - a cubic reduction in power at the relatively minor cost of a linear performance penalty. Because this reduction comes at a cost in execution speed, a key point of DVS-based DTM research is how accurately the processor predicts the optimal performance point where it can meet the thermal constraints while also minimizing the performance penalty. In this paper, we propose a new DVS-based DTM technique that makes the prediction of the optimal performance point more accurate. To achieve this, run-time prediction techniques are used and different power compositions due to process variations are considered from a VLSI perspective. The prediction process is performed by referring to one of the Look-Up Tables (LUTs) prepared during design time and also the average clock enable ratio that is dynamically calculated at run time. The simulation results show that we can achieve maximum processor performance while keeping the processor temperature from exceeding the threshold temperature.
{"title":"Run-time Prediction of the Optimal Performance Point in DVS-based Dynamic Thermal Management","authors":"Junyoung Park, H. M. Ustun, J. Abraham","doi":"10.1109/VLSID.2012.63","DOIUrl":"https://doi.org/10.1109/VLSID.2012.63","url":null,"abstract":"Due to the increasing trend toward greater processor power density and computationally intensive applications, Dynamic Thermal Management (DTM) has become an essential technique in modern processors. Among many DTM techniques, Dynamic Voltage Scaling (DVS) is widely used because of its chief virtue - a cubic reduction in power at the relatively minor cost of a linear performance penalty. Because this reduction comes at a cost in execution speed, a key point of DVS-based DTM research is how accurately the processor predicts the optimal performance point where it can meet the thermal constraints while also minimizing the performance penalty. In this paper, we propose a new DVS-based DTM technique that makes the prediction of the optimal performance point more accurate. To achieve this, run-time prediction techniques are used and different power compositions due to process variations are considered from a VLSI perspective. The prediction process is performed by referring to one of the Look-Up Tables (LUTs) prepared during design time and also the average clock enable ratio that is dynamically calculated at run time. The simulation results show that we can achieve maximum processor performance while keeping the processor temperature from exceeding the threshold temperature.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121462486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
IR drops in a Power Delivery Network (PDN) on chip multi-processors (CMPs) can worsen the quality of voltage supply and thereby affect overall performance. This problem is more severe in 3D CMPs with network-on-chip (NoC) fabrics where the current in the PDN increases proportionally to the number of device layers. Even though the PDN and NoC design goals are non-overlapping, both the optimizations are interdependent, for instance, each new core mapping on the 3D die will change traffic patterns and have a unique distribution of IR-drops in the PDN. Unfortunately, designers today seldom consider design of PDN while synthesizing NoCs. If NoC synthesis is carried out without considering the associated PDN design cost, it can easily result in an overall sub-optimal design. In this work, for the first time, we propose a novel PDN-aware 3D NoC synthesis framework that minimizes NoC power while meeting performance goals, and optimizes the corresponding PDN for total number of Voltage Regulator Modules (VRMs), current efficiency, and grid-wire width while satisfying IR-drop constraints. Our experimental results show that the proposed methodology provides more comprehensive results compared to a traditional approach where the NoC synthesis step does not consider the PDN costs.
{"title":"A Power Delivery Network Aware Framework for Synthesis of 3D Networks-on-Chip with Multiple Voltage Islands","authors":"N. Kapadia, S. Pasricha","doi":"10.1109/VLSID.2012.81","DOIUrl":"https://doi.org/10.1109/VLSID.2012.81","url":null,"abstract":"IR drops in a Power Delivery Network (PDN) on chip multi-processors (CMPs) can worsen the quality of voltage supply and thereby affect overall performance. This problem is more severe in 3D CMPs with network-on-chip (NoC) fabrics where the current in the PDN increases proportionally to the number of device layers. Even though the PDN and NoC design goals are non-overlapping, both the optimizations are interdependent, for instance, each new core mapping on the 3D die will change traffic patterns and have a unique distribution of IR-drops in the PDN. Unfortunately, designers today seldom consider design of PDN while synthesizing NoCs. If NoC synthesis is carried out without considering the associated PDN design cost, it can easily result in an overall sub-optimal design. In this work, for the first time, we propose a novel PDN-aware 3D NoC synthesis framework that minimizes NoC power while meeting performance goals, and optimizes the corresponding PDN for total number of Voltage Regulator Modules (VRMs), current efficiency, and grid-wire width while satisfying IR-drop constraints. Our experimental results show that the proposed methodology provides more comprehensive results compared to a traditional approach where the NoC synthesis step does not consider the PDN costs.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122588791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An RF envelope detector (ED) and an asynchronous latching circuit have been designed for a wake-up receiver in 400 MHz MICS and 433 MHz / 915 MHz ISM band. The architecture is designed to tolerate significant process, supply-voltage and temperature variations. An alternative bit encoding technique has been used, which eliminates the need for symbol synchronization and the associated circuitry. The power consumption of the entire circuit, which is designed using 1.8 V supply voltage and 180 nm CMOS process, is limited to 43 uW during symbol detection and is limited to 34 uW when no input signal activity is present in the receiver RF front-end. For an input current swing of ±3 μA from the RF front-end, the circuit successfully detects up to a 2.5 Mbps input data rate.
{"title":"An Ultra-low Power Symbol Detection Methodology and Its Circuit Implementation for a Wake-up Receiver in Wireless Sensor Nodes","authors":"D. K. Meher, A. Salimath, Achintya Halder","doi":"10.1109/VLSID.2012.83","DOIUrl":"https://doi.org/10.1109/VLSID.2012.83","url":null,"abstract":"An RF envelope detector (ED) and an asynchronous latching circuit have been designed for a wake-up receiver in 400 MHz MICS and 433 MHz / 915 MHz ISM band. The architecture is designed to tolerate significant process, supply-voltage and temperature variations. An alternative bit encoding technique has been used, which eliminates the need for symbol synchronization and the associated circuitry. The power consumption of the entire circuit, which is designed using 1.8 V supply voltage and 180 nm CMOS process, is limited to 43 uW during symbol detection and is limited to 34 uW when no input signal activity is present in the receiver RF front-end. For an input current swing of ±3 μA from the RF front-end, the circuit successfully detects up to a 2.5 Mbps input data rate.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125684861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Reversible logic is emerging as a promising computing paradigm with applications in ultralow power nanocomputing and emerging nanotechnologies such as quantum computing, quantum dot cellular automata (QCA), optical computing, etc. Reversible circuits are similar to conventional logic circuits except that they are built from reversible gates. In reversible gates, there is a unique, one-to-one mapping between the inputs and outputs, not the case with conventional logic. One of the primary motivations for adopting reversible logic lies in the fact that it can provide a logic design methodology for designing ultra-low power circuits beyond KTln2 limit for those emerging nanotechnologies in which the energy dissipated due to information destruction will be a significant factor of the overall heat dissipation. Further, logic circuits for quantum computers must be built from reversible logic components. Several important metrics need to be considered in the design of reversible circuits the importance of which needs to be discussed. Quantum computers of many qubits are extremely difficult to realize thus the number of qubits in the quantum circuits needs to be minimized. This sets the major objective of optimizing the number of ancilla inputs and the number of the garbage outputs in the reversible logic based quantum circuits. The constant input in the reversible quantum circuit is called the ancilla input, while the garbage output refers to the output which exists in the circuit just to maintain one-to-one mapping but is not a primary or a useful output. The reversible circuit has other important parameters of quantum cost and delay which need to be optimized.
{"title":"Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future","authors":"H. Thapliyal, N. Ranganathan","doi":"10.1109/VLSID.2012.29","DOIUrl":"https://doi.org/10.1109/VLSID.2012.29","url":null,"abstract":"Reversible logic is emerging as a promising computing paradigm with applications in ultralow power nanocomputing and emerging nanotechnologies such as quantum computing, quantum dot cellular automata (QCA), optical computing, etc. Reversible circuits are similar to conventional logic circuits except that they are built from reversible gates. In reversible gates, there is a unique, one-to-one mapping between the inputs and outputs, not the case with conventional logic. One of the primary motivations for adopting reversible logic lies in the fact that it can provide a logic design methodology for designing ultra-low power circuits beyond KTln2 limit for those emerging nanotechnologies in which the energy dissipated due to information destruction will be a significant factor of the overall heat dissipation. Further, logic circuits for quantum computers must be built from reversible logic components. Several important metrics need to be considered in the design of reversible circuits the importance of which needs to be discussed. Quantum computers of many qubits are extremely difficult to realize thus the number of qubits in the quantum circuits needs to be minimized. This sets the major objective of optimizing the number of ancilla inputs and the number of the garbage outputs in the reversible logic based quantum circuits. The constant input in the reversible quantum circuit is called the ancilla input, while the garbage output refers to the output which exists in the circuit just to maintain one-to-one mapping but is not a primary or a useful output. The reversible circuit has other important parameters of quantum cost and delay which need to be optimized.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125295323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a technique to improve the accuracy of the final design predicted by Geometric Programming based CMOS analog circuit sizing methodology. Here we use a multi-level AC performance modeling paradigm to develop the empirical models of circuit performance metrics. Performance models are then upgraded over iterations of design cycle. This iterative model up gradation in a sequence of geometric programming guides the final design to converge with better accuracy. The methodology is validated by designing a two-stage amplifier cascaded with a Class-A (source-follower) output buffer stage in UMC 0.18 μm technology.
{"title":"Iterative Performance Model Upgradation in Geometric Programming Based Analog Circuit Sizing for Improved Design Accuracy","authors":"S. Dam, P. Mandal","doi":"10.1109/VLSID.2012.100","DOIUrl":"https://doi.org/10.1109/VLSID.2012.100","url":null,"abstract":"In this paper, we propose a technique to improve the accuracy of the final design predicted by Geometric Programming based CMOS analog circuit sizing methodology. Here we use a multi-level AC performance modeling paradigm to develop the empirical models of circuit performance metrics. Performance models are then upgraded over iterations of design cycle. This iterative model up gradation in a sequence of geometric programming guides the final design to converge with better accuracy. The methodology is validated by designing a two-stage amplifier cascaded with a Class-A (source-follower) output buffer stage in UMC 0.18 μm technology.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131914816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
One of the goals of clock tree synthesis in ASIC design flow is skew minimization. There are several approaches used in traditional clock tree synthesis tools to achieve this goal. However, many of the approaches create a large number of clock-buffer levels while others result in congested clock routing. Increase in buffer level and routing congestion essentially triggers the problem of increase in buffer area and total power. Also the performance of the circuit is degraded due to on-chip variation in such situations. For certain fan-out number restricted designs, a few proposals with H-tree routed clock nets have been proposed to reduce the skew, but those proposals can hardly be used across various designs used in industry. Here we propose a method where skew minimization is mainly achieved by structured routing of clock nets. Finally, we show that with this proposal, for a few real designs from industry, we could reduce the skew up to 6.5% with increase in total wire delay up to 1.89% compared to when simple H-tree routing was deployed.
{"title":"Clock Tree Skew Minimization with Structured Routing","authors":"Pinaki Chakrabarti","doi":"10.1109/VLSID.2012.76","DOIUrl":"https://doi.org/10.1109/VLSID.2012.76","url":null,"abstract":"One of the goals of clock tree synthesis in ASIC design flow is skew minimization. There are several approaches used in traditional clock tree synthesis tools to achieve this goal. However, many of the approaches create a large number of clock-buffer levels while others result in congested clock routing. Increase in buffer level and routing congestion essentially triggers the problem of increase in buffer area and total power. Also the performance of the circuit is degraded due to on-chip variation in such situations. For certain fan-out number restricted designs, a few proposals with H-tree routed clock nets have been proposed to reduce the skew, but those proposals can hardly be used across various designs used in industry. Here we propose a method where skew minimization is mainly achieved by structured routing of clock nets. Finally, we show that with this proposal, for a few real designs from industry, we could reduce the skew up to 6.5% with increase in total wire delay up to 1.89% compared to when simple H-tree routing was deployed.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121253518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The development and use of assertions in the Analog and Mixed-signal (AMS) domain is a subject which has attracted significant attention lately from the verification community. Recent studies have suggested that natural extensions of assertion languages (like PSL and SVA) into the AMS domain are not expressive enough to capture many AMS behaviors, and that a library of auxiliary AMS functions are needed along with the assertion language. The integration of auxiliary functions with the core fabric of a temporal logic is non-trivial and can be challenging for a verification engineer. In this paper we propose a purely library-based verification approach, where libraries for checking elementary properties can be naturally connected with libraries for auxiliary functions to monitor complex AMS behaviors. We study the modeling of behaviors with the proposed library, and outline the main challenges and their solutions towards implementing the verification library over commercial AMS simulators.
{"title":"A Library for Passive Online Verification of Analog and Mixed-Signal Circuits","authors":"D. Pal, P. Dasgupta, S. Mukhopadhyay","doi":"10.1109/VLSID.2012.98","DOIUrl":"https://doi.org/10.1109/VLSID.2012.98","url":null,"abstract":"The development and use of assertions in the Analog and Mixed-signal (AMS) domain is a subject which has attracted significant attention lately from the verification community. Recent studies have suggested that natural extensions of assertion languages (like PSL and SVA) into the AMS domain are not expressive enough to capture many AMS behaviors, and that a library of auxiliary AMS functions are needed along with the assertion language. The integration of auxiliary functions with the core fabric of a temporal logic is non-trivial and can be challenging for a verification engineer. In this paper we propose a purely library-based verification approach, where libraries for checking elementary properties can be naturally connected with libraries for auxiliary functions to monitor complex AMS behaviors. We study the modeling of behaviors with the proposed library, and outline the main challenges and their solutions towards implementing the verification library over commercial AMS simulators.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114995174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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