In order for logic built-in-self-test (LBIST) to achieve coverages comparable with deterministic tests, multiple (and frequently many) seeds are often needed. Unlike previous methods that attempt to chain/compact the number of seeds, we present a novel Satisfiability Modulo Theory (SMT) based technique that can reduce the number of seeds significantly while simultaneously achieving high coverage for LBIST. In this technique we integrate the process of deterministic test generation and seed generation in one SMT process to eliminate the problems of chaining the separately generated deterministic patterns. Experimental results show the promise of the approach.
{"title":"A Novel SMT-Based Technique for LFSR Reseeding","authors":"S. Prabhu, M. Hsiao, L. Lingappan, V. Gangaram","doi":"10.1109/VLSID.2012.103","DOIUrl":"https://doi.org/10.1109/VLSID.2012.103","url":null,"abstract":"In order for logic built-in-self-test (LBIST) to achieve coverages comparable with deterministic tests, multiple (and frequently many) seeds are often needed. Unlike previous methods that attempt to chain/compact the number of seeds, we present a novel Satisfiability Modulo Theory (SMT) based technique that can reduce the number of seeds significantly while simultaneously achieving high coverage for LBIST. In this technique we integrate the process of deterministic test generation and seed generation in one SMT process to eliminate the problems of chaining the separately generated deterministic patterns. Experimental results show the promise of the approach.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126170280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Roy, A. Bhattacharya, R. Chaudhuri, T. K. Bhattacharyya
High-Q factor voltage controlled oscillators (VCO) need a wide tuning range and low phase noise over gigahertz ranges of frequency which depends on the tunability of the capacitors in the LC tank circuit. The reasons behind the development of a micro electro mechanical (MEM) varactor were the difficulties encountered in the realization of on-chip variable capacitors having low phase noise and high quality factors with a wide tuning range in the span of frequencies over process and temperature variations. This paper presents an efficient closed-form model for determination of the pull-in voltage in a surface micro machined MEM varactor which is a factor directly affecting the tunability of the device. The nonlinear spring hardening effects associated with proper load-deflection characteristics of clamped plates and the electrostatic spring softening effects due to the parallel-plate and fringing field capacitances have been taken into account with the dimensions of the device optimized through finite element analysis (FEA).
{"title":"Analysis of the Pull-In Phenomenon in Microelectromechanical Varactors","authors":"A. Roy, A. Bhattacharya, R. Chaudhuri, T. K. Bhattacharyya","doi":"10.1109/VLSID.2012.68","DOIUrl":"https://doi.org/10.1109/VLSID.2012.68","url":null,"abstract":"High-Q factor voltage controlled oscillators (VCO) need a wide tuning range and low phase noise over gigahertz ranges of frequency which depends on the tunability of the capacitors in the LC tank circuit. The reasons behind the development of a micro electro mechanical (MEM) varactor were the difficulties encountered in the realization of on-chip variable capacitors having low phase noise and high quality factors with a wide tuning range in the span of frequencies over process and temperature variations. This paper presents an efficient closed-form model for determination of the pull-in voltage in a surface micro machined MEM varactor which is a factor directly affecting the tunability of the device. The nonlinear spring hardening effects associated with proper load-deflection characteristics of clamped plates and the electrostatic spring softening effects due to the parallel-plate and fringing field capacitances have been taken into account with the dimensions of the device optimized through finite element analysis (FEA).","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127008764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Environmental energy harvesting is a promising approach to achieving extremely long operational lifetimes in a variety of micro-scale electronic systems. Maximum power point tracking (MPPT) is a technique used in energy harvesting systems to maximize the amount of harvested power. Existing MPPT methods, originally intended for large-scale systems, incur high power overheads when used in micro-scale energy harvesting, where the output voltage of the transducers is very low (less than 500mV) and the harvested power is miniscule (only hundreds of μW). This paper presents a low-overhead MPPT algorithm for micro-scale solar energy harvesting systems. The proposed algorithm is based on the use of a negative feedback control loop and is particularly amenable to hardware-efficient implementation. We have used the proposed algorithm to design a micro-scale solar energy harvesting system, which has been implemented using IBM 45nm technology. Post-layout simulation results demonstrate that the proposed MPPT scheme successfully tracks the optimal operating point with a tracking error of less than 1% and incurs minimal power overheads.
{"title":"Low-Overhead Maximum Power Point Tracking for Micro-Scale Solar Energy Harvesting Systems","authors":"Chao Lu, S. P. Park, V. Raghunathan, K. Roy","doi":"10.1109/VLSID.2012.73","DOIUrl":"https://doi.org/10.1109/VLSID.2012.73","url":null,"abstract":"Environmental energy harvesting is a promising approach to achieving extremely long operational lifetimes in a variety of micro-scale electronic systems. Maximum power point tracking (MPPT) is a technique used in energy harvesting systems to maximize the amount of harvested power. Existing MPPT methods, originally intended for large-scale systems, incur high power overheads when used in micro-scale energy harvesting, where the output voltage of the transducers is very low (less than 500mV) and the harvested power is miniscule (only hundreds of μW). This paper presents a low-overhead MPPT algorithm for micro-scale solar energy harvesting systems. The proposed algorithm is based on the use of a negative feedback control loop and is particularly amenable to hardware-efficient implementation. We have used the proposed algorithm to design a micro-scale solar energy harvesting system, which has been implemented using IBM 45nm technology. Post-layout simulation results demonstrate that the proposed MPPT scheme successfully tracks the optimal operating point with a tracking error of less than 1% and incurs minimal power overheads.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114226777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bodhisatwa Mazumdar, Debdeep Mukhopadhyay, I. Sengupta
This paper proposes an S-box construction of AES-128 block cipher which is more robust to differential power analysis (DPA) attacks than that of AES-128 implemented with Rijndael S-box while having similar cryptographic properties. The proposed S-box avoids use of countermeasures for thwarting DPA attacks thus consuming lesser area and power in the embedded hardware and still being more DPA resistive compared to Rijndael S-box. The design has been prototyped on Xilinx FPGA Spartan device XC3S400-4PQ208 and the power traces of the two different running AES-128 algorithms with the proposed and Rijndael S-boxes have been analyzed separately. The experimental results of the FPGA implementations show a lesser gate count consumption and increased throughput for the AES-128 with proposed S-box as that when implemented with Rijndael S-box on the same FPGA device. The requirement of higher number of power traces to perform DPA analysis on AES-128 with RAIN S-box as compared to that implemented with Rijndael S-box is an experimental validation of the theoretical claim of lower transparency order computed for RAIN S-box as being more DPA resistant than that of Rijndael S-box.
{"title":"Design for Security of Block Cipher S-Boxes to Resist Differential Power Attacks","authors":"Bodhisatwa Mazumdar, Debdeep Mukhopadhyay, I. Sengupta","doi":"10.1109/VLSID.2012.56","DOIUrl":"https://doi.org/10.1109/VLSID.2012.56","url":null,"abstract":"This paper proposes an S-box construction of AES-128 block cipher which is more robust to differential power analysis (DPA) attacks than that of AES-128 implemented with Rijndael S-box while having similar cryptographic properties. The proposed S-box avoids use of countermeasures for thwarting DPA attacks thus consuming lesser area and power in the embedded hardware and still being more DPA resistive compared to Rijndael S-box. The design has been prototyped on Xilinx FPGA Spartan device XC3S400-4PQ208 and the power traces of the two different running AES-128 algorithms with the proposed and Rijndael S-boxes have been analyzed separately. The experimental results of the FPGA implementations show a lesser gate count consumption and increased throughput for the AES-128 with proposed S-box as that when implemented with Rijndael S-box on the same FPGA device. The requirement of higher number of power traces to perform DPA analysis on AES-128 with RAIN S-box as compared to that implemented with Rijndael S-box is an experimental validation of the theoretical claim of lower transparency order computed for RAIN S-box as being more DPA resistant than that of Rijndael S-box.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133872684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This tutorial begins with a broad overview of challenges in emerging mixed signal systems. After describing the system-level requirements along with the architecture and circuit needs, specific circuit and system solutions will be discussed to highlight promising approaches. Design techniques for advanced analog- and mixed signal circuit blocks such as phase-locked loops and analog-to-digital converters will be covered in detail. Finally, the modeling and analysis of substrate noise coupling in mixed-signal integrated circuits is addressed. This day long tutorial addresses both the system- and circuit-level aspects of emerging mixed-signal systems. Analysis and design techniques to implement analog to digital converters, phase-locked loops, and the impact of substrate noise on these circuits in large system-on-chips will be discussed. The tutorial is categorized into the following four categories.
{"title":"Tutorial T5: Advanced Analog-Mixed Signal System and Circuit Techniques","authors":"P. Hanumolu, U. Moon, T. Fiez","doi":"10.1109/VLSID.2012.32","DOIUrl":"https://doi.org/10.1109/VLSID.2012.32","url":null,"abstract":"This tutorial begins with a broad overview of challenges in emerging mixed signal systems. After describing the system-level requirements along with the architecture and circuit needs, specific circuit and system solutions will be discussed to highlight promising approaches. Design techniques for advanced analog- and mixed signal circuit blocks such as phase-locked loops and analog-to-digital converters will be covered in detail. Finally, the modeling and analysis of substrate noise coupling in mixed-signal integrated circuits is addressed. This day long tutorial addresses both the system- and circuit-level aspects of emerging mixed-signal systems. Analysis and design techniques to implement analog to digital converters, phase-locked loops, and the impact of substrate noise on these circuits in large system-on-chips will be discussed. The tutorial is categorized into the following four categories.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133448957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a novel memory architecture, introducing Random Access Analog Memory (RA2M), to store unquantized samples of video signal of maximum 5 MHz bandwidth for storing time duration in order of millisecond by implementing periodic memory refreshing mechanism in it. At 16.5 MHz sampling frequency with 25 frames/s frame rate, this implemented design can store voltage signal sample of up to 200 mV for 40 ms with 8 bit resolution. The proposed architecture contains unit RA2M cell of 250 fF capacitance occupying 21 μm × 21 μm area with 4.1 mW average power dissipation per cell in 0.18 μm standard CMOS fabrication process. The improvement in signal storage time duration into analog memory by introducing periodic memory refreshing mechanism in voltage mode is implemented for the first time. The circuit implementation is based on switched capacitor technique and is compatible with conventional fabrication process. This architecture facilitates random location data accessibility and includes common mode noise rejection by its differential signal implementation.
{"title":"Random Access Analog Memory (RA2M) for Video Signal Application","authors":"Nilanjan Chattaraj, A. Dhar","doi":"10.1109/VLSID.2012.43","DOIUrl":"https://doi.org/10.1109/VLSID.2012.43","url":null,"abstract":"This paper proposes a novel memory architecture, introducing Random Access Analog Memory (RA2M), to store unquantized samples of video signal of maximum 5 MHz bandwidth for storing time duration in order of millisecond by implementing periodic memory refreshing mechanism in it. At 16.5 MHz sampling frequency with 25 frames/s frame rate, this implemented design can store voltage signal sample of up to 200 mV for 40 ms with 8 bit resolution. The proposed architecture contains unit RA2M cell of 250 fF capacitance occupying 21 μm × 21 μm area with 4.1 mW average power dissipation per cell in 0.18 μm standard CMOS fabrication process. The improvement in signal storage time duration into analog memory by introducing periodic memory refreshing mechanism in voltage mode is implemented for the first time. The circuit implementation is based on switched capacitor technique and is compatible with conventional fabrication process. This architecture facilitates random location data accessibility and includes common mode noise rejection by its differential signal implementation.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127882925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Sachid, Pallavi Paliwal, S. Joshi, M. Baghini, D. Sharma, V. Rao
With every new technology node, scaling down of Device-to-Interconnect Capacitance ratio causes Interconnect delay to become bottleneck for circuit performance. To miti-gate this effect, interconnect routing area on-chip should be minimized for improved power-delay product. In this aspect, Fin FET with multiple fins per lithographic pitch gains more advantage, in comparison to Planar Device, since, such Fin FET devices allow increase of electrical width without increasing device layout area and thus, interconnect capacitance is comparatively lower. Therefore, minimum delay could be achieved for lesser device width, and thus, with lower power. This paper proves the performance enhancement with such Fin FET Device for Mux Circuit, and aims to find out Optimum Design Space for Mux Circuit, at 22nm technology node, with practical value of Interconnect Capacitive load (extrapolated from circuit layout in current technology node).
{"title":"Circuit Optimization at 22nm Technology Node","authors":"A. Sachid, Pallavi Paliwal, S. Joshi, M. Baghini, D. Sharma, V. Rao","doi":"10.1109/VLSID.2012.91","DOIUrl":"https://doi.org/10.1109/VLSID.2012.91","url":null,"abstract":"With every new technology node, scaling down of Device-to-Interconnect Capacitance ratio causes Interconnect delay to become bottleneck for circuit performance. To miti-gate this effect, interconnect routing area on-chip should be minimized for improved power-delay product. In this aspect, Fin FET with multiple fins per lithographic pitch gains more advantage, in comparison to Planar Device, since, such Fin FET devices allow increase of electrical width without increasing device layout area and thus, interconnect capacitance is comparatively lower. Therefore, minimum delay could be achieved for lesser device width, and thus, with lower power. This paper proves the performance enhancement with such Fin FET Device for Mux Circuit, and aims to find out Optimum Design Space for Mux Circuit, at 22nm technology node, with practical value of Interconnect Capacitive load (extrapolated from circuit layout in current technology node).","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129875830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Effect of shadowing and/or backscattering of halo implant species from halo implant mask layer on leakage current of NMOS driver transistor of a 65nm SRAM cell is studied. The halo implant mask layer thickness has been varied from 100nm to 3000nm in steps, in response to this variation, leakage behavior of this NMOS transistor is observed. The leakage current of this transistor is shown to be a strong function of halo implant mask layer thickness with implant window width W=0.27mm. The poly gate is located approximately in the middle of this implant window. The leakage current is seen to increase monotonically by more than an order of magnitude with the increase in thickness till 500nm. When this thickness is increased beyond 500nm, the leakage current variation fits approximately into a damped oscillatory curve whose period is seen to be proportional to the width W of the halo implant window. The leakage current observed is 22nA for this NMOS device (with gate width Wn=120nm) at 500nm of halo implant mask layer thickness. Further when the halo implant window width W is increased beyond 0.27mm with the halo mask layer thickness fixed at 500nm, the leakage attained a minimum value of 0.54nA. All the leakage currents that are observed are in saturation region at cell Vdd=1.2V.
{"title":"Implications of Halo Implant Shadowing and Backscattering from Mask Layer Edges on Device Leakage Current in 65nm SRAM","authors":"H. C. Srinivasaiah","doi":"10.1109/VLSID.2012.106","DOIUrl":"https://doi.org/10.1109/VLSID.2012.106","url":null,"abstract":"Effect of shadowing and/or backscattering of halo implant species from halo implant mask layer on leakage current of NMOS driver transistor of a 65nm SRAM cell is studied. The halo implant mask layer thickness has been varied from 100nm to 3000nm in steps, in response to this variation, leakage behavior of this NMOS transistor is observed. The leakage current of this transistor is shown to be a strong function of halo implant mask layer thickness with implant window width W=0.27mm. The poly gate is located approximately in the middle of this implant window. The leakage current is seen to increase monotonically by more than an order of magnitude with the increase in thickness till 500nm. When this thickness is increased beyond 500nm, the leakage current variation fits approximately into a damped oscillatory curve whose period is seen to be proportional to the width W of the halo implant window. The leakage current observed is 22nA for this NMOS device (with gate width Wn=120nm) at 500nm of halo implant mask layer thickness. Further when the halo implant window width W is increased beyond 0.27mm with the halo mask layer thickness fixed at 500nm, the leakage attained a minimum value of 0.54nA. All the leakage currents that are observed are in saturation region at cell Vdd=1.2V.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123823832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Finite (Galois) field arithmetic finds applications in cryptography, error correction codes, signal processing, etc. Multiplication usually lies at the core of all Galois field computations and is a high-complexity operation. This paper addresses the problem of formal verification of hardware implementations of modulo-multipliers over Galois fields of the type F2k, using a computer-algebra/algebraic-geometry based approach. The multiplier circuit is modeled as a polynomial system in F2k[x1,x2,⋯,xd] and the verification test is formulated as a Nullstellensatz proof over the finite field. A Grobner basis engine is used as the underlying computational framework. The efficiency of Grobner basis computations depends heavily upon the variable (and term) ordering used to represent and manipulate the polynomials. We present a variable (and term) ordering heuristic that significantly improves the efficiency of Grobner basis engines. Using our approach, we can verify the correctness of up to 96-bit multipliers, whereas contemporary BDDs/SAT/SMT-solver based methods are infeasible.
{"title":"Formal Verification of Galois Field Multipliers Using Computer Algebra Techniques","authors":"Jinpeng Lv, P. Kalla","doi":"10.1109/VLSID.2012.102","DOIUrl":"https://doi.org/10.1109/VLSID.2012.102","url":null,"abstract":"Finite (Galois) field arithmetic finds applications in cryptography, error correction codes, signal processing, etc. Multiplication usually lies at the core of all Galois field computations and is a high-complexity operation. This paper addresses the problem of formal verification of hardware implementations of modulo-multipliers over Galois fields of the type F2k, using a computer-algebra/algebraic-geometry based approach. The multiplier circuit is modeled as a polynomial system in F2k[x1,x2,⋯,xd] and the verification test is formulated as a Nullstellensatz proof over the finite field. A Grobner basis engine is used as the underlying computational framework. The efficiency of Grobner basis computations depends heavily upon the variable (and term) ordering used to represent and manipulate the polynomials. We present a variable (and term) ordering heuristic that significantly improves the efficiency of Grobner basis engines. Using our approach, we can verify the correctness of up to 96-bit multipliers, whereas contemporary BDDs/SAT/SMT-solver based methods are infeasible.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129184098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As device geometries shrink to nanometers, increasing leakage current coupled with particle induced soft errors is exasperating the circuit reliability issues. In this paper, we first establish that independent solutions to these two problems can not lead to a good final solution. A more thoughtful and integrated design methodology is required to reconcile these two challenging issues. Next, we investigate the dependency of soft error rate on the body bias based leakage reduction method and introduce a novel body bias-dependent soft error model. We propose an optimization based and a heuristic driven approach to reduce leakage while satisfying the soft error rate limit. Our methods provide appropriate body bias configurations that lead to near-optimal total mean time to failure improvement of a circuit.
{"title":"Impact of Body Bias Based Leakage Power Reduction on Soft Error Rate","authors":"Warin Sootkaneung, K. Saluja","doi":"10.1109/VLSID.2012.49","DOIUrl":"https://doi.org/10.1109/VLSID.2012.49","url":null,"abstract":"As device geometries shrink to nanometers, increasing leakage current coupled with particle induced soft errors is exasperating the circuit reliability issues. In this paper, we first establish that independent solutions to these two problems can not lead to a good final solution. A more thoughtful and integrated design methodology is required to reconcile these two challenging issues. Next, we investigate the dependency of soft error rate on the body bias based leakage reduction method and introduce a novel body bias-dependent soft error model. We propose an optimization based and a heuristic driven approach to reduce leakage while satisfying the soft error rate limit. Our methods provide appropriate body bias configurations that lead to near-optimal total mean time to failure improvement of a circuit.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122973495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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