Conventional circuit dissipates energy to reload missing information because of overlapped mapping between input and output vectors. Reversibility recovers energy loss and prevents bit error by including Fault Tolerant mechanism. Reversible Computing is gaining the popularity of various fields such as Quantum Computing, DNA Informatics and CMOS Technology etc. In this paper, we have proposed the fault tolerant design of Reversible Full Adder (RFT-FA) with minimum quantum cost. Also we have proposed the cost effective design of Carry Skip Adder (CSA) and Carry Look-Ahead Adder (CLA) circuits by using proposed fault tolerant full adder circuit. The regular structures of n-bit Reversible Fault Tolerant Carry Skip Adder (RFT-CSA) and Carry Look-ahead Adder (RFT-CLA) by composing several theorems. Proposed designs have been populated by merging the minimization of total gates, garbage outputs, quantum cost and critical path delay criterion and comparing with exiting designs.
{"title":"Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis","authors":"Sajib Kumar Mitra, A. Chowdhury","doi":"10.1109/VLSID.2012.93","DOIUrl":"https://doi.org/10.1109/VLSID.2012.93","url":null,"abstract":"Conventional circuit dissipates energy to reload missing information because of overlapped mapping between input and output vectors. Reversibility recovers energy loss and prevents bit error by including Fault Tolerant mechanism. Reversible Computing is gaining the popularity of various fields such as Quantum Computing, DNA Informatics and CMOS Technology etc. In this paper, we have proposed the fault tolerant design of Reversible Full Adder (RFT-FA) with minimum quantum cost. Also we have proposed the cost effective design of Carry Skip Adder (CSA) and Carry Look-Ahead Adder (CLA) circuits by using proposed fault tolerant full adder circuit. The regular structures of n-bit Reversible Fault Tolerant Carry Skip Adder (RFT-CSA) and Carry Look-ahead Adder (RFT-CLA) by composing several theorems. Proposed designs have been populated by merging the minimization of total gates, garbage outputs, quantum cost and critical path delay criterion and comparing with exiting designs.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114626714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With increasing performance-per-watt implementation requirements for emerging applications and barriers in interconnect scaling for ultra-deep sub micron (UDSM) technologies, traditional 2D integrated circuits (2D-ICs) are being pushed to their limit. Three dimensional integrated circuits (3D-ICs) have recently emerged as a promising solution that can overcome many of the performance, area, and power concerns in 2D-ICs. In this paper we propose a novel framework (MORPHEUS) for the synthesis of application-specific 3D networks on chip (NoCs). The goal is to generate 3D NoCs that meet application performance constraints while minimizing power dissipation. MORPHEUS incorporates thermal-aware core layout, 3D topology and route generation, and placement of network interfaces (NIs), routers, and serialized vertical through silicon vias (TSVs). Experimental studies on several chip multiprocessor (CMP) applications indicate that our generated solutions notably reduce power dissipation (up to 2.3×) and average latency (up to 1.2×) over 2D NoCs. Comparisons with a previous work on application-specific 3D NoC synthesis also show improvements in power dissipation (up to 1.9×) and average latency (up to 1.6×).
{"title":"A Framework for TSV Serialization-aware Synthesis of Application Specific 3D Networks-on-Chip","authors":"S. Pasricha","doi":"10.1109/VLSID.2012.82","DOIUrl":"https://doi.org/10.1109/VLSID.2012.82","url":null,"abstract":"With increasing performance-per-watt implementation requirements for emerging applications and barriers in interconnect scaling for ultra-deep sub micron (UDSM) technologies, traditional 2D integrated circuits (2D-ICs) are being pushed to their limit. Three dimensional integrated circuits (3D-ICs) have recently emerged as a promising solution that can overcome many of the performance, area, and power concerns in 2D-ICs. In this paper we propose a novel framework (MORPHEUS) for the synthesis of application-specific 3D networks on chip (NoCs). The goal is to generate 3D NoCs that meet application performance constraints while minimizing power dissipation. MORPHEUS incorporates thermal-aware core layout, 3D topology and route generation, and placement of network interfaces (NIs), routers, and serialized vertical through silicon vias (TSVs). Experimental studies on several chip multiprocessor (CMP) applications indicate that our generated solutions notably reduce power dissipation (up to 2.3×) and average latency (up to 1.2×) over 2D NoCs. Comparisons with a previous work on application-specific 3D NoC synthesis also show improvements in power dissipation (up to 1.9×) and average latency (up to 1.6×).","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114345434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Vudadha, G. Makkena, M. Nayudu, P. Phaneendra, Syed Ershad Ahmed, S. Veeramachaneni, N. Muthukrishnan, M. Srinivas
This paper presents a new improved multiplexer based decoder for flash analog-to-digital converters. The proposed decoder is based on 2:1 multiplexers. It calculates the binary code for low operand length thermometer code at initial stages and groups the output of initial stages to generate the final result. The proposed decoder can be configured to operate on thermometer code with reduced length without any extra overhead. This 'self-reconfigurable' property is particularly useful in adaptive resolution analog-to-digital converters. Simulation results indicate that the proposed decoder results in reduced delay, power and power delay product when compared to existing digital decoders for flash analog-digital converters.
{"title":"Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs","authors":"C. Vudadha, G. Makkena, M. Nayudu, P. Phaneendra, Syed Ershad Ahmed, S. Veeramachaneni, N. Muthukrishnan, M. Srinivas","doi":"10.1109/VLSID.2012.84","DOIUrl":"https://doi.org/10.1109/VLSID.2012.84","url":null,"abstract":"This paper presents a new improved multiplexer based decoder for flash analog-to-digital converters. The proposed decoder is based on 2:1 multiplexers. It calculates the binary code for low operand length thermometer code at initial stages and groups the output of initial stages to generate the final result. The proposed decoder can be configured to operate on thermometer code with reduced length without any extra overhead. This 'self-reconfigurable' property is particularly useful in adaptive resolution analog-to-digital converters. Simulation results indicate that the proposed decoder results in reduced delay, power and power delay product when compared to existing digital decoders for flash analog-digital converters.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123019174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a companding continuous-time ΔΣ ADC for audio applications. The 3rd-order modulator uses a 3-bit companding quantizer and has an over sampling rate of 64. The companding quantizer is implemented by a log amplifier followed by a flash ADC. The modulator, in simulation, achieves a peak signal-to-noise ratio of 76 dB, a dynamic range of 110 dB in a 24 kHz bandwidth and dissipates 860 μW of power.
{"title":"A 110-dB Dynamic Range, 76-dB Peak SNR Companding Continuous-Time ?S Modulator for Audio Applications","authors":"Saravana Kumar, S. Chatterjee","doi":"10.1109/VLSID.2012.45","DOIUrl":"https://doi.org/10.1109/VLSID.2012.45","url":null,"abstract":"This paper presents a companding continuous-time ΔΣ ADC for audio applications. The 3rd-order modulator uses a 3-bit companding quantizer and has an over sampling rate of 64. The companding quantizer is implemented by a log amplifier followed by a flash ADC. The modulator, in simulation, achieves a peak signal-to-noise ratio of 76 dB, a dynamic range of 110 dB in a 24 kHz bandwidth and dissipates 860 μW of power.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126929923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Resonant rotary clocking is a high-frequency, low-power technology for high performance integrated circuits (IC). The implementation of the rotary clocking technology requires long interconnects with varying geometric shape segments on the chip, which are modeled by transmission lines. The parasitics exhibited by the transmission line interconnects play a major role in characterizing the high frequency operation. To this end, the impact of parasitics on the operating characteristics of the rotary rings due to the different interconnect segments are identified. The interconnect parasitics are analyzed using a 3D finite element method based full wave electromagnetic analysis. Simulations performed for the rotary ring with 3D full wave based parasitic analysis results in 23.68% reduced clock frequency when compared with a conventional 2D based parasitic analysis. The power dissipated on the rotary ring simulated using the 3D full wave based parasitic analysis is around 84% less than the clock tree and is within 5% of the power dissipated on the ring simulated using the 2D based parasitic analysis.
{"title":"3-D Parasitic Modeling for Rotary Interconnects","authors":"V. Honkote, A. More, B. Taskin","doi":"10.1109/VLSID.2012.60","DOIUrl":"https://doi.org/10.1109/VLSID.2012.60","url":null,"abstract":"Resonant rotary clocking is a high-frequency, low-power technology for high performance integrated circuits (IC). The implementation of the rotary clocking technology requires long interconnects with varying geometric shape segments on the chip, which are modeled by transmission lines. The parasitics exhibited by the transmission line interconnects play a major role in characterizing the high frequency operation. To this end, the impact of parasitics on the operating characteristics of the rotary rings due to the different interconnect segments are identified. The interconnect parasitics are analyzed using a 3D finite element method based full wave electromagnetic analysis. Simulations performed for the rotary ring with 3D full wave based parasitic analysis results in 23.68% reduced clock frequency when compared with a conventional 2D based parasitic analysis. The power dissipated on the rotary ring simulated using the 3D full wave based parasitic analysis is around 84% less than the clock tree and is within 5% of the power dissipated on the ring simulated using the 2D based parasitic analysis.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129189672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Mukherjee, H. Rahaman, I. Banerjee, T. Samanta, P. Dasgupta
Design automation in Digital micro fluidic biochip is of immense importance in to days clinical diagnosis process. In this paper, we try to build a heuristic algorithm to simultaneously perform droplet routing and electrode actuation. The proposed method is capable of performing (i) droplet routing with minimal electrode usages in optimized routing completion time, and (ii) minimal number of control pin assignment on the routing path for successful droplet transportation. The proposed method is a co-optimization technique that finds the possible shortest path between the source and the target pair for a droplet and assigns control pins in an optimal manner to actuate the routing path. Intersection regions for multiple droplets are also assigned with pins in an efficient manner to avoid unnecessary mixing between several droplets. The proposed method is tested on various benchmarks and random test sets, and experimental results are quite encouraging.
{"title":"A Heuristic Method for Co-optimization of Pin Assignment and Droplet Routing in Digital Microfluidic Biochip","authors":"R. Mukherjee, H. Rahaman, I. Banerjee, T. Samanta, P. Dasgupta","doi":"10.1109/VLSID.2012.75","DOIUrl":"https://doi.org/10.1109/VLSID.2012.75","url":null,"abstract":"Design automation in Digital micro fluidic biochip is of immense importance in to days clinical diagnosis process. In this paper, we try to build a heuristic algorithm to simultaneously perform droplet routing and electrode actuation. The proposed method is capable of performing (i) droplet routing with minimal electrode usages in optimized routing completion time, and (ii) minimal number of control pin assignment on the routing path for successful droplet transportation. The proposed method is a co-optimization technique that finds the possible shortest path between the source and the target pair for a droplet and assigns control pins in an optimal manner to actuate the routing path. Intersection regions for multiple droplets are also assigned with pins in an efficient manner to avoid unnecessary mixing between several droplets. The proposed method is tested on various benchmarks and random test sets, and experimental results are quite encouraging.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116953682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Digital Subscriber Line (DSL) is a family of standards that allow existing twisted pair copper lines to carry modulated digital signals which uses telephone network and unused frequency Spectrum. In this tutorial we describe DSL (Digital Subscriber Line), comparing with POTS and ISDN. We explain the different DSL flavors available with the modulation techniques used and also discuss challenges in getting high performance and throughput, achieving xDSL rate and meeting the DSL standard. We begin by introducing DSL having a pair of modems CO (Central office) and CPE (Customer Premises Equipment) and talk about frequency spectrums. We explain the limitations of POTS (Plain Old Telephone System) with Dial-up Connection and ISDN (Integrated Services Digital Network), and advantages of DSL over POTS. Next we describe various flavors of DSL with their frequency spectrums, power enhancements, standardization, profiles, and band plans. We discuss different modulation techniques with their advantages and disadvantages, including Single carrier Modulation like CAP and QAM and Multi Carrier Modulation like DMT. We explain the interferers/noise: Line Attenuation, The channel attenuation, Bridged taps, Impulse noise, White noise, NEXT, FEXT, RE Interference. We conclude the tutorial with a description of full activation and initialization phases. The targeted audience for the tutorial is designers, developers, testers, people working in the area of VDSL, ADSL technology and People working on different platforms like DSLAM's, Central office, Customer premises equipment, Gateway products as well as products related to access network who are familiar with copper line and modems.
{"title":"Embedded Tutorial ET2: Digital Subscriber Line","authors":"M. K. K. Rao, V. ShanthaKumariP., B. Sellappan","doi":"10.1109/VLSID.2012.41","DOIUrl":"https://doi.org/10.1109/VLSID.2012.41","url":null,"abstract":"Digital Subscriber Line (DSL) is a family of standards that allow existing twisted pair copper lines to carry modulated digital signals which uses telephone network and unused frequency Spectrum. In this tutorial we describe DSL (Digital Subscriber Line), comparing with POTS and ISDN. We explain the different DSL flavors available with the modulation techniques used and also discuss challenges in getting high performance and throughput, achieving xDSL rate and meeting the DSL standard. We begin by introducing DSL having a pair of modems CO (Central office) and CPE (Customer Premises Equipment) and talk about frequency spectrums. We explain the limitations of POTS (Plain Old Telephone System) with Dial-up Connection and ISDN (Integrated Services Digital Network), and advantages of DSL over POTS. Next we describe various flavors of DSL with their frequency spectrums, power enhancements, standardization, profiles, and band plans. We discuss different modulation techniques with their advantages and disadvantages, including Single carrier Modulation like CAP and QAM and Multi Carrier Modulation like DMT. We explain the interferers/noise: Line Attenuation, The channel attenuation, Bridged taps, Impulse noise, White noise, NEXT, FEXT, RE Interference. We conclude the tutorial with a description of full activation and initialization phases. The targeted audience for the tutorial is designers, developers, testers, people working in the area of VDSL, ADSL technology and People working on different platforms like DSLAM's, Central office, Customer premises equipment, Gateway products as well as products related to access network who are familiar with copper line and modems.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126228679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the implementation of a 3GPP standards compliant configurable turbo decoder on a GPU. The challenge in implementing a turbo decoder on a GPU is in suitably parallelizing the Log-MAP decoding algorithm and doing an architecture aware mapping of it on to the GPU. The approximations in parallelizing the Log-MAP algorithm come at the cost of reduced BER performance. To mitigate this reduction, different guarding mechanisms of varying computational complexity have been presented. The limited shared memory and registers available on GPUs are carefully allocated to obtain a high real-time decoding rate without requiring several independent data streams in parallel.
{"title":"GPU Implementation of a Programmable Turbo Decoder for Software Defined Radio Applications","authors":"Dhiraj Reddy Nallapa Yoge, N. Chandrachoodan","doi":"10.1109/VLSID.2012.62","DOIUrl":"https://doi.org/10.1109/VLSID.2012.62","url":null,"abstract":"This paper presents the implementation of a 3GPP standards compliant configurable turbo decoder on a GPU. The challenge in implementing a turbo decoder on a GPU is in suitably parallelizing the Log-MAP decoding algorithm and doing an architecture aware mapping of it on to the GPU. The approximations in parallelizing the Log-MAP algorithm come at the cost of reduced BER performance. To mitigate this reduction, different guarding mechanisms of varying computational complexity have been presented. The limited shared memory and registers available on GPUs are carefully allocated to obtain a high real-time decoding rate without requiring several independent data streams in parallel.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124232089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
High performance video standards use prediction techniques to achieve high picture quality at low bit rates. The type of prediction decides the bit rates and the image quality. Intra Prediction achieves high video quality with significant reduction in bit rate. This paper presents novel area optimized architecture for Intra prediction of H.264 decoding at HDTV resolution. The architecture has been validated on a Xilinx Virtex-5 FPGA based platform and achieved a frame rate of 64 fps. The architecture is based on multi-level memory hierarchy to reduce latency and ensure optimum resources utilization. It removes redundancy by reusing same functional blocks across different modes. The proposed architecture uses only 13% of the total LUTs available on the Xilinx FPGA XC5VLX50T.
{"title":"HD Resolution Intra Prediction Architecture for H.264 Decoder","authors":"Jimit Shah, K. S. Raghunandan, Kuruvilla Varghese","doi":"10.1109/VLSID.2012.55","DOIUrl":"https://doi.org/10.1109/VLSID.2012.55","url":null,"abstract":"High performance video standards use prediction techniques to achieve high picture quality at low bit rates. The type of prediction decides the bit rates and the image quality. Intra Prediction achieves high video quality with significant reduction in bit rate. This paper presents novel area optimized architecture for Intra prediction of H.264 decoding at HDTV resolution. The architecture has been validated on a Xilinx Virtex-5 FPGA based platform and achieved a frame rate of 64 fps. The architecture is based on multi-level memory hierarchy to reduce latency and ensure optimum resources utilization. It removes redundancy by reusing same functional blocks across different modes. The proposed architecture uses only 13% of the total LUTs available on the Xilinx FPGA XC5VLX50T.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131708822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Among different multi-gate transistors, Fin FETs and Trigate FETs have set themselves apart as the most promising candidates for the upcoming 22nm technology node and beyond owing to their superior device performance, lower leakage power consumption and cost-effective fabrication process. Innovative circuit design and optimization techniques will be required to harness the power of multi-gate transistors, which in turn will depend on accurate leakage and timing characterization of these devices under spatial and environmental variations. Hence, in order to aid circuit designers, we present accurate analytical models using central composite rotatable design (CCRD) based on response surface methodology (RSM) to estimate the leakage current in Fin FET standard cells under the effect of variations in gate length (LG), fin thickness (TSI), gate-oxide thickness (TOX) and gate-work function (ΦG). To the best of our knowledge, this is the first attempt to develop analytical models for leakage estimation of Fin FET devices/logic gates based on TCAD simulations of adjusted 2D device cross-sections that have been shown to track TCAD simulations of 3D device behavior within a 1-3% error range. This drastically reduces the CPU time of our modeling technique (by several orders of magnitude) without much loss in accuracy. We present analytical leakage models for different logic styles, e.g., shorted-gate (SG) and independent-gate (IG) Fin FETs, at the 22nm technology node. The leakage estimates derived from the analytical models are in close agreement with quasi-Monte Carlo (QMC) simulation results obtained for different adjusted-2D (3D) devices/logic gates with a maximum root mean square error (RMSE) of 5.28% (7.03%).
在不同的多栅极晶体管中，Fin fet和Trigate fet由于其优越的器件性能、更低的泄漏功耗和具有成本效益的制造工艺，已成为即将到来的22nm技术节点最有前途的候选者。创新的电路设计和优化技术将需要利用多栅极晶体管的功率，这反过来又取决于这些器件在空间和环境变化下的准确泄漏和定时特性。因此，为了帮助电路设计者，我们提出了基于响应面方法(RSM)的中心复合可旋转设计(CCRD)的精确分析模型，以估计在栅极长度(LG)，鳍片厚度(TSI)，栅极氧化厚度(TOX)和栅极功函数(ΦG)变化的影响下，Fin FET标准电池中的泄漏电流。据我们所知，这是基于调整后的2D器件横截面的TCAD模拟开发Fin FET器件/逻辑门泄漏估计的分析模型的第一次尝试，该模型已被证明可以在1-3%的误差范围内跟踪3D器件行为的TCAD模拟。这极大地减少了我们建模技术的CPU时间(减少了几个数量级)，而精度没有很大的损失。我们提出了不同逻辑风格的解析泄漏模型，例如在22nm技术节点上的短门(SG)和独立门(IG) Fin fet。从分析模型中得出的泄漏估计与准蒙特卡罗(QMC)模拟结果非常吻合，不同的可调2d (3D)器件/逻辑门的最大均方根误差(RMSE)为5.28%(7.03%)。
{"title":"Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology","authors":"S. Chaudhuri, Prateek Mishra, N. Jha","doi":"10.1109/VLSID.2012.77","DOIUrl":"https://doi.org/10.1109/VLSID.2012.77","url":null,"abstract":"Among different multi-gate transistors, Fin FETs and Trigate FETs have set themselves apart as the most promising candidates for the upcoming 22nm technology node and beyond owing to their superior device performance, lower leakage power consumption and cost-effective fabrication process. Innovative circuit design and optimization techniques will be required to harness the power of multi-gate transistors, which in turn will depend on accurate leakage and timing characterization of these devices under spatial and environmental variations. Hence, in order to aid circuit designers, we present accurate analytical models using central composite rotatable design (CCRD) based on response surface methodology (RSM) to estimate the leakage current in Fin FET standard cells under the effect of variations in gate length (LG), fin thickness (TSI), gate-oxide thickness (TOX) and gate-work function (ΦG). To the best of our knowledge, this is the first attempt to develop analytical models for leakage estimation of Fin FET devices/logic gates based on TCAD simulations of adjusted 2D device cross-sections that have been shown to track TCAD simulations of 3D device behavior within a 1-3% error range. This drastically reduces the CPU time of our modeling technique (by several orders of magnitude) without much loss in accuracy. We present analytical leakage models for different logic styles, e.g., shorted-gate (SG) and independent-gate (IG) Fin FETs, at the 22nm technology node. The leakage estimates derived from the analytical models are in close agreement with quasi-Monte Carlo (QMC) simulation results obtained for different adjusted-2D (3D) devices/logic gates with a maximum root mean square error (RMSE) of 5.28% (7.03%).","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120938921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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