In this paper we introduce a novel interface for Globally-Asynchronous, Locally-Synchronous systems which does not use any form of handshake to cross the gap between the clock domains. In particular, links in which the Receiver runs faster than the Transmitter are targeted. The interface works by finding an approximate ratio between the clock frequencies. Then, ratiochronous synchronizers that can tolerate clock drifts are employed to transmit data from the Transmitter to the Receiver clock domain. Thanks to the periodic properties of rationally-related systems, no handshake is employed and the average latency of the interface is decreased 75 % compared to state-of-the-art GALS interfaces. Additionally, the interface uses only standard cells and, save for a delay line, can be designed at Register Transfer Level.
{"title":"Low-Latency No-Handshake GALS Interfaces for Fast-Receiver Links","authors":"Jean-Michel Chabloz, A. Hemani","doi":"10.1109/VLSID.2012.69","DOIUrl":"https://doi.org/10.1109/VLSID.2012.69","url":null,"abstract":"In this paper we introduce a novel interface for Globally-Asynchronous, Locally-Synchronous systems which does not use any form of handshake to cross the gap between the clock domains. In particular, links in which the Receiver runs faster than the Transmitter are targeted. The interface works by finding an approximate ratio between the clock frequencies. Then, ratiochronous synchronizers that can tolerate clock drifts are employed to transmit data from the Transmitter to the Receiver clock domain. Thanks to the periodic properties of rationally-related systems, no handshake is employed and the average latency of the interface is decreased 75 % compared to state-of-the-art GALS interfaces. Additionally, the interface uses only standard cells and, save for a delay line, can be designed at Register Transfer Level.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114942175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As SoC design becomes larger and more complex, verification engineers are expanding constrained-random testing to meet the validation demand. This expansion creates a new set of challenges: engineers now face exponentially growing verification performance and capacity issues. It is no longer enough to write constraints that simply function to validate a design. Today, engineers must also optimize the constraints they write for performance if they wish to have any hope of both successfully validating their design and meeting their deadlines. In this tutorial, we discuss a scalable methodology for writing constraints and optimizing performance is which will improve engineers' productivity to write and debug ever-increasing amounts of larger, more complex sets of constraints. Our goal is to reduce the time needed for functional convergence, and later for debug and volume manufacturing. We will also discuss the vital role of Verification IP providers and users in this scenario.
{"title":"Tutorial T7B: Optimally Addressing Verification Constraint Complexity for Effective Functional Convergence","authors":"S. Hemmady","doi":"10.1109/VLSID.2012.35","DOIUrl":"https://doi.org/10.1109/VLSID.2012.35","url":null,"abstract":"As SoC design becomes larger and more complex, verification engineers are expanding constrained-random testing to meet the validation demand. This expansion creates a new set of challenges: engineers now face exponentially growing verification performance and capacity issues. It is no longer enough to write constraints that simply function to validate a design. Today, engineers must also optimize the constraints they write for performance if they wish to have any hope of both successfully validating their design and meeting their deadlines. In this tutorial, we discuss a scalable methodology for writing constraints and optimizing performance is which will improve engineers' productivity to write and debug ever-increasing amounts of larger, more complex sets of constraints. Our goal is to reduce the time needed for functional convergence, and later for debug and volume manufacturing. We will also discuss the vital role of Verification IP providers and users in this scenario.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121716049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Abercrombie, B. Koenemann, Nagesh Tamarapalli, S. Venkataraman
Semiconductor yield has traditionally been limited by random particle-defect based issues. However, as the feature sizes reduced to 90nm and below, systematic mechanism-limited yield loss began to appear as a substantial component in yield loss. In addition, it is becoming clear that ramping yield would take longer and final yields would not reach historical norms. A key factor for not reaching previously attained yield levels is the interaction between design and manufacturing. Yield losses in the newer processes include functional defects, parametric defects and issues with testing. Each of these sources of yield loss needs to be analyzed and understood by designers and tool developers. In addition, new techniques and methods must be devised to minimize the impact of these yield loss mechanisms. After an introduction of the issues involved in the first section, the second section covers Design-for- Manufacturing (DFM) techniques to analyze the design content, flag areas of design that could limit yield, and make changes to improve yield. However, once the changes are made it is necessary to quantify their impact so that knowledge about yield contribution of different features can be fed back to design and DFM tools. Test presents an opportunity to close the loop by crafting test patterns to expose the defect prone features during automatic test pattern generation (ATPG) and by analyzing silicon failures through diagnosis to determine the features that are actually causing yield loss and their relative impact. The third section covers design techniques (DFX) to improve testability, debuggability and diagnosability, and DFM and defect-aware test generation to both meet product quality and expose yield issues at test. Section four covers the basic concepts and theoretical aspects of debug and diagnosis including algorithmic IC diagnosis, scan chain diagnosis, critical path based techniques and diagnosis of delay defects. The applications of the basic concepts and techniques for silicon debug are covered in section five. Section six covers the application of statistical diagnosis techniques to determine the features that are actually causing yield loss and their relative impact. Finally, in section seven, future trends, challenges and directions are covered. The proposed tutorial includes the basics to be of interest to students, new engineers and managers but covers new and recent advances in hot topics in Design-for-Manufacturing, yield, test and diagnosis to be of interest to researchers and practicing engineers. The selection of topics cover a broad spectrum and will be of interest to a wide audience including design, test, product, validation, yield, debug and FA engineers.
{"title":"Tutorial T3: DFM, DFT, Silicon Debug and Diagnosis -- The Loop to Ensure Product Yield","authors":"D. Abercrombie, B. Koenemann, Nagesh Tamarapalli, S. Venkataraman","doi":"10.1109/VLSID.2006.73","DOIUrl":"https://doi.org/10.1109/VLSID.2006.73","url":null,"abstract":"Semiconductor yield has traditionally been limited by random particle-defect based issues. However, as the feature sizes reduced to 90nm and below, systematic mechanism-limited yield loss began to appear as a substantial component in yield loss. In addition, it is becoming clear that ramping yield would take longer and final yields would not reach historical norms. A key factor for not reaching previously attained yield levels is the interaction between design and manufacturing. Yield losses in the newer processes include functional defects, parametric defects and issues with testing. Each of these sources of yield loss needs to be analyzed and understood by designers and tool developers. In addition, new techniques and methods must be devised to minimize the impact of these yield loss mechanisms. After an introduction of the issues involved in the first section, the second section covers Design-for- Manufacturing (DFM) techniques to analyze the design content, flag areas of design that could limit yield, and make changes to improve yield. However, once the changes are made it is necessary to quantify their impact so that knowledge about yield contribution of different features can be fed back to design and DFM tools. Test presents an opportunity to close the loop by crafting test patterns to expose the defect prone features during automatic test pattern generation (ATPG) and by analyzing silicon failures through diagnosis to determine the features that are actually causing yield loss and their relative impact. The third section covers design techniques (DFX) to improve testability, debuggability and diagnosability, and DFM and defect-aware test generation to both meet product quality and expose yield issues at test. Section four covers the basic concepts and theoretical aspects of debug and diagnosis including algorithmic IC diagnosis, scan chain diagnosis, critical path based techniques and diagnosis of delay defects. The applications of the basic concepts and techniques for silicon debug are covered in section five. Section six covers the application of statistical diagnosis techniques to determine the features that are actually causing yield loss and their relative impact. Finally, in section seven, future trends, challenges and directions are covered. The proposed tutorial includes the basics to be of interest to students, new engineers and managers but covers new and recent advances in hot topics in Design-for-Manufacturing, yield, test and diagnosis to be of interest to researchers and practicing engineers. The selection of topics cover a broad spectrum and will be of interest to a wide audience including design, test, product, validation, yield, debug and FA engineers.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115288487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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