J. W. Wells, Jayaram Natarajan, A. Chatterjee, I. Barlas
In this paper, a content aware, low power video encoder design is presented in which the algorithms and hardware are co-optimized to adapt concurrently to video content in real-time. Natural image statistical models are used to form spatiotemporal predictions about the content of future frames. A key innovation in this work is that that the predictions are used as parameters in a feedback control loop to intelligently down sample (change the resolution of the frame image across different parts of the image) the video encoder input immediately at the camera, thus reducing the amount of work required by the encoder per frame. A multiresolution frame representation is used to produce regular data structures which allow for efficient hardware design. The hardware is co-optimized with the algorithm to reduce power based on the reduced input size resulting from the algorithm. The design also allows for selectable, graceful degradation of video quality while reducing power consumption.
{"title":"Real-Time, Content Aware Camera -- Algorithm -- Hardware Co-Adaptation for Minimal Power Video Encoding","authors":"J. W. Wells, Jayaram Natarajan, A. Chatterjee, I. Barlas","doi":"10.1109/VLSID.2012.78","DOIUrl":"https://doi.org/10.1109/VLSID.2012.78","url":null,"abstract":"In this paper, a content aware, low power video encoder design is presented in which the algorithms and hardware are co-optimized to adapt concurrently to video content in real-time. Natural image statistical models are used to form spatiotemporal predictions about the content of future frames. A key innovation in this work is that that the predictions are used as parameters in a feedback control loop to intelligently down sample (change the resolution of the frame image across different parts of the image) the video encoder input immediately at the camera, thus reducing the amount of work required by the encoder per frame. A multiresolution frame representation is used to produce regular data structures which allow for efficient hardware design. The hardware is co-optimized with the algorithm to reduce power based on the reduced input size resulting from the algorithm. The design also allows for selectable, graceful degradation of video quality while reducing power consumption.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115192747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given: Pervasiveness of wireless technology is impacting every aspect of the society and is becoming a de facto feature of any electronic product. This tutorial provides a comprehensive overview of wireless system design and brings out the systems engineering issues through real-life design case studies. It begins with an overview of a typical wireless system and the underlying RF technology. Next, a detailed view of wireless system design with mathematical underpinning of concepts and design of sub-systems will be presented; it highlights systems engineering issues in wireless product development. Subsequently, the tutorial presents the relevant system design case studies, for various wireless applications viz; medical electronics, consumer electronics, defense, telecommunications etc., and explains the methodologies to address the systems engineering issues. Finally, the tutorial explains the trends in future wireless systems design and the associated challenges. The last session concludes the tutorial, followed by a discussion.
{"title":"Tutorial T8B: Wireless System Design and Systems Engineering Challenges","authors":"Kameswara Rao, M. B. Reddy, Ravi Kishore","doi":"10.1109/VLSID.2012.37","DOIUrl":"https://doi.org/10.1109/VLSID.2012.37","url":null,"abstract":"Summary form only given: Pervasiveness of wireless technology is impacting every aspect of the society and is becoming a de facto feature of any electronic product. This tutorial provides a comprehensive overview of wireless system design and brings out the systems engineering issues through real-life design case studies. It begins with an overview of a typical wireless system and the underlying RF technology. Next, a detailed view of wireless system design with mathematical underpinning of concepts and design of sub-systems will be presented; it highlights systems engineering issues in wireless product development. Subsequently, the tutorial presents the relevant system design case studies, for various wireless applications viz; medical electronics, consumer electronics, defense, telecommunications etc., and explains the methodologies to address the systems engineering issues. Finally, the tutorial explains the trends in future wireless systems design and the associated challenges. The last session concludes the tutorial, followed by a discussion.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121430312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A fast equation free iterative approach for sizing of analog circuit is proposed. Equation based sizing approach has been popular as it removes time consuming simulation effort. If equations are cast in posynomial inequality format, a special optimization technique called geometric programming(GP) can be deployed. The advantage of formulating the problem in GP form is that, it ensures global optimality and can return the final design point instantly even in the presence of hundreds of equation and thousands of variable. But main limitation comes in deriving performance equations in posynomial inequality format. In this context, we develop one novel methodology for fast sizing of analog circuit. This method does not require any such performance expressions. It is based on the meaningful presentation of only device constraints. Infeasibility is handled iteratively making suitable changes on those constraints. Due to the simplicity of formulation, fully automated flow is achieved.
{"title":"A Fast Equation Free Iterative Approach to Analog Circuit Sizing","authors":"S. Maji, P. Mandal","doi":"10.1109/VLSID.2012.99","DOIUrl":"https://doi.org/10.1109/VLSID.2012.99","url":null,"abstract":"A fast equation free iterative approach for sizing of analog circuit is proposed. Equation based sizing approach has been popular as it removes time consuming simulation effort. If equations are cast in posynomial inequality format, a special optimization technique called geometric programming(GP) can be deployed. The advantage of formulating the problem in GP form is that, it ensures global optimality and can return the final design point instantly even in the presence of hundreds of equation and thousands of variable. But main limitation comes in deriving performance equations in posynomial inequality format. In this context, we develop one novel methodology for fast sizing of analog circuit. This method does not require any such performance expressions. It is based on the meaningful presentation of only device constraints. Infeasibility is handled iteratively making suitable changes on those constraints. Due to the simplicity of formulation, fully automated flow is achieved.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116541400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gigascale integration in recent semiconductor technology mandates design reuse in order to meet the design specifications in time. Electronic description of VLSI design being an intellectual property (IP), may be infringed upon during design reuse. This calls for incorporating techniques for intellectual property protection in the VLSI design flow. The IP of VLSI design, which culminates in fabrication of the integrated circuit, differs from other sources of IPs because in addition to its physical and structural description, it has also a behavioral specification which should remain unaltered after application of IP protection techniques. Security in activation of chips, especially in embedded systems, is an equally grave issue and has led to the paradigm of design-for-security. This tutorial aims at presenting the major concerns related to IP security that are significant to both the circuit designers and developers of CAD tools. The nature of threats are broadly categorized as (i) misappropriation by hacking during electronic commerce and intentional reselling mostly at design level, and (ii) unauthorized design retrieval. Various attack models and the mechanisms for effective counter measures such as encryption, obfuscation, watermarking and fingerprinting, and certain analytic methods derived from the behavioral aspect, specific to chip designs, will be discussed. First, the scenario of digital rights management, attack models and security goals will be described. Next, the existing approaches for protection of soft IPs such as HDL codes, firm IPs especially at the value-added layout level, and hard IPs including DFM-enhanced layout will be presented. This will include a number of published research results by the presenters. Finally, the recent advances in tackling security issues for design of smart cards and crypto processors will be surveyed.
{"title":"Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design","authors":"S. Sur-Kolay, S. Bhunia","doi":"10.1109/VLSID.2012.31","DOIUrl":"https://doi.org/10.1109/VLSID.2012.31","url":null,"abstract":"Gigascale integration in recent semiconductor technology mandates design reuse in order to meet the design specifications in time. Electronic description of VLSI design being an intellectual property (IP), may be infringed upon during design reuse. This calls for incorporating techniques for intellectual property protection in the VLSI design flow. The IP of VLSI design, which culminates in fabrication of the integrated circuit, differs from other sources of IPs because in addition to its physical and structural description, it has also a behavioral specification which should remain unaltered after application of IP protection techniques. Security in activation of chips, especially in embedded systems, is an equally grave issue and has led to the paradigm of design-for-security. This tutorial aims at presenting the major concerns related to IP security that are significant to both the circuit designers and developers of CAD tools. The nature of threats are broadly categorized as (i) misappropriation by hacking during electronic commerce and intentional reselling mostly at design level, and (ii) unauthorized design retrieval. Various attack models and the mechanisms for effective counter measures such as encryption, obfuscation, watermarking and fingerprinting, and certain analytic methods derived from the behavioral aspect, specific to chip designs, will be discussed. First, the scenario of digital rights management, attack models and security goals will be described. Next, the existing approaches for protection of soft IPs such as HDL codes, firm IPs especially at the value-added layout level, and hard IPs including DFM-enhanced layout will be presented. This will include a number of published research results by the presenters. Finally, the recent advances in tackling security issues for design of smart cards and crypto processors will be surveyed.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132929269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SystemC has become an accepted standard for design of HW/SW Systems at system level. How-ever, nowadays systems include more and more analog/RF components such as transceivers, sensor interfaces, or PLL. To enable design of such mixed-signal systems, OSCI has standardized AMS extensions for SystemC in 2010. In addition to the capabilities of SystemC for modelling multi-processor HW/SW systems, the AMS extensions enable modelling the behaviour of analog/RF parts, physical environment and digital signal processing methods. The tutorial gives an introduction into SystemC AMS extensions. The introduction includes the language itself, some simple examples, use cases and (top-down) methodology for refinement of AMS systems, starting from an executable specification.
{"title":"Tutorial T1: Design of Mixed-Signal Systems using SystemC AMS Extensions","authors":"Sumit Adhikari, Markus Damm, C. Grimm, F. Pêcheux","doi":"10.1109/VLSID.2012.28","DOIUrl":"https://doi.org/10.1109/VLSID.2012.28","url":null,"abstract":"SystemC has become an accepted standard for design of HW/SW Systems at system level. How-ever, nowadays systems include more and more analog/RF components such as transceivers, sensor interfaces, or PLL. To enable design of such mixed-signal systems, OSCI has standardized AMS extensions for SystemC in 2010. In addition to the capabilities of SystemC for modelling multi-processor HW/SW systems, the AMS extensions enable modelling the behaviour of analog/RF parts, physical environment and digital signal processing methods. The tutorial gives an introduction into SystemC AMS extensions. The introduction includes the language itself, some simple examples, use cases and (top-down) methodology for refinement of AMS systems, starting from an executable specification.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133767811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Reversible circuits are of vital importance in many applications involving low power design. One of the principle areas where reversible circuits play great role is quantum computing. One of the foremost requirements of quantum computation is that it requires all the circuits that are used should be reversible in nature. Reversible circuit is one which maps an individual input vector to a singular output vector. Because of its application in many areas including quantum computing, many synthesis approaches have been developed. In this paper we focus on a synthesis approach which is based on permutation theory and heuristic search. An artificial intelligence based search technique A* is used to find near optimal solutions. Experimental results demonstrate that the proposed approach provides solutions within a very reasonable span of time.
{"title":"Synthesis of Reversible Circuits Using Heuristic Search Method","authors":"K. Datta, G. Rathi, I. Sengupta, H. Rahaman","doi":"10.1109/VLSID.2012.92","DOIUrl":"https://doi.org/10.1109/VLSID.2012.92","url":null,"abstract":"Reversible circuits are of vital importance in many applications involving low power design. One of the principle areas where reversible circuits play great role is quantum computing. One of the foremost requirements of quantum computation is that it requires all the circuits that are used should be reversible in nature. Reversible circuit is one which maps an individual input vector to a singular output vector. Because of its application in many areas including quantum computing, many synthesis approaches have been developed. In this paper we focus on a synthesis approach which is based on permutation theory and heuristic search. An artificial intelligence based search technique A* is used to find near optimal solutions. Experimental results demonstrate that the proposed approach provides solutions within a very reasonable span of time.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132723158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Stringent performance requirements magnify the performance degradation impact of Design-for-Testability (DfT) techniques. As more aggressive performance optimizations are being employed, resulting in high-performance designs with reduced logic depth, the impact of scan multiplexers is becoming even more magnified. In this work, we propose a scan cell transformation technique that transfers the scan multiplexer delay from the input of the flip-flop to its output, enabling the removal of the scan multiplexer delay off the critical paths. By inserting a few shadow flip-flops properly, the proposed transformation technique retains test development (test data, quality, etc.) and application (test time, power dissipation, etc.) intact, fully complying with the conventional design and test flow. Experimental results justify the efficacy of the proposed techniques in eliminating the performance penalty of scan quickly and cost-effectively, and thus in enhancing functional speed of integrated circuits.
{"title":"Eliminating Performance Penalty of Scan","authors":"O. Sinanoglu","doi":"10.1109/VLSID.2012.95","DOIUrl":"https://doi.org/10.1109/VLSID.2012.95","url":null,"abstract":"Stringent performance requirements magnify the performance degradation impact of Design-for-Testability (DfT) techniques. As more aggressive performance optimizations are being employed, resulting in high-performance designs with reduced logic depth, the impact of scan multiplexers is becoming even more magnified. In this work, we propose a scan cell transformation technique that transfers the scan multiplexer delay from the input of the flip-flop to its output, enabling the removal of the scan multiplexer delay off the critical paths. By inserting a few shadow flip-flops properly, the proposed transformation technique retains test development (test data, quality, etc.) and application (test time, power dissipation, etc.) intact, fully complying with the conventional design and test flow. Experimental results justify the efficacy of the proposed techniques in eliminating the performance penalty of scan quickly and cost-effectively, and thus in enhancing functional speed of integrated circuits.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"32 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121004556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes 8-bit 300MS/s 7-stages parallel pipeline ADC with 1.5-bit per stage and power efficient architecture is designed by sharing an amplifier between two pipeline stages, introducing the proper clock timing between the two parallel stages. This architecture is realized by eight no. of amplifier and the sample hold architecture is designed by using double sampling sample hold (DSSH) technique. A wide swing and wide bandwidth regulated folded cascode and power efficient dynamic comparator has been developed to further reduce the power consumption of the pipeline ADC. The ADC is implemented in 0.18 μm CMOS process technology, achieves 57.40 dB spurious free dynamic range (SFDR), 49.078 dB signal to noise distortion ratio (SNDR), 7.86 effective no of bit (ENOB) and consumes 55 mW from 1.8 V supply. The resulting figure of merit (FOM) is 0.789 PJ/conversion step.
{"title":"A 55-mW 300MS/s 8-bit CMOS Parallel Pipeline ADC","authors":"M. K. Hati, T. K. Bhattacharyya","doi":"10.1109/VLSID.2012.44","DOIUrl":"https://doi.org/10.1109/VLSID.2012.44","url":null,"abstract":"This paper describes 8-bit 300MS/s 7-stages parallel pipeline ADC with 1.5-bit per stage and power efficient architecture is designed by sharing an amplifier between two pipeline stages, introducing the proper clock timing between the two parallel stages. This architecture is realized by eight no. of amplifier and the sample hold architecture is designed by using double sampling sample hold (DSSH) technique. A wide swing and wide bandwidth regulated folded cascode and power efficient dynamic comparator has been developed to further reduce the power consumption of the pipeline ADC. The ADC is implemented in 0.18 μm CMOS process technology, achieves 57.40 dB spurious free dynamic range (SFDR), 49.078 dB signal to noise distortion ratio (SNDR), 7.86 effective no of bit (ENOB) and consumes 55 mW from 1.8 V supply. The resulting figure of merit (FOM) is 0.789 PJ/conversion step.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121979846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With increasing contribution of leakage in total active power, run-time leakage control techniques are becoming extremely important. Supply gating provides an effective, low-overhead and technology scalable approach for active leakage reduction through the well-known "stacking effect". However, conventional supply gating approaches are typically coarse-grained in both space and time - i.e. are applied to large data path or memory blocks when an entire logic/memory block is idle for sufficiently long period. They suffer from limited applicability at run time. On the other hand, fine-grained supply gating is constrained primarily by the large wake-up delay and wake-up power overhead. In this paper, we propose a novel fine-grained width-aware dynamic supply gating (WADSG) approach to reduce both active leakage and redundant switching power in data path and embedded memory (e.g. L1/L2 cache). The approach exploits the abundance of narrow-width (NW) operands in general-purpose and embedded applications to "supply-gate" unused parts of integer execution units and memory blocks while they are in use. We introduce a novel levelized gating strategy to virtually eliminate the wake-up delay overhead. We employ the proposed WADSG approach to a super scalar processor. To reduce the wake-up power we use a width aware instruction issue policy. In case of L1 and L2 cache, we store the width information per "ways" of associative cache and supply-gate the most significant bits of the NW ways. We also propose a width-aware block allocation and replacement policy to maximize the number of NW ways. Simulation results for 45nm technology with Spec2k benchmarks show major savings (34.5%) in total processor power (considering both switching and active leakage power) with no performance impact. As a by-product, the proposed scheme also improves the thermal profile of both data path and memory.
{"title":"Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory","authors":"L. Wang, Somnath Paul, S. Bhunia","doi":"10.1109/VLSID.2012.94","DOIUrl":"https://doi.org/10.1109/VLSID.2012.94","url":null,"abstract":"With increasing contribution of leakage in total active power, run-time leakage control techniques are becoming extremely important. Supply gating provides an effective, low-overhead and technology scalable approach for active leakage reduction through the well-known \"stacking effect\". However, conventional supply gating approaches are typically coarse-grained in both space and time - i.e. are applied to large data path or memory blocks when an entire logic/memory block is idle for sufficiently long period. They suffer from limited applicability at run time. On the other hand, fine-grained supply gating is constrained primarily by the large wake-up delay and wake-up power overhead. In this paper, we propose a novel fine-grained width-aware dynamic supply gating (WADSG) approach to reduce both active leakage and redundant switching power in data path and embedded memory (e.g. L1/L2 cache). The approach exploits the abundance of narrow-width (NW) operands in general-purpose and embedded applications to \"supply-gate\" unused parts of integer execution units and memory blocks while they are in use. We introduce a novel levelized gating strategy to virtually eliminate the wake-up delay overhead. We employ the proposed WADSG approach to a super scalar processor. To reduce the wake-up power we use a width aware instruction issue policy. In case of L1 and L2 cache, we store the width information per \"ways\" of associative cache and supply-gate the most significant bits of the NW ways. We also propose a width-aware block allocation and replacement policy to maximize the number of NW ways. Simulation results for 45nm technology with Spec2k benchmarks show major savings (34.5%) in total processor power (considering both switching and active leakage power) with no performance impact. As a by-product, the proposed scheme also improves the thermal profile of both data path and memory.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126460497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cyber-Physical Systems (CPSs) are poised to play a pivotal role in engineering new solutions to a variety of societal-scale problems, such as energy conservation, climate change, healthcare, transportation, etc. Their importance is reflected in the overall theme for VLSI Design 2012, which is "Embedded Solutions for Emerging Markets Infrastructure, Energy, and Automotive." Networked embedded systems, such as wireless sensor networks, form a crucial building block for realizing large scale CPSs and have, therefore, received considerable research attention over the past few years. While this has resulted in numerous technological advances (e.g., a plethora of tiny, cheap, and low-power sensor platforms is now available), the problem of programming a distributed wireless sensor network still remains a major challenge and a potential show stopper to widespread adoption.
{"title":"Embedded Tutorial ET4: Advanced Techniques for Programming Networked Embedded Systems","authors":"V. Raghunathan","doi":"10.1109/VLSID.2012.39","DOIUrl":"https://doi.org/10.1109/VLSID.2012.39","url":null,"abstract":"Cyber-Physical Systems (CPSs) are poised to play a pivotal role in engineering new solutions to a variety of societal-scale problems, such as energy conservation, climate change, healthcare, transportation, etc. Their importance is reflected in the overall theme for VLSI Design 2012, which is \"Embedded Solutions for Emerging Markets Infrastructure, Energy, and Automotive.\" Networked embedded systems, such as wireless sensor networks, form a crucial building block for realizing large scale CPSs and have, therefore, received considerable research attention over the past few years. While this has resulted in numerous technological advances (e.g., a plethora of tiny, cheap, and low-power sensor platforms is now available), the problem of programming a distributed wireless sensor network still remains a major challenge and a potential show stopper to widespread adoption.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126810547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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