The need to integrate multiple wireless communication protocols into a single low-cost, low power hardware platform is prompted by the increasing number of emerging communication protocols and applications. This paper presents an efficient methodology for integrating multiple wireless protocols in an ASIC which minimizes resource occupation. A hierarchical data path merging algorithm is developed to find common shareable components in two different communication circuits. The data path merging approach will build a combined generic circuit with inserted multiplexers (MUXes) which can provide the same functionality of each individual circuit. The proposed method is orders of magnitude faster (well over 1000 times faster for realistic circuits) than the existing data path merging algorithm (with an overhead of 3% additional area) and can switch communication protocols on the fly (i.e. it can switch between protocols in a single clock cycle), which is a desirable feature for seemingly simultaneous multi-mode wireless communication. Wireless LAN (WLAN) 802.11a, WLAN802.11b and Ultra Wide Band (UWB) transmission circuits are merged to prove the efficacy of our proposal.
{"title":"A Rapid Methodology for Multi-mode Communication Circuit Generation","authors":"L. Tang, Jorgen Peddersen, S. Parameswaran","doi":"10.1109/VLSID.2012.71","DOIUrl":"https://doi.org/10.1109/VLSID.2012.71","url":null,"abstract":"The need to integrate multiple wireless communication protocols into a single low-cost, low power hardware platform is prompted by the increasing number of emerging communication protocols and applications. This paper presents an efficient methodology for integrating multiple wireless protocols in an ASIC which minimizes resource occupation. A hierarchical data path merging algorithm is developed to find common shareable components in two different communication circuits. The data path merging approach will build a combined generic circuit with inserted multiplexers (MUXes) which can provide the same functionality of each individual circuit. The proposed method is orders of magnitude faster (well over 1000 times faster for realistic circuits) than the existing data path merging algorithm (with an overhead of 3% additional area) and can switch communication protocols on the fly (i.e. it can switch between protocols in a single clock cycle), which is a desirable feature for seemingly simultaneous multi-mode wireless communication. Wireless LAN (WLAN) 802.11a, WLAN802.11b and Ultra Wide Band (UWB) transmission circuits are merged to prove the efficacy of our proposal.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122058167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given: We discuss the low-dropout (LDO) voltage regulator pole-zero analysis in this tutorial. A priori knowledge of poles and zeros assist in choosing the right topology and appropriate frequency compensation techniques before implementing the transistor level design, as the location of poles move with output load current. The objective of this tutorial is to provide a step-by-step procedure for analyzing poles and zeros in LDO regulators. To this end, two recent state-of-the-art LDO regulators from the literature are analyzed, explaining several intricacies involved. We explain step-by-step procedure in developing the small-signal model, breaking the voltage/current loop and techniques for quickly arriving at simple and approximate pole-zero equations. During the process, several frequency compensation techniques are elucidated. The derived analytic expressions for poles and zeros help in developing intuition of circuit behavior.
{"title":"Embedded Tutorial ET1: Pole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial Overview","authors":"A. Garimella, Punith R. Surkanti, P. Furth","doi":"10.1109/VLSID.2012.59","DOIUrl":"https://doi.org/10.1109/VLSID.2012.59","url":null,"abstract":"Summary form only given: We discuss the low-dropout (LDO) voltage regulator pole-zero analysis in this tutorial. A priori knowledge of poles and zeros assist in choosing the right topology and appropriate frequency compensation techniques before implementing the transistor level design, as the location of poles move with output load current. The objective of this tutorial is to provide a step-by-step procedure for analyzing poles and zeros in LDO regulators. To this end, two recent state-of-the-art LDO regulators from the literature are analyzed, explaining several intricacies involved. We explain step-by-step procedure in developing the small-signal model, breaking the voltage/current loop and techniques for quickly arriving at simple and approximate pole-zero equations. During the process, several frequency compensation techniques are elucidated. The derived analytic expressions for poles and zeros help in developing intuition of circuit behavior.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121543700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Vooka, Khushboo Agarwal, Abhijeet Shrivastava, P. Murthy, R. Venkatraman
With the increasing clock frequencies to multiple Gigahertz and increasing need to achieve it at lower voltages for keeping operating power lower, frequency of operation is not only limited by the data path delay scaling but also by the behavior of clock signals. Failures induced by violation of minimum clock pulse width required, at higher frequencies is more commonly seen due to increased operating frequencies and usage of voltage scaling techniques for achieving higher frequencies [1]. Silicon failures caused by minimum pulse width violation due to clock shrinkage can be due to variety of reasons right from duty cycle distortion at clock generator (PLL) to clock pulse distortion due to slew degradation along the clock path. In this paper authors discuss different techniques that enable us to minimize pulse width failures as the mechanism that limit the frequency of operation of the device. In this paper we propose a simple and novel technique to detect and diagnose pulse width failures. Silicon results from 40nm multi-million gate industrial SoC is presented to indicate the effects of pulse width degradation on performance of the device and to evaluate the effectiveness of the proposed pattern generation technique.
{"title":"A Silicon Testing Strategy for Pulse-Width Failures","authors":"S. Vooka, Khushboo Agarwal, Abhijeet Shrivastava, P. Murthy, R. Venkatraman","doi":"10.1109/VLSID.2012.96","DOIUrl":"https://doi.org/10.1109/VLSID.2012.96","url":null,"abstract":"With the increasing clock frequencies to multiple Gigahertz and increasing need to achieve it at lower voltages for keeping operating power lower, frequency of operation is not only limited by the data path delay scaling but also by the behavior of clock signals. Failures induced by violation of minimum clock pulse width required, at higher frequencies is more commonly seen due to increased operating frequencies and usage of voltage scaling techniques for achieving higher frequencies [1]. Silicon failures caused by minimum pulse width violation due to clock shrinkage can be due to variety of reasons right from duty cycle distortion at clock generator (PLL) to clock pulse distortion due to slew degradation along the clock path. In this paper authors discuss different techniques that enable us to minimize pulse width failures as the mechanism that limit the frequency of operation of the device. In this paper we propose a simple and novel technique to detect and diagnose pulse width failures. Silicon results from 40nm multi-million gate industrial SoC is presented to indicate the effects of pulse width degradation on performance of the device and to evaluate the effectiveness of the proposed pattern generation technique.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117343174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Unmesh D. Bordoloi, B. Suri, S. Nunna, S. Chakraborty, P. Eles, Zebo Peng
Many reconfigurable processors allow their instruction sets to be tailored according to the performance requirements of target applications. They have gained immense popularity in recent years because of this flexibility of adding custom instructions. However, most design automation algorithms for instruction set customization (like enumerating and selecting the optimal set of custom instructions) are computationally intractable. As such, existing tools to customize instruction sets of extensible processors rely on approximation methods or heuristics. In contrast to such traditional approaches, we propose to use GPUs (Graphics Processing Units) to efficiently solve computationally expensive algorithms in the design automation tools for extensible processors. To demonstrate our idea, we choose a custom instruction selection problem and accelerate it using CUDA (CUDA is a GPU computing engine). Our CUDA implementation is devised to maximize the achievable speedups by various optimizations like exploiting on-chip shared memory and register usage. Experiments conducted on well known benchmarks show significant speedups over sequential CPU implementations as well as over multi-core implementations.
{"title":"Customizing Instruction Set Extensible Reconfigurable Processors Using GPUs","authors":"Unmesh D. Bordoloi, B. Suri, S. Nunna, S. Chakraborty, P. Eles, Zebo Peng","doi":"10.1109/VLSID.2012.107","DOIUrl":"https://doi.org/10.1109/VLSID.2012.107","url":null,"abstract":"Many reconfigurable processors allow their instruction sets to be tailored according to the performance requirements of target applications. They have gained immense popularity in recent years because of this flexibility of adding custom instructions. However, most design automation algorithms for instruction set customization (like enumerating and selecting the optimal set of custom instructions) are computationally intractable. As such, existing tools to customize instruction sets of extensible processors rely on approximation methods or heuristics. In contrast to such traditional approaches, we propose to use GPUs (Graphics Processing Units) to efficiently solve computationally expensive algorithms in the design automation tools for extensible processors. To demonstrate our idea, we choose a custom instruction selection problem and accelerate it using CUDA (CUDA is a GPU computing engine). Our CUDA implementation is devised to maximize the achievable speedups by various optimizations like exploiting on-chip shared memory and register usage. Experiments conducted on well known benchmarks show significant speedups over sequential CPU implementations as well as over multi-core implementations.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115409529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In high speed link transmitters, one major contributor of jitter is the data-dependant switching of the transmitters. Such switching leads to oscillations in the supply R-L-C network. This paper presents an area-efficient way to reduce this supply noise by shifting the switching beyond the resonance frequency of the supply network, irrespective of the data-pattern. This scheme is implemented in HDMI transmitter in 65nm technology.
{"title":"Self-Induced Supply Noise Reduction Technique in GBPS Rate Transmitters","authors":"Nitin Gupta, Tapas Nandy, P. Bala","doi":"10.1109/VLSID.2012.52","DOIUrl":"https://doi.org/10.1109/VLSID.2012.52","url":null,"abstract":"In high speed link transmitters, one major contributor of jitter is the data-dependant switching of the transmitters. Such switching leads to oscillations in the supply R-L-C network. This paper presents an area-efficient way to reduce this supply noise by shifting the switching beyond the resonance frequency of the supply network, irrespective of the data-pattern. This scheme is implemented in HDMI transmitter in 65nm technology.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130347488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. W. Wells, Jayaram Natarajan, A. Chatterjee, I. Barlas
In this paper, a content aware, low power video encoder design is presented in which the algorithms and hardware are co-optimized to adapt concurrently to video content in real-time. Natural image statistical models are used to form spatiotemporal predictions about the content of future frames. A key innovation in this work is that that the predictions are used as parameters in a feedback control loop to intelligently down sample (change the resolution of the frame image across different parts of the image) the video encoder input immediately at the camera, thus reducing the amount of work required by the encoder per frame. A multiresolution frame representation is used to produce regular data structures which allow for efficient hardware design. The hardware is co-optimized with the algorithm to reduce power based on the reduced input size resulting from the algorithm. The design also allows for selectable, graceful degradation of video quality while reducing power consumption.
{"title":"Real-Time, Content Aware Camera -- Algorithm -- Hardware Co-Adaptation for Minimal Power Video Encoding","authors":"J. W. Wells, Jayaram Natarajan, A. Chatterjee, I. Barlas","doi":"10.1109/VLSID.2012.78","DOIUrl":"https://doi.org/10.1109/VLSID.2012.78","url":null,"abstract":"In this paper, a content aware, low power video encoder design is presented in which the algorithms and hardware are co-optimized to adapt concurrently to video content in real-time. Natural image statistical models are used to form spatiotemporal predictions about the content of future frames. A key innovation in this work is that that the predictions are used as parameters in a feedback control loop to intelligently down sample (change the resolution of the frame image across different parts of the image) the video encoder input immediately at the camera, thus reducing the amount of work required by the encoder per frame. A multiresolution frame representation is used to produce regular data structures which allow for efficient hardware design. The hardware is co-optimized with the algorithm to reduce power based on the reduced input size resulting from the algorithm. The design also allows for selectable, graceful degradation of video quality while reducing power consumption.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115192747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Jain, Maheedhar Jalasutram, S. Vooka, Prasun Nair, Neeraj Pradhan
In sub-threshold technology nodes, device failure due to timing related defects (setup & hold timing) is on rise due to extreme process variability and increasing use of voltage scaling techniques for achieving required performance. High coverage using stuck-at fault patterns, which can effectively screen static defects is no longer sufficient to control DPPM (Defective parts per million). High test coverage of timing defects that is induced by process variation is required for controlling DPPM. Lot of work has been done to find the ways to increase the delay test coverage of industrial circuits including the various methods to cover inter-domain clock faults but very little or no work is done on the ways to effectively cover the asynchronous reset paths to the memory registers for timing defects. In this paper we propose a novel methodology that allows us to effectively detect the failures induced by timing defects on asynchronous reset path of the registers. This problem is further complicated by the fact that commercially available ATPG tools are not capable of generating test patterns due to modeling limitations. Results from 45nm industrial multi-million gates design is presented to illustrate the effectiveness of the proposed methodology.
{"title":"At-speed Testing of Asynchronous Reset De-assertion Faults","authors":"A. Jain, Maheedhar Jalasutram, S. Vooka, Prasun Nair, Neeraj Pradhan","doi":"10.1109/VLSID.2012.97","DOIUrl":"https://doi.org/10.1109/VLSID.2012.97","url":null,"abstract":"In sub-threshold technology nodes, device failure due to timing related defects (setup & hold timing) is on rise due to extreme process variability and increasing use of voltage scaling techniques for achieving required performance. High coverage using stuck-at fault patterns, which can effectively screen static defects is no longer sufficient to control DPPM (Defective parts per million). High test coverage of timing defects that is induced by process variation is required for controlling DPPM. Lot of work has been done to find the ways to increase the delay test coverage of industrial circuits including the various methods to cover inter-domain clock faults but very little or no work is done on the ways to effectively cover the asynchronous reset paths to the memory registers for timing defects. In this paper we propose a novel methodology that allows us to effectively detect the failures induced by timing defects on asynchronous reset path of the registers. This problem is further complicated by the fact that commercially available ATPG tools are not capable of generating test patterns due to modeling limitations. Results from 45nm industrial multi-million gates design is presented to illustrate the effectiveness of the proposed methodology.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124806762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mahima Arrawatia, Varish Diddi, H. Kochar, M. Baghini, G. Kumar
This paper presents an energy harvesting system which extracts energy from radio frequency radiation for battery charging applications. It comprises of a new differential center tapped Micro strip antenna, off-chip matching circuit, on-chip novel CMOS rectifier and control circuitry in 180nm CMOS technology. For on-chip modules, thick oxide devices have been used so as to meet the charging requirements of the target batteries. The designed battery charging module charges either of 250 Ah and 10 Ah batteries according to the selected battery and available input power. The 250 Ah battery is charged at input power of 2dBm and 10 Ah battery is charged at input power of -6.5dBm. The fabricated antenna has a gain of 8.3dB and a VSWR less than 2 in the bandwidth from 844 to 970MHz. An efficient Periodic Steady State(PSS)-based power matching technique is also presented which improves the system efficiency. For 0dBm input power at 950 MHz to the antenna the proposed technique leads to 55.2% efficiency of RF to DC converter system. In addition to the integrated design a discrete rectifier using high frequency Schottky diodes and differential micro strip antenna at the input are fabricated. The discrete system uses the proposed matching technique and exhibits efficiency of 40% for-11dBm received power by the antenna.
{"title":"An Integrated CMOS RF Energy Harvester with Differential Microstrip Antenna and On-Chip Charger","authors":"Mahima Arrawatia, Varish Diddi, H. Kochar, M. Baghini, G. Kumar","doi":"10.1109/VLSID.2012.72","DOIUrl":"https://doi.org/10.1109/VLSID.2012.72","url":null,"abstract":"This paper presents an energy harvesting system which extracts energy from radio frequency radiation for battery charging applications. It comprises of a new differential center tapped Micro strip antenna, off-chip matching circuit, on-chip novel CMOS rectifier and control circuitry in 180nm CMOS technology. For on-chip modules, thick oxide devices have been used so as to meet the charging requirements of the target batteries. The designed battery charging module charges either of 250 Ah and 10 Ah batteries according to the selected battery and available input power. The 250 Ah battery is charged at input power of 2dBm and 10 Ah battery is charged at input power of -6.5dBm. The fabricated antenna has a gain of 8.3dB and a VSWR less than 2 in the bandwidth from 844 to 970MHz. An efficient Periodic Steady State(PSS)-based power matching technique is also presented which improves the system efficiency. For 0dBm input power at 950 MHz to the antenna the proposed technique leads to 55.2% efficiency of RF to DC converter system. In addition to the integrated design a discrete rectifier using high frequency Schottky diodes and differential micro strip antenna at the input are fabricated. The discrete system uses the proposed matching technique and exhibits efficiency of 40% for-11dBm received power by the antenna.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125092938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Given a Boolean function, the Unate-Covering Problem (UCP) is NP-hard. This problem can be modeled as a set cover problem where minterms are the elements and implicants form the sets. Traditional solutions in logic synthesis use set cover algorithms that are oblivious to the special semantic of the elements and sets. We propose three new heuristics for the set-cover problem which are aware of the relationship between implicants and minterms. We show that the proposed heuristics are effective for breaking ties when a cyclic core is obtained. We evaluate the heuristics on a set of hard instances from BHOSLIB benchmark suite. We also replace ESPRESSO's set cover algorithm using these heuristics and compare the logic synthesis results. We further map the minimized Boolean equations using ABC's technology mapping tool using 2-input NAND gates and 4-input Lookup Tables (LUTs).
给定一个布尔函数，unate - coverage Problem (UCP)是np困难的。这个问题可以建模为集合覆盖问题，其中最小项是集合的元素和隐含项。传统的逻辑综合解决方案使用集合覆盖算法，忽略了元素和集合的特殊语义。我们提出了三种新的启发式方法来解决集合覆盖问题，它们都意识到隐含项和最小项之间的关系。我们证明，当得到一个循环核时，所提出的启发式方法对于打破联系是有效的。我们在BHOSLIB基准测试套件中的一组硬实例上评估启发式。我们还使用这些启发式算法替换了ESPRESSO的集合覆盖算法，并比较了逻辑综合结果。我们使用ABC的技术映射工具使用2输入NAND门和4输入查找表(LUTs)进一步映射最小化布尔方程。
{"title":"Set-Cover Heuristics for Two-Level Logic Minimization","authors":"Ankit Kagliwal, S. Balachandran","doi":"10.1109/VLSID.2012.70","DOIUrl":"https://doi.org/10.1109/VLSID.2012.70","url":null,"abstract":"Given a Boolean function, the Unate-Covering Problem (UCP) is NP-hard. This problem can be modeled as a set cover problem where minterms are the elements and implicants form the sets. Traditional solutions in logic synthesis use set cover algorithms that are oblivious to the special semantic of the elements and sets. We propose three new heuristics for the set-cover problem which are aware of the relationship between implicants and minterms. We show that the proposed heuristics are effective for breaking ties when a cyclic core is obtained. We evaluate the heuristics on a set of hard instances from BHOSLIB benchmark suite. We also replace ESPRESSO's set cover algorithm using these heuristics and compare the logic synthesis results. We further map the minimized Boolean equations using ABC's technology mapping tool using 2-input NAND gates and 4-input Lookup Tables (LUTs).","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116961459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A fast equation free iterative approach for sizing of analog circuit is proposed. Equation based sizing approach has been popular as it removes time consuming simulation effort. If equations are cast in posynomial inequality format, a special optimization technique called geometric programming(GP) can be deployed. The advantage of formulating the problem in GP form is that, it ensures global optimality and can return the final design point instantly even in the presence of hundreds of equation and thousands of variable. But main limitation comes in deriving performance equations in posynomial inequality format. In this context, we develop one novel methodology for fast sizing of analog circuit. This method does not require any such performance expressions. It is based on the meaningful presentation of only device constraints. Infeasibility is handled iteratively making suitable changes on those constraints. Due to the simplicity of formulation, fully automated flow is achieved.
{"title":"A Fast Equation Free Iterative Approach to Analog Circuit Sizing","authors":"S. Maji, P. Mandal","doi":"10.1109/VLSID.2012.99","DOIUrl":"https://doi.org/10.1109/VLSID.2012.99","url":null,"abstract":"A fast equation free iterative approach for sizing of analog circuit is proposed. Equation based sizing approach has been popular as it removes time consuming simulation effort. If equations are cast in posynomial inequality format, a special optimization technique called geometric programming(GP) can be deployed. The advantage of formulating the problem in GP form is that, it ensures global optimality and can return the final design point instantly even in the presence of hundreds of equation and thousands of variable. But main limitation comes in deriving performance equations in posynomial inequality format. In this context, we develop one novel methodology for fast sizing of analog circuit. This method does not require any such performance expressions. It is based on the meaningful presentation of only device constraints. Infeasibility is handled iteratively making suitable changes on those constraints. Due to the simplicity of formulation, fully automated flow is achieved.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116541400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：