As device geometries shrink to nanometers, increasing leakage current coupled with particle induced soft errors is exasperating the circuit reliability issues. In this paper, we first establish that independent solutions to these two problems can not lead to a good final solution. A more thoughtful and integrated design methodology is required to reconcile these two challenging issues. Next, we investigate the dependency of soft error rate on the body bias based leakage reduction method and introduce a novel body bias-dependent soft error model. We propose an optimization based and a heuristic driven approach to reduce leakage while satisfying the soft error rate limit. Our methods provide appropriate body bias configurations that lead to near-optimal total mean time to failure improvement of a circuit.
{"title":"Impact of Body Bias Based Leakage Power Reduction on Soft Error Rate","authors":"Warin Sootkaneung, K. Saluja","doi":"10.1109/VLSID.2012.49","DOIUrl":"https://doi.org/10.1109/VLSID.2012.49","url":null,"abstract":"As device geometries shrink to nanometers, increasing leakage current coupled with particle induced soft errors is exasperating the circuit reliability issues. In this paper, we first establish that independent solutions to these two problems can not lead to a good final solution. A more thoughtful and integrated design methodology is required to reconcile these two challenging issues. Next, we investigate the dependency of soft error rate on the body bias based leakage reduction method and introduce a novel body bias-dependent soft error model. We propose an optimization based and a heuristic driven approach to reduce leakage while satisfying the soft error rate limit. Our methods provide appropriate body bias configurations that lead to near-optimal total mean time to failure improvement of a circuit.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122973495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Effect of shadowing and/or backscattering of halo implant species from halo implant mask layer on leakage current of NMOS driver transistor of a 65nm SRAM cell is studied. The halo implant mask layer thickness has been varied from 100nm to 3000nm in steps, in response to this variation, leakage behavior of this NMOS transistor is observed. The leakage current of this transistor is shown to be a strong function of halo implant mask layer thickness with implant window width W=0.27mm. The poly gate is located approximately in the middle of this implant window. The leakage current is seen to increase monotonically by more than an order of magnitude with the increase in thickness till 500nm. When this thickness is increased beyond 500nm, the leakage current variation fits approximately into a damped oscillatory curve whose period is seen to be proportional to the width W of the halo implant window. The leakage current observed is 22nA for this NMOS device (with gate width Wn=120nm) at 500nm of halo implant mask layer thickness. Further when the halo implant window width W is increased beyond 0.27mm with the halo mask layer thickness fixed at 500nm, the leakage attained a minimum value of 0.54nA. All the leakage currents that are observed are in saturation region at cell Vdd=1.2V.
{"title":"Implications of Halo Implant Shadowing and Backscattering from Mask Layer Edges on Device Leakage Current in 65nm SRAM","authors":"H. C. Srinivasaiah","doi":"10.1109/VLSID.2012.106","DOIUrl":"https://doi.org/10.1109/VLSID.2012.106","url":null,"abstract":"Effect of shadowing and/or backscattering of halo implant species from halo implant mask layer on leakage current of NMOS driver transistor of a 65nm SRAM cell is studied. The halo implant mask layer thickness has been varied from 100nm to 3000nm in steps, in response to this variation, leakage behavior of this NMOS transistor is observed. The leakage current of this transistor is shown to be a strong function of halo implant mask layer thickness with implant window width W=0.27mm. The poly gate is located approximately in the middle of this implant window. The leakage current is seen to increase monotonically by more than an order of magnitude with the increase in thickness till 500nm. When this thickness is increased beyond 500nm, the leakage current variation fits approximately into a damped oscillatory curve whose period is seen to be proportional to the width W of the halo implant window. The leakage current observed is 22nA for this NMOS device (with gate width Wn=120nm) at 500nm of halo implant mask layer thickness. Further when the halo implant window width W is increased beyond 0.27mm with the halo mask layer thickness fixed at 500nm, the leakage attained a minimum value of 0.54nA. All the leakage currents that are observed are in saturation region at cell Vdd=1.2V.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123823832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Vooka, Khushboo Agarwal, Abhijeet Shrivastava, P. Murthy, R. Venkatraman
With the increasing clock frequencies to multiple Gigahertz and increasing need to achieve it at lower voltages for keeping operating power lower, frequency of operation is not only limited by the data path delay scaling but also by the behavior of clock signals. Failures induced by violation of minimum clock pulse width required, at higher frequencies is more commonly seen due to increased operating frequencies and usage of voltage scaling techniques for achieving higher frequencies [1]. Silicon failures caused by minimum pulse width violation due to clock shrinkage can be due to variety of reasons right from duty cycle distortion at clock generator (PLL) to clock pulse distortion due to slew degradation along the clock path. In this paper authors discuss different techniques that enable us to minimize pulse width failures as the mechanism that limit the frequency of operation of the device. In this paper we propose a simple and novel technique to detect and diagnose pulse width failures. Silicon results from 40nm multi-million gate industrial SoC is presented to indicate the effects of pulse width degradation on performance of the device and to evaluate the effectiveness of the proposed pattern generation technique.
{"title":"A Silicon Testing Strategy for Pulse-Width Failures","authors":"S. Vooka, Khushboo Agarwal, Abhijeet Shrivastava, P. Murthy, R. Venkatraman","doi":"10.1109/VLSID.2012.96","DOIUrl":"https://doi.org/10.1109/VLSID.2012.96","url":null,"abstract":"With the increasing clock frequencies to multiple Gigahertz and increasing need to achieve it at lower voltages for keeping operating power lower, frequency of operation is not only limited by the data path delay scaling but also by the behavior of clock signals. Failures induced by violation of minimum clock pulse width required, at higher frequencies is more commonly seen due to increased operating frequencies and usage of voltage scaling techniques for achieving higher frequencies [1]. Silicon failures caused by minimum pulse width violation due to clock shrinkage can be due to variety of reasons right from duty cycle distortion at clock generator (PLL) to clock pulse distortion due to slew degradation along the clock path. In this paper authors discuss different techniques that enable us to minimize pulse width failures as the mechanism that limit the frequency of operation of the device. In this paper we propose a simple and novel technique to detect and diagnose pulse width failures. Silicon results from 40nm multi-million gate industrial SoC is presented to indicate the effects of pulse width degradation on performance of the device and to evaluate the effectiveness of the proposed pattern generation technique.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117343174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given: We discuss the low-dropout (LDO) voltage regulator pole-zero analysis in this tutorial. A priori knowledge of poles and zeros assist in choosing the right topology and appropriate frequency compensation techniques before implementing the transistor level design, as the location of poles move with output load current. The objective of this tutorial is to provide a step-by-step procedure for analyzing poles and zeros in LDO regulators. To this end, two recent state-of-the-art LDO regulators from the literature are analyzed, explaining several intricacies involved. We explain step-by-step procedure in developing the small-signal model, breaking the voltage/current loop and techniques for quickly arriving at simple and approximate pole-zero equations. During the process, several frequency compensation techniques are elucidated. The derived analytic expressions for poles and zeros help in developing intuition of circuit behavior.
{"title":"Embedded Tutorial ET1: Pole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial Overview","authors":"A. Garimella, Punith R. Surkanti, P. Furth","doi":"10.1109/VLSID.2012.59","DOIUrl":"https://doi.org/10.1109/VLSID.2012.59","url":null,"abstract":"Summary form only given: We discuss the low-dropout (LDO) voltage regulator pole-zero analysis in this tutorial. A priori knowledge of poles and zeros assist in choosing the right topology and appropriate frequency compensation techniques before implementing the transistor level design, as the location of poles move with output load current. The objective of this tutorial is to provide a step-by-step procedure for analyzing poles and zeros in LDO regulators. To this end, two recent state-of-the-art LDO regulators from the literature are analyzed, explaining several intricacies involved. We explain step-by-step procedure in developing the small-signal model, breaking the voltage/current loop and techniques for quickly arriving at simple and approximate pole-zero equations. During the process, several frequency compensation techniques are elucidated. The derived analytic expressions for poles and zeros help in developing intuition of circuit behavior.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121543700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Finite (Galois) field arithmetic finds applications in cryptography, error correction codes, signal processing, etc. Multiplication usually lies at the core of all Galois field computations and is a high-complexity operation. This paper addresses the problem of formal verification of hardware implementations of modulo-multipliers over Galois fields of the type F2k, using a computer-algebra/algebraic-geometry based approach. The multiplier circuit is modeled as a polynomial system in F2k[x1,x2,⋯,xd] and the verification test is formulated as a Nullstellensatz proof over the finite field. A Grobner basis engine is used as the underlying computational framework. The efficiency of Grobner basis computations depends heavily upon the variable (and term) ordering used to represent and manipulate the polynomials. We present a variable (and term) ordering heuristic that significantly improves the efficiency of Grobner basis engines. Using our approach, we can verify the correctness of up to 96-bit multipliers, whereas contemporary BDDs/SAT/SMT-solver based methods are infeasible.
{"title":"Formal Verification of Galois Field Multipliers Using Computer Algebra Techniques","authors":"Jinpeng Lv, P. Kalla","doi":"10.1109/VLSID.2012.102","DOIUrl":"https://doi.org/10.1109/VLSID.2012.102","url":null,"abstract":"Finite (Galois) field arithmetic finds applications in cryptography, error correction codes, signal processing, etc. Multiplication usually lies at the core of all Galois field computations and is a high-complexity operation. This paper addresses the problem of formal verification of hardware implementations of modulo-multipliers over Galois fields of the type F2k, using a computer-algebra/algebraic-geometry based approach. The multiplier circuit is modeled as a polynomial system in F2k[x1,x2,⋯,xd] and the verification test is formulated as a Nullstellensatz proof over the finite field. A Grobner basis engine is used as the underlying computational framework. The efficiency of Grobner basis computations depends heavily upon the variable (and term) ordering used to represent and manipulate the polynomials. We present a variable (and term) ordering heuristic that significantly improves the efficiency of Grobner basis engines. Using our approach, we can verify the correctness of up to 96-bit multipliers, whereas contemporary BDDs/SAT/SMT-solver based methods are infeasible.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129184098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Jain, Maheedhar Jalasutram, S. Vooka, Prasun Nair, Neeraj Pradhan
In sub-threshold technology nodes, device failure due to timing related defects (setup & hold timing) is on rise due to extreme process variability and increasing use of voltage scaling techniques for achieving required performance. High coverage using stuck-at fault patterns, which can effectively screen static defects is no longer sufficient to control DPPM (Defective parts per million). High test coverage of timing defects that is induced by process variation is required for controlling DPPM. Lot of work has been done to find the ways to increase the delay test coverage of industrial circuits including the various methods to cover inter-domain clock faults but very little or no work is done on the ways to effectively cover the asynchronous reset paths to the memory registers for timing defects. In this paper we propose a novel methodology that allows us to effectively detect the failures induced by timing defects on asynchronous reset path of the registers. This problem is further complicated by the fact that commercially available ATPG tools are not capable of generating test patterns due to modeling limitations. Results from 45nm industrial multi-million gates design is presented to illustrate the effectiveness of the proposed methodology.
{"title":"At-speed Testing of Asynchronous Reset De-assertion Faults","authors":"A. Jain, Maheedhar Jalasutram, S. Vooka, Prasun Nair, Neeraj Pradhan","doi":"10.1109/VLSID.2012.97","DOIUrl":"https://doi.org/10.1109/VLSID.2012.97","url":null,"abstract":"In sub-threshold technology nodes, device failure due to timing related defects (setup & hold timing) is on rise due to extreme process variability and increasing use of voltage scaling techniques for achieving required performance. High coverage using stuck-at fault patterns, which can effectively screen static defects is no longer sufficient to control DPPM (Defective parts per million). High test coverage of timing defects that is induced by process variation is required for controlling DPPM. Lot of work has been done to find the ways to increase the delay test coverage of industrial circuits including the various methods to cover inter-domain clock faults but very little or no work is done on the ways to effectively cover the asynchronous reset paths to the memory registers for timing defects. In this paper we propose a novel methodology that allows us to effectively detect the failures induced by timing defects on asynchronous reset path of the registers. This problem is further complicated by the fact that commercially available ATPG tools are not capable of generating test patterns due to modeling limitations. Results from 45nm industrial multi-million gates design is presented to illustrate the effectiveness of the proposed methodology.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124806762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Banerjee, Shreyas Sen, S. Devarakond, A. Chatterjee
This paper presents a methodology for post-manufacture tuning of MIMO (Multiple-Input-Multiple-Output) wireless systems aimed at increasing device manufacturing yield under large process variations. The goal is to achieve specified system-level EVM (Error Vector Magnitude) targets for MIMO receiver systems by tuning the individual MIMO receiver subsystems whose combined gain, noise and nonlinearity parameters determine the overall system-level EVM metric. While there has been prior work on tuning of SISO systems, the current work is novel due to the fact that the performances of individual receiver subsystems can combine in different ways to result in the same system-level EVM value. As the systems are tuned to meet the system level end-to-end metric it is ensured that all devices that are tuned for EVM consume the least amount of power possible. Tuning infrastructure for MIMO receivers and underlying tuning algorithms are developed in this work. A 1×2 MIMO system for a 2.4 GHz OFDM WLAN is used to demonstrate the core ideas of this research. This work demonstrates a 23% increase in yield of the device with an average power increase of 9.18% for the system under consideration.
{"title":"Power Aware Post-Manufacture Tuning of MIMO Receiver Systems","authors":"D. Banerjee, Shreyas Sen, S. Devarakond, A. Chatterjee","doi":"10.1109/VLSID.2012.61","DOIUrl":"https://doi.org/10.1109/VLSID.2012.61","url":null,"abstract":"This paper presents a methodology for post-manufacture tuning of MIMO (Multiple-Input-Multiple-Output) wireless systems aimed at increasing device manufacturing yield under large process variations. The goal is to achieve specified system-level EVM (Error Vector Magnitude) targets for MIMO receiver systems by tuning the individual MIMO receiver subsystems whose combined gain, noise and nonlinearity parameters determine the overall system-level EVM metric. While there has been prior work on tuning of SISO systems, the current work is novel due to the fact that the performances of individual receiver subsystems can combine in different ways to result in the same system-level EVM value. As the systems are tuned to meet the system level end-to-end metric it is ensured that all devices that are tuned for EVM consume the least amount of power possible. Tuning infrastructure for MIMO receivers and underlying tuning algorithms are developed in this work. A 1×2 MIMO system for a 2.4 GHz OFDM WLAN is used to demonstrate the core ideas of this research. This work demonstrates a 23% increase in yield of the device with an average power increase of 9.18% for the system under consideration.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121771659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mahima Arrawatia, Varish Diddi, H. Kochar, M. Baghini, G. Kumar
This paper presents an energy harvesting system which extracts energy from radio frequency radiation for battery charging applications. It comprises of a new differential center tapped Micro strip antenna, off-chip matching circuit, on-chip novel CMOS rectifier and control circuitry in 180nm CMOS technology. For on-chip modules, thick oxide devices have been used so as to meet the charging requirements of the target batteries. The designed battery charging module charges either of 250 Ah and 10 Ah batteries according to the selected battery and available input power. The 250 Ah battery is charged at input power of 2dBm and 10 Ah battery is charged at input power of -6.5dBm. The fabricated antenna has a gain of 8.3dB and a VSWR less than 2 in the bandwidth from 844 to 970MHz. An efficient Periodic Steady State(PSS)-based power matching technique is also presented which improves the system efficiency. For 0dBm input power at 950 MHz to the antenna the proposed technique leads to 55.2% efficiency of RF to DC converter system. In addition to the integrated design a discrete rectifier using high frequency Schottky diodes and differential micro strip antenna at the input are fabricated. The discrete system uses the proposed matching technique and exhibits efficiency of 40% for-11dBm received power by the antenna.
{"title":"An Integrated CMOS RF Energy Harvester with Differential Microstrip Antenna and On-Chip Charger","authors":"Mahima Arrawatia, Varish Diddi, H. Kochar, M. Baghini, G. Kumar","doi":"10.1109/VLSID.2012.72","DOIUrl":"https://doi.org/10.1109/VLSID.2012.72","url":null,"abstract":"This paper presents an energy harvesting system which extracts energy from radio frequency radiation for battery charging applications. It comprises of a new differential center tapped Micro strip antenna, off-chip matching circuit, on-chip novel CMOS rectifier and control circuitry in 180nm CMOS technology. For on-chip modules, thick oxide devices have been used so as to meet the charging requirements of the target batteries. The designed battery charging module charges either of 250 Ah and 10 Ah batteries according to the selected battery and available input power. The 250 Ah battery is charged at input power of 2dBm and 10 Ah battery is charged at input power of -6.5dBm. The fabricated antenna has a gain of 8.3dB and a VSWR less than 2 in the bandwidth from 844 to 970MHz. An efficient Periodic Steady State(PSS)-based power matching technique is also presented which improves the system efficiency. For 0dBm input power at 950 MHz to the antenna the proposed technique leads to 55.2% efficiency of RF to DC converter system. In addition to the integrated design a discrete rectifier using high frequency Schottky diodes and differential micro strip antenna at the input are fabricated. The discrete system uses the proposed matching technique and exhibits efficiency of 40% for-11dBm received power by the antenna.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125092938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Given a Boolean function, the Unate-Covering Problem (UCP) is NP-hard. This problem can be modeled as a set cover problem where minterms are the elements and implicants form the sets. Traditional solutions in logic synthesis use set cover algorithms that are oblivious to the special semantic of the elements and sets. We propose three new heuristics for the set-cover problem which are aware of the relationship between implicants and minterms. We show that the proposed heuristics are effective for breaking ties when a cyclic core is obtained. We evaluate the heuristics on a set of hard instances from BHOSLIB benchmark suite. We also replace ESPRESSO's set cover algorithm using these heuristics and compare the logic synthesis results. We further map the minimized Boolean equations using ABC's technology mapping tool using 2-input NAND gates and 4-input Lookup Tables (LUTs).
给定一个布尔函数，unate - coverage Problem (UCP)是np困难的。这个问题可以建模为集合覆盖问题，其中最小项是集合的元素和隐含项。传统的逻辑综合解决方案使用集合覆盖算法，忽略了元素和集合的特殊语义。我们提出了三种新的启发式方法来解决集合覆盖问题，它们都意识到隐含项和最小项之间的关系。我们证明，当得到一个循环核时，所提出的启发式方法对于打破联系是有效的。我们在BHOSLIB基准测试套件中的一组硬实例上评估启发式。我们还使用这些启发式算法替换了ESPRESSO的集合覆盖算法，并比较了逻辑综合结果。我们使用ABC的技术映射工具使用2输入NAND门和4输入查找表(LUTs)进一步映射最小化布尔方程。
{"title":"Set-Cover Heuristics for Two-Level Logic Minimization","authors":"Ankit Kagliwal, S. Balachandran","doi":"10.1109/VLSID.2012.70","DOIUrl":"https://doi.org/10.1109/VLSID.2012.70","url":null,"abstract":"Given a Boolean function, the Unate-Covering Problem (UCP) is NP-hard. This problem can be modeled as a set cover problem where minterms are the elements and implicants form the sets. Traditional solutions in logic synthesis use set cover algorithms that are oblivious to the special semantic of the elements and sets. We propose three new heuristics for the set-cover problem which are aware of the relationship between implicants and minterms. We show that the proposed heuristics are effective for breaking ties when a cyclic core is obtained. We evaluate the heuristics on a set of hard instances from BHOSLIB benchmark suite. We also replace ESPRESSO's set cover algorithm using these heuristics and compare the logic synthesis results. We further map the minimized Boolean equations using ABC's technology mapping tool using 2-input NAND gates and 4-input Lookup Tables (LUTs).","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116961459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a sub-circuit model for partially depleted SOI drain extended MOSFETs (DEMOS) based on the HiSIM-HV model suitable for circuit simulator implementation. Our model accounts both for the high voltage and the floating body effects such as the quasi saturation effect, the impact ionization in the drift region and the famous kink effect. The model is validated for a set of channel and drift lengths to demonstrate the scalability of the model. The accuracy of the proposed sub-circuit model is verified using 2-D numerical simulations.
{"title":"Modeling of Partially Depleted SOI DEMOSFETs with a Sub-circuit Utilizing the HiSIM-HV Compact Model","authors":"T. Agarwal, M. J. Kumar","doi":"10.1109/VLSID.2012.105","DOIUrl":"https://doi.org/10.1109/VLSID.2012.105","url":null,"abstract":"This paper presents a sub-circuit model for partially depleted SOI drain extended MOSFETs (DEMOS) based on the HiSIM-HV model suitable for circuit simulator implementation. Our model accounts both for the high voltage and the floating body effects such as the quasi saturation effect, the impact ionization in the drift region and the famous kink effect. The model is validated for a set of channel and drift lengths to demonstrate the scalability of the model. The accuracy of the proposed sub-circuit model is verified using 2-D numerical simulations.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"4 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120970937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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