Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772837
Maitreyi Ashok, E. Levine, A. Chandrakasan
Analog to digital converters (ADCs) are necessary in most Internet of Things (loT) devices, to link the physical analog world to digital computation. Physical side channel attacks (SCAs) have been used to reconstruct information processed within digital integrated circuits in a variety of applications, through power or electromagnetic (EM) traces [1]. Furthermore, power SCAs have successfully decoded the analog information converted within Successive Approximation Register (SAR) ADCs [2], [3]. Previous works have proposed initial protections, such as switched-capacitor current equalization for power SCAs [2], random dithering for the reference charge [3], or general power side channel security using a stacked digital low dropout array and random noise injection [4]. Whereas power SCAs require cutting the power trace and introducing a shunt resistor for measurement, EM SCAs can effectively perform non-invasive measurements external to packaging (Fig. 1). However, supply current equalization is not effective against localized EM SCAs, which can probe currents directly above the ADC circuitry.
{"title":"Randomized Switching SAR (RS-SAR) ADC Protections for Power and Electromagnetic Side Channel Security","authors":"Maitreyi Ashok, E. Levine, A. Chandrakasan","doi":"10.1109/CICC53496.2022.9772837","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772837","url":null,"abstract":"Analog to digital converters (ADCs) are necessary in most Internet of Things (loT) devices, to link the physical analog world to digital computation. Physical side channel attacks (SCAs) have been used to reconstruct information processed within digital integrated circuits in a variety of applications, through power or electromagnetic (EM) traces [1]. Furthermore, power SCAs have successfully decoded the analog information converted within Successive Approximation Register (SAR) ADCs [2], [3]. Previous works have proposed initial protections, such as switched-capacitor current equalization for power SCAs [2], random dithering for the reference charge [3], or general power side channel security using a stacked digital low dropout array and random noise injection [4]. Whereas power SCAs require cutting the power trace and introducing a shunt resistor for measurement, EM SCAs can effectively perform non-invasive measurements external to packaging (Fig. 1). However, supply current equalization is not effective against localized EM SCAs, which can probe currents directly above the ADC circuitry.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129971857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772813
Yangtao Dong, C. Boon, Kaituo Yang, Zhe Liu
Ring voltage-controlled oscillator (VCO) based PLLs have several advantages over LC-VCO based PLLs, like smaller chip area, wider frequency tuning range and multi-phase output signals. However, the inferior jitter/phase noise of ring VCOs has always been the bottleneck of the overall PLL jitter/phase noise performance. To suppress ring VCO's phase noise, feedforward phase noise cancellation (FFPNC) techniques [1]–[4] and feedback phase noise cancellation (FBPNC) technique [5] are widely researched. However, most FFPNC and FBPNC based structures require numerous additional blocks, like complicated phase noise extraction circuits, long voltage-controlled delay line, or additional clock generation circuits, which consumes significant extra area and power. In order to suppress the phase noise of the ring VCO with minimal area and power consumption, this paper proposes a dual-path sub-sampling PLL (SSPLL) architecture incorporating an FBPNC technique. The SSPLL's bandwidth is extended with a compensated phase margin due to the proposed FBPNC technique, as a result, the in-band phase noise contributed by the ring VCO is effectively reduced.
{"title":"A 2-GHz Dual-Path Sub-Sampling PLL with Ring VCO Phase Noise Suppression","authors":"Yangtao Dong, C. Boon, Kaituo Yang, Zhe Liu","doi":"10.1109/CICC53496.2022.9772813","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772813","url":null,"abstract":"Ring voltage-controlled oscillator (VCO) based PLLs have several advantages over LC-VCO based PLLs, like smaller chip area, wider frequency tuning range and multi-phase output signals. However, the inferior jitter/phase noise of ring VCOs has always been the bottleneck of the overall PLL jitter/phase noise performance. To suppress ring VCO's phase noise, feedforward phase noise cancellation (FFPNC) techniques [1]–[4] and feedback phase noise cancellation (FBPNC) technique [5] are widely researched. However, most FFPNC and FBPNC based structures require numerous additional blocks, like complicated phase noise extraction circuits, long voltage-controlled delay line, or additional clock generation circuits, which consumes significant extra area and power. In order to suppress the phase noise of the ring VCO with minimal area and power consumption, this paper proposes a dual-path sub-sampling PLL (SSPLL) architecture incorporating an FBPNC technique. The SSPLL's bandwidth is extended with a compensated phase margin due to the proposed FBPNC technique, as a result, the in-band phase noise contributed by the ring VCO is effectively reduced.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114803519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772786
Animesh Gupta, V. Rajanna, Thoithoi Salam, Saurabh Jain, O. Aiello, P. Crovetti, M. Alioto
Relentless advances in DNN accelerator energy and area efficiency are demanded in low-cost edge devices [1]–[8]. Both directly benefit from the reduction in the complexity of MAC units (neurons), thanks to the reduction in area and energy of computations and the interconnect fabric. Unfortunately, such area and energy cost per neuron further increases in practical cases where flexibility is needed (e.g., precision scaling), ultimately limiting cost and power reductions. In this work, the all-digital DDPMnet architecture for DNN acceleration based on a pulse density data representation is introduced to reduce the gate count/MAC unit from the thousand range to few hundreds (Fig. 1). The proposed architecture removes any arithmetic block from MAC units (e.g., multipliers), while retaining the advantages of standard cell based design.
{"title":"DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm","authors":"Animesh Gupta, V. Rajanna, Thoithoi Salam, Saurabh Jain, O. Aiello, P. Crovetti, M. Alioto","doi":"10.1109/CICC53496.2022.9772786","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772786","url":null,"abstract":"Relentless advances in DNN accelerator energy and area efficiency are demanded in low-cost edge devices [1]–[8]. Both directly benefit from the reduction in the complexity of MAC units (neurons), thanks to the reduction in area and energy of computations and the interconnect fabric. Unfortunately, such area and energy cost per neuron further increases in practical cases where flexibility is needed (e.g., precision scaling), ultimately limiting cost and power reductions. In this work, the all-digital DDPMnet architecture for DNN acceleration based on a pulse density data representation is introduced to reduce the gate count/MAC unit from the thousand range to few hundreds (Fig. 1). The proposed architecture removes any arithmetic block from MAC units (e.g., multipliers), while retaining the advantages of standard cell based design.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126264918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772862
Tianshi Xie, Jianglin Zhu, Tom Byrd, D. Maksimović, Hanh-Phuc Le
As passive components play a critical role in determining the overall footprint of power management solutions, significant efforts have been put into new converter topologies, operating principles, and packaging techniques aimed at reducing the size of passive components [1]–[5]. To achieve these goals, one can increase the effective switching frequency [3]–[5], or use hybrid converter topologies and/or resonant operation to better utilize inductors and capacitors for power transfer. Packaging that prioritizes close proximity and low parasitics is also of particular interest [5]. Starting from the preliminary discrete-circuit implementation in [6], this work strives to achieve the high-density goals based on a new integrated hybrid converter topology and operation, high switching frequency, and advanced packaging, which collectively enable the use of nano-Henry scale inductors. The prototype is fabricated in 3.23 mm2 of a 1P6M 0.13 µm BCD process (Die micrograph).
由于无源元件在决定电源管理解决方案的总体占地面积方面起着至关重要的作用，为了减小无源元件[1]-[5]的尺寸，人们已经在新的转换器拓扑、工作原理和封装技术上投入了大量的努力。为了实现这些目标，可以提高有效开关频率[3]-[5]，或者使用混合转换器拓扑和/或谐振操作来更好地利用电感和电容器进行功率传输。优先考虑近距离和低寄生性的包装也特别令人感兴趣。从[6]的初步离散电路实现开始，本工作努力实现基于新的集成混合转换器拓扑和操作，高开关频率和先进封装的高密度目标，这些共同使纳米亨利级电感器的使用成为可能。该原型是在3.23 mm2的1P6M 0.13 μ m BCD工艺(模具显微图)中制造的。
{"title":"A 0.66 W/mm2 Power Density, 92.4% Peak Efficiency Hybrid Converter with nH-Scale Inductors for 12 V System","authors":"Tianshi Xie, Jianglin Zhu, Tom Byrd, D. Maksimović, Hanh-Phuc Le","doi":"10.1109/CICC53496.2022.9772862","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772862","url":null,"abstract":"As passive components play a critical role in determining the overall footprint of power management solutions, significant efforts have been put into new converter topologies, operating principles, and packaging techniques aimed at reducing the size of passive components [1]–[5]. To achieve these goals, one can increase the effective switching frequency [3]–[5], or use hybrid converter topologies and/or resonant operation to better utilize inductors and capacitors for power transfer. Packaging that prioritizes close proximity and low parasitics is also of particular interest [5]. Starting from the preliminary discrete-circuit implementation in [6], this work strives to achieve the high-density goals based on a new integrated hybrid converter topology and operation, high switching frequency, and advanced packaging, which collectively enable the use of nano-Henry scale inductors. The prototype is fabricated in 3.23 mm2 of a 1P6M 0.13 µm BCD process (Die micrograph).","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"105 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116638491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772865
Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, R. Theertham, S. Pavan, Lu Jie, Nan Sun
CTDSMs with high resolution and bandwidth greater than 200kHz are needed in industrial, medical, and automotive applications. Such high performance demands very low noise and distortion. The noise and distortion have to be suppressed even further in advanced technologies due to the low voltage headroom. A major challenge of low noise and distortion design is the large area cost of DAC and loop filters. The main feedback RDAC occupies a large area in [1]. 1st-order data weighted average (DWA) is used but has limited mismatch error suppression. There is also a kink in the SNDR plot of [1] at low input amplitudes due to tones caused by DWA. To reduce the area, [2], [3] use DWA for the MSB bits and mismatch error shaping (MES) for the LSB bits. MES enables the binary coded DAC to save the LSB DAC area. However, the overall DAC's mismatch-induced distortion is dominated by the MSB bits. Thus, the approach of [2], [3] yields limited performance benefits due to the relatively mild 1st-order mismatch error shaping obtained from the DWA operation on the MSB bits.
{"title":"A 0.37mm2 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2nd-order Vector-Quantizer DEM","authors":"Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, R. Theertham, S. Pavan, Lu Jie, Nan Sun","doi":"10.1109/CICC53496.2022.9772865","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772865","url":null,"abstract":"CTDSMs with high resolution and bandwidth greater than 200kHz are needed in industrial, medical, and automotive applications. Such high performance demands very low noise and distortion. The noise and distortion have to be suppressed even further in advanced technologies due to the low voltage headroom. A major challenge of low noise and distortion design is the large area cost of DAC and loop filters. The main feedback RDAC occupies a large area in [1]. 1st-order data weighted average (DWA) is used but has limited mismatch error suppression. There is also a kink in the SNDR plot of [1] at low input amplitudes due to tones caused by DWA. To reduce the area, [2], [3] use DWA for the MSB bits and mismatch error shaping (MES) for the LSB bits. MES enables the binary coded DAC to save the LSB DAC area. However, the overall DAC's mismatch-induced distortion is dominated by the MSB bits. Thus, the approach of [2], [3] yields limited performance benefits due to the relatively mild 1st-order mismatch error shaping obtained from the DWA operation on the MSB bits.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116882166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Many sensors exhibit output impedances greater than a few MΩ, and the subsequent instrumentation amplifier (IA) must be carefully designed to meet the requirements of high input impedance $(mathrm{R}_{text{in}})$, low noise and low offset. Chopping is a power-efficient technique to achieve low offset and low 1/f noise without noise aliasing [1]–[4], but at the expense of a lower $mathrm{R}_{text{in}}$ (10–100MΩ [1] [4] [5]). Positive feedback loop (PFL) can boost $mathrm{R}_{text{in}}$ of a capacitively-coupled chopper IA (CCIA) by providing a large portion of input source current [4]. However, in practice, the PFL is not suitable for a generic chopper amplifier to achieve a high $mathrm{R}_{text{in}}$ above $100text{MO}$, because the actual impedance boosting factor highly depends on the absolute accuracy of the feedback elements and the overall gain of the IA. For instance, to compensate input parasitic capacitance of 100fF by the PFL, an IA with a voltage gain of 100 requires a very small feedback capacitor of 1fF. Meanwhile, this feedback capacitor must be reconfigured with different IA gains. For the same reason, the PFL is not applicable to a chopper operational amplifier (OPA) either due to its ill-defined open-loop gain. Apart from the limited $mathrm{R}_{text{in}}$, chopper amplifiers also suffer from output ripple, i.e. the up-modulated offset. Prior art ripple reduction loop (RRL) can realize a sub-µV residual input referred ripple [1] [3], but this often involves an active loop integrator with large DC gain and time constant, resulting in power and area overhead.
{"title":"A 1.8GΩ-Input-Impedance 0.15µV-Input-Referred-Ripple Chopper Amplifier with Local Positive Feedback and SAR-Assisted Ripple Reduction","authors":"Tianxiang Qu, Qinjing Pan, Xiaoyang Zeng, Zhiliang Hong, Jiawei Xu","doi":"10.1109/CICC53496.2022.9772860","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772860","url":null,"abstract":"Many sensors exhibit output impedances greater than a few MΩ, and the subsequent instrumentation amplifier (IA) must be carefully designed to meet the requirements of high input impedance $(mathrm{R}_{text{in}})$, low noise and low offset. Chopping is a power-efficient technique to achieve low offset and low 1/f noise without noise aliasing [1]–[4], but at the expense of a lower $mathrm{R}_{text{in}}$ (10–100MΩ [1] [4] [5]). Positive feedback loop (PFL) can boost $mathrm{R}_{text{in}}$ of a capacitively-coupled chopper IA (CCIA) by providing a large portion of input source current [4]. However, in practice, the PFL is not suitable for a generic chopper amplifier to achieve a high $mathrm{R}_{text{in}}$ above $100text{MO}$, because the actual impedance boosting factor highly depends on the absolute accuracy of the feedback elements and the overall gain of the IA. For instance, to compensate input parasitic capacitance of 100fF by the PFL, an IA with a voltage gain of 100 requires a very small feedback capacitor of 1fF. Meanwhile, this feedback capacitor must be reconfigured with different IA gains. For the same reason, the PFL is not applicable to a chopper operational amplifier (OPA) either due to its ill-defined open-loop gain. Apart from the limited $mathrm{R}_{text{in}}$, chopper amplifiers also suffer from output ripple, i.e. the up-modulated offset. Prior art ripple reduction loop (RRL) can realize a sub-µV residual input referred ripple [1] [3], but this often involves an active loop integrator with large DC gain and time constant, resulting in power and area overhead.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127946088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772779
R. Rabbani, Hossein Najafiaghdam, Biqi Zhao, Megan Zeng, V. Stojanović, R. Muller, M. Anwar
Real-time in vivo imaging provides detailed cellular information from targets inside the body. In cancer immunotherapy, for instance, this information can be utilized for early assessments of the treatment, where effective activation of the immune system leads to durable responses against cancer. While only 30% of the patients respond to the treatment, detailed multicellular-level information can help rapidly alter the therapy based on the individual's response. However, this is not possible with current modalities such as CT or MRI that image purely anatomic changes taking months to manifest, by the end of which the window of cure is lost. Moreover, continuous monitoring of the tumor via frequent biopsies is impractical due to the invasiveness of the procedure. To overcome these limitations, fluorescence microscopy can be used to identify multiple cell types within tissue during ongoing therapy.
{"title":"A $36times 40$ Wireless Fluorescence Image Sensor for Real-Time Microscopy in Cancer Therapy","authors":"R. Rabbani, Hossein Najafiaghdam, Biqi Zhao, Megan Zeng, V. Stojanović, R. Muller, M. Anwar","doi":"10.1109/CICC53496.2022.9772779","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772779","url":null,"abstract":"Real-time in vivo imaging provides detailed cellular information from targets inside the body. In cancer immunotherapy, for instance, this information can be utilized for early assessments of the treatment, where effective activation of the immune system leads to durable responses against cancer. While only 30% of the patients respond to the treatment, detailed multicellular-level information can help rapidly alter the therapy based on the individual's response. However, this is not possible with current modalities such as CT or MRI that image purely anatomic changes taking months to manifest, by the end of which the window of cure is lost. Moreover, continuous monitoring of the tumor via frequent biopsies is impractical due to the invasiveness of the procedure. To overcome these limitations, fluorescence microscopy can be used to identify multiple cell types within tissue during ongoing therapy.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126352729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772811
L. Pham-Nguyen, Nam Nguyen-Dac, Thinh Tran-Dinh, H. Pham, M. Je, Sang-Gug Lee, Hanh-Phuc Le
Thermoelectric energy has proved to be a dependable source for sustainable loT devices in practice. However, efficiently harvesting this energy source still remains a challenge because of system size constraints and large conversion ratios from a low input voltage (10s mV) out of a thermoelectric generator (TEG) to ~1V output levels for system circuit loads [1]–[5]. To meet this challenge, different converter topologies have been explored, including a conventional boost topology [1]–[2] and a bipolar hybrid converter [3] that combined a flyback stage with a boost converter. Unfortunately, while the former suffers from an undesirable small duty cycle, leading to low efficiency, the latter requires a bulky transformer, unwanted for loT applications. To better bridge the large voltage gap, a more power-and space-efficient DC-DC converter is desirable for this application.
{"title":"An 86.7%-Efficient Three-Level Boost Converter with Active Voltage Balancing for Thermoelectric Energy Harvesting","authors":"L. Pham-Nguyen, Nam Nguyen-Dac, Thinh Tran-Dinh, H. Pham, M. Je, Sang-Gug Lee, Hanh-Phuc Le","doi":"10.1109/CICC53496.2022.9772811","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772811","url":null,"abstract":"Thermoelectric energy has proved to be a dependable source for sustainable loT devices in practice. However, efficiently harvesting this energy source still remains a challenge because of system size constraints and large conversion ratios from a low input voltage (10s mV) out of a thermoelectric generator (TEG) to ~1V output levels for system circuit loads [1]–[5]. To meet this challenge, different converter topologies have been explored, including a conventional boost topology [1]–[2] and a bipolar hybrid converter [3] that combined a flyback stage with a boost converter. Unfortunately, while the former suffers from an undesirable small duty cycle, leading to low efficiency, the latter requires a bulky transformer, unwanted for loT applications. To better bridge the large voltage gap, a more power-and space-efficient DC-DC converter is desirable for this application.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127145222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772818
Zhixian Deng, H. Qian, Changxuan Han, Yifan Li, Xun Luo
The ever-increasing demands on the high data-rate and high signal-to-noise ratio accelerate the development of high-performance millimeter-wave phased-array systems, especially for 5G NR at 24, 28, 37, and 39GHz bands. However, the reports of the wideband phased-array receiver (RX) [1]–[6] that can fully cover the 24/28/37/39 GHz bands are limited. The suppression of image-signal located at the RF passband is the main challenge for such wideband RX array. Meanwhile, the phase resolution and dynamic range of the phased-array RX should be improved to support multiple applications. This work presents a 23-40GHz phased-array RX in a 40-nm CMOS technology. The proposed phased-array RX consists of a 14-bit phase & gain manager and a noise-cancelling low noise amplifier (LNA). The phase & gain manager with the capacity of rearranging the phase- and gain-control bit can not only provide a maximum 14-bit phase tuning operation and >35dB gain variation range, but also achieve a 28-52dB calibration-free image rejection ratio (IRR) at 23-40GHz by the dual-mode operation. The fabricated chip can support 3Gb/s, 64-QAM and 2.4Gb/s, 256-QAM modulation signal.
{"title":"A 3.8-dB NF, 23-40GHz Phased-Array Receiver with 14-Bit Phase & Gain Manager and Calibration-Free Dual-Mode 28-52dB Image Rejection Ratio for 5G NR","authors":"Zhixian Deng, H. Qian, Changxuan Han, Yifan Li, Xun Luo","doi":"10.1109/CICC53496.2022.9772818","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772818","url":null,"abstract":"The ever-increasing demands on the high data-rate and high signal-to-noise ratio accelerate the development of high-performance millimeter-wave phased-array systems, especially for 5G NR at 24, 28, 37, and 39GHz bands. However, the reports of the wideband phased-array receiver (RX) [1]–[6] that can fully cover the 24/28/37/39 GHz bands are limited. The suppression of image-signal located at the RF passband is the main challenge for such wideband RX array. Meanwhile, the phase resolution and dynamic range of the phased-array RX should be improved to support multiple applications. This work presents a 23-40GHz phased-array RX in a 40-nm CMOS technology. The proposed phased-array RX consists of a 14-bit phase & gain manager and a noise-cancelling low noise amplifier (LNA). The phase & gain manager with the capacity of rearranging the phase- and gain-control bit can not only provide a maximum 14-bit phase tuning operation and >35dB gain variation range, but also achieve a 28-52dB calibration-free image rejection ratio (IRR) at 23-40GHz by the dual-mode operation. The fabricated chip can support 3Gb/s, 64-QAM and 2.4Gb/s, 256-QAM modulation signal.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116050026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772801
J. D. Boles, J. J. Piel, Ng Elaine, Joseph E. Bonavia, J. Lang, D. Perreault
Pursuits of miniaturization, greater performance, and lower cost for power electronics necessitate advancement of power passive component technologies. While wide-bandgap semiconductor devices and advanced control techniques have enabled substantial size and performance improvements, miniaturizing power electronics remains bottlenecked by the passive components dominating their sizes, particularly magnetics (i.e., inductors and transformers). Magnetic components pose fundamental power handling and efficiency challenges at small scales, amounting to lower power densities at low volume [1]–[3]. On the other hand, switched capacitor converters have achieved record-breaking power densities and efficiencies, but these architectures still require magnetics for efficient voltage regulation. While several miniaturization strategies have been developed despite the limitations of magnetics (e.g., higher switching frequencies, more sophisticated circuit topologies and operating techniques, and improved magnetic designs), they ultimately still face the same scaling impediments. This motivates investigation into alternative passive component technologies for power conversion that can provide the same high-level functionalities as magnetics but with superior scalability to small sizes.
{"title":"Piezoelectric-Based Power Conversion: Recent Progress, Opportunities, and Challenges","authors":"J. D. Boles, J. J. Piel, Ng Elaine, Joseph E. Bonavia, J. Lang, D. Perreault","doi":"10.1109/CICC53496.2022.9772801","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772801","url":null,"abstract":"Pursuits of miniaturization, greater performance, and lower cost for power electronics necessitate advancement of power passive component technologies. While wide-bandgap semiconductor devices and advanced control techniques have enabled substantial size and performance improvements, miniaturizing power electronics remains bottlenecked by the passive components dominating their sizes, particularly magnetics (i.e., inductors and transformers). Magnetic components pose fundamental power handling and efficiency challenges at small scales, amounting to lower power densities at low volume [1]–[3]. On the other hand, switched capacitor converters have achieved record-breaking power densities and efficiencies, but these architectures still require magnetics for efficient voltage regulation. While several miniaturization strategies have been developed despite the limitations of magnetics (e.g., higher switching frequencies, more sophisticated circuit topologies and operating techniques, and improved magnetic designs), they ultimately still face the same scaling impediments. This motivates investigation into alternative passive component technologies for power conversion that can provide the same high-level functionalities as magnetics but with superior scalability to small sizes.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132024076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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