Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355762
S. Goel, Narendra Devta-Prasanna, Mark Ward
Shrinking feature size and increased wire density increase the likelihood of occurrence of bridge related defects. N- detect based pattern sets are used commonly to improve the detection of bridge defects. However, achieving high bridge coverage requires deterministic bridge sites extraction from physical layout and bridge fault pattern generation. In this paper, we present a comprehensive comparative analysis about the effectiveness of deterministic bridge fault patterns and n-detect patterns for two large designs (90 and 65nm). We show that extracting different types of bridge faults is required as they represent different unique defect sites. Simulation results show that n-detect patterns have very poor bridge coverage performance and commonly used metric bridge coverage estimate (BCE) does not relate to the true bridge fault coverage. Finally, we discuss the DPPM impact for deterministic bridge fault and n-detect stuck-at patterns for the 90nm design.
{"title":"Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon study","authors":"S. Goel, Narendra Devta-Prasanna, Mark Ward","doi":"10.1109/TEST.2009.5355762","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355762","url":null,"abstract":"Shrinking feature size and increased wire density increase the likelihood of occurrence of bridge related defects. N- detect based pattern sets are used commonly to improve the detection of bridge defects. However, achieving high bridge coverage requires deterministic bridge sites extraction from physical layout and bridge fault pattern generation. In this paper, we present a comprehensive comparative analysis about the effectiveness of deterministic bridge fault patterns and n-detect patterns for two large designs (90 and 65nm). We show that extracting different types of bridge faults is required as they represent different unique defect sites. Simulation results show that n-detect patterns have very poor bridge coverage performance and commonly used metric bridge coverage estimate (BCE) does not relate to the true bridge fault coverage. Finally, we discuss the DPPM impact for deterministic bridge fault and n-detect stuck-at patterns for the 90nm design.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"26 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128802062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355687
Joon-Sung Yang, N. Touba, Shih-Yu Yang, T. M. Mak
An X-tolerant multiple-input signature register (MISR) compaction methodology that compacts output streams containing unknown (X) values was described in [Touba 07]. Unlike conventional approaches, it does not use X-masking logic at the input of the MISR. Instead it uses symbolic simulation to express each bit of the MISR signature as a linear equation in terms of the X's. Linearly dependent combinations of the signature bits are identified with Gaussian elimination and XORed together to cancel out all X values and yield deterministic values. This new X-canceling approach was applied to some industrial designs under the constraints imposed by an industrial test environment. Practical issues for implementing X-canceling are discussed, and a new architecture for implementing X-canceling based on using a shadow register with multiple selective XORs is presented. Experimental results are shown for industrial designs comparing the performance of X-canceling with X-compact.
{"title":"An industrial case study for X-canceling MISR","authors":"Joon-Sung Yang, N. Touba, Shih-Yu Yang, T. M. Mak","doi":"10.1109/TEST.2009.5355687","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355687","url":null,"abstract":"An X-tolerant multiple-input signature register (MISR) compaction methodology that compacts output streams containing unknown (X) values was described in [Touba 07]. Unlike conventional approaches, it does not use X-masking logic at the input of the MISR. Instead it uses symbolic simulation to express each bit of the MISR signature as a linear equation in terms of the X's. Linearly dependent combinations of the signature bits are identified with Gaussian elimination and XORed together to cancel out all X values and yield deterministic values. This new X-canceling approach was applied to some industrial designs under the constraints imposed by an industrial test environment. Practical issues for implementing X-canceling are discussed, and a new architecture for implementing X-canceling based on using a shadow register with multiple selective XORs is presented. Experimental results are shown for industrial designs comparing the performance of X-canceling with X-compact.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125004196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355639
K. Posse, A. Crouch, J. Rearick
The use of embedded test instrumentation in ASIC designs has changed dramatically over the last decade. This is due to a variety of forces that affect the semiconductor industry. Unfortunately, processes surrounding test creation and validation this instrumentation has become significantly more complicated in recent years. IEEE P1687, which is now nearing completion and ballot, addresses these issues and makes the access and control of embedded instruments nearly automatic. This poster session will illustrate the latest innovations in the standard.
{"title":"IEEE P1687 IJTAG a presentation of current technology","authors":"K. Posse, A. Crouch, J. Rearick","doi":"10.1109/TEST.2009.5355639","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355639","url":null,"abstract":"The use of embedded test instrumentation in ASIC designs has changed dramatically over the last decade. This is due to a variety of forces that affect the semiconductor industry. Unfortunately, processes surrounding test creation and validation this instrumentation has become significantly more complicated in recent years. IEEE P1687, which is now nearing completion and ballot, addresses these issues and makes the access and control of embedded instruments nearly automatic. This poster session will illustrate the latest innovations in the standard.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116701991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355702
M. E. Amyeen, S. Venkataraman, M.W. Mak
Diagnosis of functional failures can be used to debug design issues, isolate manufacturing defects, and improve manufacturing yield. Automated failure analysis and rapid root-cause isolation is critical for meeting ever decreasing product time to market demand. Conventional debug approach requires in-depth architecture knowledge and debug expertise. In this paper, we present a two phase approach for isolating microprocessor functional failures. First, failing functional blocks are identified utilizing functional fault simulation. Then, algorithmic diagnosis techniques are applied to accurately identify the failing signals within a functional block. Results are presented showing successful isolation of silicon defects on Intel® Core™ dual-core processor.
{"title":"Microprocessor system failures debug and fault isolation methodology","authors":"M. E. Amyeen, S. Venkataraman, M.W. Mak","doi":"10.1109/TEST.2009.5355702","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355702","url":null,"abstract":"Diagnosis of functional failures can be used to debug design issues, isolate manufacturing defects, and improve manufacturing yield. Automated failure analysis and rapid root-cause isolation is critical for meeting ever decreasing product time to market demand. Conventional debug approach requires in-depth architecture knowledge and debug expertise. In this paper, we present a two phase approach for isolating microprocessor functional failures. First, failing functional blocks are identified utilizing functional fault simulation. Then, algorithmic diagnosis techniques are applied to accurately identify the failing signals within a functional block. Results are presented showing successful isolation of silicon defects on Intel® Core™ dual-core processor.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122106099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355828
Adam W. Ley
Non-intrusive board test (NBT) [1] is an emerging test methodology that integrates several complementary test technologies to restore test coverage lost due to diminishing physical (probe) access to printed circuit boards. While NBT boundary-scan test provides a core capability for structural test (e.g., shorts & opens), NBT processor-controlled test adds an element of functional test (e.g., at-speed operation) and NBT built-in self test delivers performance test (e.g., on-margin operation). A framework to consider the overall test coverage in these multiple dimensions is required to assess the full impact of the test strategy.
{"title":"Defect coverage of non-intrusive board tests (NBT): What does it mean when a non-intrusive board test passes?","authors":"Adam W. Ley","doi":"10.1109/TEST.2009.5355828","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355828","url":null,"abstract":"Non-intrusive board test (NBT) [1] is an emerging test methodology that integrates several complementary test technologies to restore test coverage lost due to diminishing physical (probe) access to printed circuit boards. While NBT boundary-scan test provides a core capability for structural test (e.g., shorts & opens), NBT processor-controlled test adds an element of functional test (e.g., at-speed operation) and NBT built-in self test delivers performance test (e.g., on-margin operation). A framework to consider the overall test coverage in these multiple dimensions is required to assess the full impact of the test strategy.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127723694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355626
B. Lai, C. Rivera, K. Waheed
The key motivation for this work is to enable the use of low cost multi-site testers that exhibit both high transmit test stability and high throughput suitable for massive production of a 2/2.75G GSM/EDGE multi-mode cellular single-chip radio. Due to stringent performance compliance test requirements, transmitter (TX) testing consumes more time on expensive automated test equipment (ATE) and therefore it is critical to develop cost efficient multi-site test schemes, which can exploit parallelism to achieve production testing cost goals. This paper illustrates our low-cost self-contained test methods for both GSM phase trajectory error (PTE) and EDGE TX error vector magnitude (EVM) testing in a TX. We compare our test results with those of the R&S vector signal analyzer (VSA) to demonstrate the achieved test accuracy. Current production solutions allow us to simultaneously test and process up to eight devices using multi-site hardware with eight ATE RF receiver cores. Through scaling and careful hardware/software co-design we are able to realize a sixteen site solution using a combination of serial capture and parallel processing scheme.
{"title":"Enabling GSM/GPRS/EDGE EVM testing on low cost multi-site testers","authors":"B. Lai, C. Rivera, K. Waheed","doi":"10.1109/TEST.2009.5355626","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355626","url":null,"abstract":"The key motivation for this work is to enable the use of low cost multi-site testers that exhibit both high transmit test stability and high throughput suitable for massive production of a 2/2.75G GSM/EDGE multi-mode cellular single-chip radio. Due to stringent performance compliance test requirements, transmitter (TX) testing consumes more time on expensive automated test equipment (ATE) and therefore it is critical to develop cost efficient multi-site test schemes, which can exploit parallelism to achieve production testing cost goals. This paper illustrates our low-cost self-contained test methods for both GSM phase trajectory error (PTE) and EDGE TX error vector magnitude (EVM) testing in a TX. We compare our test results with those of the R&S vector signal analyzer (VSA) to demonstrate the achieved test accuracy. Current production solutions allow us to simultaneously test and process up to eight devices using multi-site hardware with eight ATE RF receiver cores. Through scaling and careful hardware/software co-design we are able to realize a sixteen site solution using a combination of serial capture and parallel processing scheme.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127741884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355636
H. Ehrenberg
IEEE P1581 is aimed at ICs that are otherwise not provisioned with Design For Test (DFT) for any reason, targeting primarily memory devices, but also allowing for implementation in other devices. This Poster provides an overview of Test Mode Entry and Exit Methods proposed in IEEE P1581.
{"title":"Test Mode Entry and Exit Methods for IEEE P1581 compliant devices","authors":"H. Ehrenberg","doi":"10.1109/TEST.2009.5355636","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355636","url":null,"abstract":"IEEE P1581 is aimed at ICs that are otherwise not provisioned with Design For Test (DFT) for any reason, targeting primarily memory devices, but also allowing for implementation in other devices. This Poster provides an overview of Test Mode Entry and Exit Methods proposed in IEEE P1581.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127892472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355594
Tong-Yu Hsieh, M. Breuer, M. Annavaram, S. Gupta, Kuen-Jong Lee
To provide a new avenue for improving yield for nano-scale fabrication processes, we introduce a new notion: performance degrading faults (pdef). A fault is said to be a pdef if it cannot cause a functional error at system outputs but may result in system performance degradation. In a processor, a fault is a pdef if it causes no error in the execution of user programs but may reduce performance, e.g., decrease the number of instructions executed per cycle. By identifying faulty chips that contain pdef's that degrade performance within some limits and binning these chips based on the their resulting instruction throughput, effective yield can be improved in a radically new manner that is completely different from the current practice of performance binning on clock frequency. To illustrate the potential benefits of this notion, we analyze the faults in the branch prediction unit of a processor. Experimental results show that every stuck-at fault in this unit is a pdef. Furthermore, 97% of these faults induce almost no performance degradation.
{"title":"Tolerance of performance degrading faults for effective yield improvement","authors":"Tong-Yu Hsieh, M. Breuer, M. Annavaram, S. Gupta, Kuen-Jong Lee","doi":"10.1109/TEST.2009.5355594","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355594","url":null,"abstract":"To provide a new avenue for improving yield for nano-scale fabrication processes, we introduce a new notion: performance degrading faults (pdef). A fault is said to be a pdef if it cannot cause a functional error at system outputs but may result in system performance degradation. In a processor, a fault is a pdef if it causes no error in the execution of user programs but may reduce performance, e.g., decrease the number of instructions executed per cycle. By identifying faulty chips that contain pdef's that degrade performance within some limits and binning these chips based on the their resulting instruction throughput, effective yield can be improved in a radically new manner that is completely different from the current practice of performance binning on clock frequency. To illustrate the potential benefits of this notion, we analyze the faults in the branch prediction unit of a processor. Experimental results show that every stuck-at fault in this unit is a pdef. Furthermore, 97% of these faults induce almost no performance degradation.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129433228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355655
Liang-Chi Chen, P. Dickinson, P. Dahlgren, S. Davidson, O. Caty, Kevin Wu
Delay test is crucial for finding slow paths and slow ICs, both during bringup and during speed binning. Path delay test has traditionally been considered to be superior in finding slow paths. This paper describes our experiments indicating that this is not always the case. For the UltraSPARC T2 microprocessor series we found that transition delay test often ran slower, was more effective in finding the root cause of the slow path, and correlated well with functional diags also used for speed binning. Transition test does a better job finding delay issues related to the impact of simultaneous switching and coupling noise on chip speed. We used transition test to measure the impact on chip timing of voltage, temperature, and we also used it to confirm the results of improving slow paths.
{"title":"Using transition test to understand timing behavior of logic circuits on UltraSPARCTM T2 family","authors":"Liang-Chi Chen, P. Dickinson, P. Dahlgren, S. Davidson, O. Caty, Kevin Wu","doi":"10.1109/TEST.2009.5355655","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355655","url":null,"abstract":"Delay test is crucial for finding slow paths and slow ICs, both during bringup and during speed binning. Path delay test has traditionally been considered to be superior in finding slow paths. This paper describes our experiments indicating that this is not always the case. For the UltraSPARC T2 microprocessor series we found that transition delay test often ran slower, was more effective in finding the root cause of the slow path, and correlated well with functional diags also used for speed binning. Transition test does a better job finding delay issues related to the impact of simultaneous switching and coupling noise on chip speed. We used transition test to measure the impact on chip timing of voltage, temperature, and we also used it to confirm the results of improving slow paths.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133529479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355900
Youhua Shi, N. Togawa, M. Yanagisawa, T. Ohtsuki
Scan technology carries the potential of being misused as a “side channel” to leak out the secret information of crypto cores. To address such a design challenge, this paper proposes a design-for-secure-test (DFST) solution for crypto cores by adding a stimuli-launched flip-flop into the traditional scan flip-flop to maintain the high test quality without compromising the security.
{"title":"Design-for-secure-test for crypto cores","authors":"Youhua Shi, N. Togawa, M. Yanagisawa, T. Ohtsuki","doi":"10.1109/TEST.2009.5355900","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355900","url":null,"abstract":"Scan technology carries the potential of being misused as a “side channel” to leak out the secret information of crypto cores. To address such a design challenge, this paper proposes a design-for-secure-test (DFST) solution for crypto cores by adding a stimuli-launched flip-flop into the traditional scan flip-flop to maintain the high test quality without compromising the security.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"11218 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126988535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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