Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355673
P. B. Geiger, S. Butkovich
Increasing circuit densities and speeds are quickly reducing electrical test point access for printed circuit assembly test. Boundary-scan (JTAG/IEEE 1149.x) is a technology that will allow continued testability of printed circuit assemblies, but its use requires that it be designed into semiconductor devices. Currently, not all semiconductor suppliers support boundary-scan. Wider availability of complying devices is necessary to enable cost-efficient and effective board test for future designs. This paper presents the results of a boundary-scan survey developed by the International Electronics Manufacturing Initiative (iNEMI). The survey was intended to gauge the current adoption rate of boundary-scan, identify any impediments to widespread use, and select areas for future research.
{"title":"Boundary-scan adoption - an industry snapshot with emphasis on the semiconductor industry","authors":"P. B. Geiger, S. Butkovich","doi":"10.1109/TEST.2009.5355673","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355673","url":null,"abstract":"Increasing circuit densities and speeds are quickly reducing electrical test point access for printed circuit assembly test. Boundary-scan (JTAG/IEEE 1149.x) is a technology that will allow continued testability of printed circuit assemblies, but its use requires that it be designed into semiconductor devices. Currently, not all semiconductor suppliers support boundary-scan. Wider availability of complying devices is necessary to enable cost-efficient and effective board test for future designs. This paper presents the results of a boundary-scan survey developed by the International Electronics Manufacturing Initiative (iNEMI). The survey was intended to gauge the current adoption rate of boundary-scan, identify any impediments to widespread use, and select areas for future research.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125200029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355661
Swapneel Donglikar, Mainak Banga, M. Chandrasekar, M. Hsiao
High test data volume and long test application time are two major concerns for testing scan based circuits. The Illinois Scan (ILS) architecture has been shown to be effective in addressing both these issues. The ILS achieves a high degree of data compression thereby reducing both test data volume and test application time. However, the fault coverage achieved in the Broadcast Mode of the ILS architecture depends on the actual configuration of individual scan chains, i.e., the number of chains and the mapping of the individual flip-flops of the circuit to the respective scan chain positions. Current methods for constructing scan chains in the ILS are either ad-hoc or rely on test pattern information from an apriori ATPG run. In this paper, we present a novel low cost technique to construct ILS scan configuration for a given design. It efficiently utilizes the circuit topology and tries to optimize the flip-flop assignment to a scan chain location without compromising the fault coverage in the Broadcast Mode. Thus, it eliminates the need of an apriori ATPG run or any test set information. Experimental results on the ISCAS'89 benchmark circuits show that the proposed ILS configuration method can achieve on an average 5% more fault coverage in the Broadcast Mode and an average 15% more reduction in total test data volume and test application time than the existing methods.
{"title":"Fast circuit topology based method to configure the scan chains in Illinois Scan architecture","authors":"Swapneel Donglikar, Mainak Banga, M. Chandrasekar, M. Hsiao","doi":"10.1109/TEST.2009.5355661","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355661","url":null,"abstract":"High test data volume and long test application time are two major concerns for testing scan based circuits. The Illinois Scan (ILS) architecture has been shown to be effective in addressing both these issues. The ILS achieves a high degree of data compression thereby reducing both test data volume and test application time. However, the fault coverage achieved in the Broadcast Mode of the ILS architecture depends on the actual configuration of individual scan chains, i.e., the number of chains and the mapping of the individual flip-flops of the circuit to the respective scan chain positions. Current methods for constructing scan chains in the ILS are either ad-hoc or rely on test pattern information from an apriori ATPG run. In this paper, we present a novel low cost technique to construct ILS scan configuration for a given design. It efficiently utilizes the circuit topology and tries to optimize the flip-flop assignment to a scan chain location without compromising the fault coverage in the Broadcast Mode. Thus, it eliminates the need of an apriori ATPG run or any test set information. Experimental results on the ISCAS'89 benchmark circuits show that the proposed ILS configuration method can achieve on an average 5% more fault coverage in the Broadcast Mode and an average 15% more reduction in total test data volume and test application time than the existing methods.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130657136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355555
Grzegorz Mrugalski, N. Mukherjee, J. Rajski, Dariusz Czysz, J. Tyszer
The presented compression scheme is a novel solution that is based on deterministic vector clustering and encompasses three data reduction features in one on-chip decoding system. The approach preserves all benefits of continuous flow decompression and offers compression ratios of order 1000x with encoding efficiency much higher than 1.00.
{"title":"Compression based on deterministic vector clustering of incompatible test cubes","authors":"Grzegorz Mrugalski, N. Mukherjee, J. Rajski, Dariusz Czysz, J. Tyszer","doi":"10.1109/TEST.2009.5355555","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355555","url":null,"abstract":"The presented compression scheme is a novel solution that is based on deterministic vector clustering and encompasses three data reduction features in one on-chip decoding system. The approach preserves all benefits of continuous flow decompression and offers compression ratios of order 1000x with encoding efficiency much higher than 1.00.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133471950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355735
Tasuku Fujibe, M. Suda, Kazuhiro Yamamoto, Y. Nagata, Kazuhiro Fujita, D. Watanabe, T. Okayasu
A dynamic arbitrary jitter injection method that can be integrated into our high speed and high density CMOS timing generator has been developed. This method makes it possible to inject arbitrary jitter including Periodic Jitter, Random Jitter and Data Dependent Jitter in order to realize flexible SerDes device testing. By this method, furthermore, jitter injection is dynamically and synchronously controllable according to a test pattern. We have implemented our jitter injection method in a prototype chip to demonstrate the concept. The chip includes a 6.5Gb/s timing generator and was fabricated by a 90nm CMOS process. Area and power consumption for each edge including the jitter injection scheme and timing generator are 0.2mm2 and 43.8mW respectively.
{"title":"Dynamic arbitrary jitter injection method for ≫6.5Gb/s SerDes testing","authors":"Tasuku Fujibe, M. Suda, Kazuhiro Yamamoto, Y. Nagata, Kazuhiro Fujita, D. Watanabe, T. Okayasu","doi":"10.1109/TEST.2009.5355735","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355735","url":null,"abstract":"A dynamic arbitrary jitter injection method that can be integrated into our high speed and high density CMOS timing generator has been developed. This method makes it possible to inject arbitrary jitter including Periodic Jitter, Random Jitter and Data Dependent Jitter in order to realize flexible SerDes device testing. By this method, furthermore, jitter injection is dynamically and synchronously controllable according to a test pattern. We have implemented our jitter injection method in a prototype chip to demonstrate the concept. The chip includes a 6.5Gb/s timing generator and was fabricated by a 90nm CMOS process. Area and power consumption for each edge including the jitter injection scheme and timing generator are 0.2mm2 and 43.8mW respectively.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128087729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355588
Colin D. Renfrew, Brian Booth, Shweta Latawa, R. Woltenberg, C. Pyron
This paper describes how at-speed testing for delay faults was achieved on the P2020 QorIQ device. Modifications to the scan clocking architecture were made over previous designs in order to facilitate at-speed testing and improve overall test coverage. A methodology for ATPG was derived for this enhanced architecture and applied to the device. The design and implementation will be presented in this paper, along with results from ATPG and silicon.
{"title":"At-speed test on the QorIQTM P2020 platform","authors":"Colin D. Renfrew, Brian Booth, Shweta Latawa, R. Woltenberg, C. Pyron","doi":"10.1109/TEST.2009.5355588","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355588","url":null,"abstract":"This paper describes how at-speed testing for delay faults was achieved on the P2020 QorIQ device. Modifications to the scan clocking architecture were made over previous designs in order to facilitate at-speed testing and improve overall test coverage. A methodology for ATPG was derived for this enhanced architecture and applied to the device. The design and implementation will be presented in this paper, along with results from ATPG and silicon.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125816052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355830
S. Carlo, N. Hatami, P. Prinetto
The goal of this work is to propose a method to fully exploit TLM2.0 potentialities to evaluate test infrastructures. By providing the high level model with necessary information from RTL, the behavior of test infrastructures can be simulated taking advantage of high simulation speed of TLM. This way, the high level model is able to both estimate the cost of test infrastructure much faster and facilitate decision making for proper test infrastructure at RTL.
{"title":"Test infrastructures evaluation at transaction level","authors":"S. Carlo, N. Hatami, P. Prinetto","doi":"10.1109/TEST.2009.5355830","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355830","url":null,"abstract":"The goal of this work is to propose a method to fully exploit TLM2.0 potentialities to evaluate test infrastructures. By providing the high level model with necessary information from RTL, the behavior of test infrastructures can be simulated taking advantage of high simulation speed of TLM. This way, the high level model is able to both estimate the cost of test infrastructure much faster and facilitate decision making for proper test infrastructure at RTL.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126175587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355733
M. O. Simsir, N. Jha
It is a well known fact that during testing of a complex integrated circuit (IC), power consumption can far exceed the values reached during its normal operation. High power consumption, combined with limited cooling support, leads to overheating of ICs. This can cause permanent damage to the chip or can invalidate test results due to changes in the path delay. Therefore, even good chips can fail the test. To prevent this problem, a methodology to generate the thermal profile of chips during test is needed. If such profiles are provided beforehand, temperature-aware testing techniques can be devised. In this paper, we address this problem by presenting a methodology for thermally characterizing circuits under test. In our methodology, first, the test sequences for each targeted test strategy, namely, built-in self-test (BIST), scan design and sequential test generation, are generated automatically. Then, power profiles are extracted by using the switching activity information obtained from simulations. Finally, a very fast thermal profiling tool is used to produce the final thermal profiles. To the best of our knowledge, this is the first work on characterizing the thermal effects of different test methods. Such a thermal characterization can be leveraged for temperature-aware system-on-chip (SoC) test scheduling. Our experimental results present the maximum temperature values attained when using different testing techniques on several benchmarks. Results also demonstrate that low power testing techniques are not necessarily temperature-aware.
{"title":"Thermal characterization of BIST, scan design and sequential test methodologies","authors":"M. O. Simsir, N. Jha","doi":"10.1109/TEST.2009.5355733","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355733","url":null,"abstract":"It is a well known fact that during testing of a complex integrated circuit (IC), power consumption can far exceed the values reached during its normal operation. High power consumption, combined with limited cooling support, leads to overheating of ICs. This can cause permanent damage to the chip or can invalidate test results due to changes in the path delay. Therefore, even good chips can fail the test. To prevent this problem, a methodology to generate the thermal profile of chips during test is needed. If such profiles are provided beforehand, temperature-aware testing techniques can be devised. In this paper, we address this problem by presenting a methodology for thermally characterizing circuits under test. In our methodology, first, the test sequences for each targeted test strategy, namely, built-in self-test (BIST), scan design and sequential test generation, are generated automatically. Then, power profiles are extracted by using the switching activity information obtained from simulations. Finally, a very fast thermal profiling tool is used to produce the final thermal profiles. To the best of our knowledge, this is the first work on characterizing the thermal effects of different test methods. Such a thermal characterization can be leveraged for temperature-aware system-on-chip (SoC) test scheduling. Our experimental results present the maximum temperature values attained when using different testing techniques on several benchmarks. Results also demonstrate that low power testing techniques are not necessarily temperature-aware.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126577520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355631
B. Bai, C. Li, A. Kifli, E. Tsai, Kun-Cheng Wu
This poster presents Power Scan, a design-for-testability for power switches in VLSI designs. It measures IR drop in function mode and detects leakage current in sleep mode. Power Scan reduces the test cost at the price of small area overhead.
{"title":"Power scan: DFT for power switches in VLSI designs","authors":"B. Bai, C. Li, A. Kifli, E. Tsai, Kun-Cheng Wu","doi":"10.1109/TEST.2009.5355631","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355631","url":null,"abstract":"This poster presents Power Scan, a design-for-testability for power switches in VLSI designs. It measures IR drop in function mode and detects leakage current in sleep mode. Power Scan reduces the test cost at the price of small area overhead.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115197456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355811
M. Portolan, Suresh Goyal, B. G. V. Treuren
This paper presents the Test Instruction Set Architecture (TISA), an invention that can enable scalable interactive testing to leverage the experience of embedded computing. This approach is applied to an 1149.1 system, obtaining a processor able to efficiently handle instrument-based operations.
{"title":"Scalable and efficient integrated test architecture","authors":"M. Portolan, Suresh Goyal, B. G. V. Treuren","doi":"10.1109/TEST.2009.5355811","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355811","url":null,"abstract":"This paper presents the Test Instruction Set Architecture (TISA), an invention that can enable scalable interactive testing to leverage the experience of embedded computing. This approach is applied to an 1149.1 system, obtaining a processor able to efficiently handle instrument-based operations.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"202 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124933217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355837
K. Parker, J. Burgess
This poster will provide a high-level description of IEEE P1149.8.1 and the manufacturing board test problem set it addresses. The poster will serve as a follow on to a paper (Session 2.1) which will be presented earlier in the conference. The principal goal of the poster is to raise awareness (and participation) for the developing standard.
{"title":"What is IEEE P1149.8.1 and why?","authors":"K. Parker, J. Burgess","doi":"10.1109/TEST.2009.5355837","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355837","url":null,"abstract":"This poster will provide a high-level description of IEEE P1149.8.1 and the manufacturing board test problem set it addresses. The poster will serve as a follow on to a paper (Session 2.1) which will be presented earlier in the conference. The principal goal of the poster is to raise awareness (and participation) for the developing standard.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128726695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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