Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355531
Shreyas Sen, S. Devarakond, A. Chatterjee
Amplitude-to-amplitude (AM-AM) and amplitude-to-phase (AM-PM) distortion are two significant effects in power amplifiers at high output power levels. Traditional measurement of amplitude and phase distortion in RF power amplifiers requires the use of expensive vector network analyzers (VNAs). This paper proposes a low cost and accurate test methodology for AM-AM and AM-PM measurement using distortion-to-amplitude conversion using simple load board test circuitry along with the use of hardware and software based difference generation and peak detection mechanisms. It is seen that both distortion effects can be measured with high accuracy while allowing significant reduction in test cost.
{"title":"Low cost AM/AM and AM/PM distortion measurement using distortion-to-amplitude transformations","authors":"Shreyas Sen, S. Devarakond, A. Chatterjee","doi":"10.1109/TEST.2009.5355531","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355531","url":null,"abstract":"Amplitude-to-amplitude (AM-AM) and amplitude-to-phase (AM-PM) distortion are two significant effects in power amplifiers at high output power levels. Traditional measurement of amplitude and phase distortion in RF power amplifiers requires the use of expensive vector network analyzers (VNAs). This paper proposes a low cost and accurate test methodology for AM-AM and AM-PM measurement using distortion-to-amplitude conversion using simple load board test circuitry along with the use of hardware and software based difference generation and peak detection mechanisms. It is seen that both distortion effects can be measured with high accuracy while allowing significant reduction in test cost.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116341797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355736
T. Lyons
For many semiconductor devices, time stability and relative time location of electrical events is critical; clocks need to strobe data when the data is valid. This fundamental performance is indicative of both the general quality of manufacture and the suitability of a particular device. Parametric measures might include duty cycle variation, peak-to-peak jitter, RMS jitter and minimum pulse width. As increasingly complex timing generation circuits are implemented with mixed analog and digital technology, more sophisticated testing requires a time sense between events (e.g. cycle-to-cycle jitter, period jitter and deterministic jitter.)
{"title":"A timestamping method using reduced cost ADC hardware","authors":"T. Lyons","doi":"10.1109/TEST.2009.5355736","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355736","url":null,"abstract":"For many semiconductor devices, time stability and relative time location of electrical events is critical; clocks need to strobe data when the data is valid. This fundamental performance is indicative of both the general quality of manufacture and the suitability of a particular device. Parametric measures might include duty cycle variation, peak-to-peak jitter, RMS jitter and minimum pulse width. As increasingly complex timing generation circuits are implemented with mixed analog and digital technology, more sophisticated testing requires a time sense between events (e.g. cycle-to-cycle jitter, period jitter and deterministic jitter.)","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126174053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355573
E. Marinissen, Y. Zorian
Today's miniaturization and performance requirements result in the usage of high-density integration and packaging technologies, such as 3D Stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs). Due to their advanced manufacturing processes and physical access limitations, the complexity and cost associated with testing this type of 3D-SICs are considered major challenges. This Embedded Tutorial provides an overview of the manufacturing steps of TSV-based 3D chips and their associated test challenges. It discusses the necessary flows for wafer-level and package-level tests, the challenges with respect to test contents and wafer-level probe access, and the on-chip DfT infrastructure required for 3D-SICs.
{"title":"Testing 3D chips containing through-silicon vias","authors":"E. Marinissen, Y. Zorian","doi":"10.1109/TEST.2009.5355573","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355573","url":null,"abstract":"Today's miniaturization and performance requirements result in the usage of high-density integration and packaging technologies, such as 3D Stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs). Due to their advanced manufacturing processes and physical access limitations, the complexity and cost associated with testing this type of 3D-SICs are considered major challenges. This Embedded Tutorial provides an overview of the manufacturing steps of TSV-based 3D chips and their associated test challenges. It discusses the necessary flows for wafer-level and package-level tests, the challenges with respect to test contents and wafer-level probe access, and the on-chip DfT infrastructure required for 3D-SICs.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128206742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355572
Adam W. Ley
IEEE Std 1149.7 offers a means to reduce chip pins dedicated to test (and debug) access while enhancing the functionality of the Test Access Port (TAP) as a complementary superset of the original IEEE Std 1149.1 (JTAG). Extended features such as hot-plug immunity, power management, optimization of scan throughput, access to instrumentation, and access to custom technologies provide welcome improvements for debug. Further, the boundary-scan architecture is bolstered to ensure full support for test. This important advancement in test and debug interfaces is well suited for access to multiple cores on SOC or multiple die in SIP or POP.
{"title":"Doing more with less - An IEEE 1149.7 embedded tutorial : Standard for reduced-pin and enhanced-functionality test access port and boundary-scan architecture","authors":"Adam W. Ley","doi":"10.1109/TEST.2009.5355572","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355572","url":null,"abstract":"IEEE Std 1149.7 offers a means to reduce chip pins dedicated to test (and debug) access while enhancing the functionality of the Test Access Port (TAP) as a complementary superset of the original IEEE Std 1149.1 (JTAG). Extended features such as hot-plug immunity, power management, optimization of scan throughput, access to instrumentation, and access to custom technologies provide welcome improvements for debug. Further, the boundary-scan architecture is bolstered to ensure full support for test. This important advancement in test and debug interfaces is well suited for access to multiple cores on SOC or multiple die in SIP or POP.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127277017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355600
Fassely Doumbia, O. Laurent, Didier Atger, C. Robach
Our work is focused on a diagnosis approach for the system testing process on AIRBUS Final Assembly Line. The method described below supports tests definition for diagnosis and faulty component identification based on functional testing.
{"title":"Using the Multiple-Clue approach for system testing on AIRBUS FAL (Final Assembly Line)","authors":"Fassely Doumbia, O. Laurent, Didier Atger, C. Robach","doi":"10.1109/TEST.2009.5355600","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355600","url":null,"abstract":"Our work is focused on a diagnosis approach for the system testing process on AIRBUS Final Assembly Line. The method described below supports tests definition for diagnosis and faulty component identification based on functional testing.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131095397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355707
J. Nonaka, T. Ishiyama, Kazuki Shigeta
The method to insert observation points by replacing cells is proposed for laser voltage probing (LVP) measurements to ease failure analysis. Also proposed are a model of delay change with placing observation points and its insertion procedure that minimizes the number of timing violations. Evaluation in a commercial product circuit shows that “replacement-type” observation points can be inserted efficiently on critical paths which left less setup margin to insert “additional-type” ones. The number of timing violations caused insertion is a little and those can be easily fixed by using proposed delay model. The proposed method is thus practical for commercial product design and effective for delay fault analysis. This application will be attractive to find defects in complicated VLSI circuits because failure analysis becomes more difficult to downsize transistors smaller than the resolution of the failure analysis equipments such as LVP.
{"title":"Design for failure analysis inserting replacement-type observation points for LVP","authors":"J. Nonaka, T. Ishiyama, Kazuki Shigeta","doi":"10.1109/TEST.2009.5355707","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355707","url":null,"abstract":"The method to insert observation points by replacing cells is proposed for laser voltage probing (LVP) measurements to ease failure analysis. Also proposed are a model of delay change with placing observation points and its insertion procedure that minimizes the number of timing violations. Evaluation in a commercial product circuit shows that “replacement-type” observation points can be inserted efficiently on critical paths which left less setup margin to insert “additional-type” ones. The number of timing violations caused insertion is a little and those can be easily fixed by using proposed delay model. The proposed method is thus practical for commercial product design and effective for delay fault analysis. This application will be attractive to find defects in complicated VLSI circuits because failure analysis becomes more difficult to downsize transistors smaller than the resolution of the failure analysis equipments such as LVP.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115427101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355593
Ping-Chuan Lu, D. Glaser, G. Uygur, K. Helmreich
Test cost is and will continue to be one of the most important issues, especially in testing analog, mixed-signal and RF devices. When considering overall test cost, the key factors are low cost test equipment, low cost of ownership and low test development cost. Universal ATE (`big iron') is associated with high equipment cost but its powerful SW enables cost-efficient test development. Rack&Stack systems, on the other hand, can be assembled from inexpensive components, but load test engineers with much higher effort for test development and debug. This paper describes a concept that promises to combine the respective advantages of Rack&Stack and universal test systems by establishing a versatile test platform in HW based on industry standards enabling modular, least-cost, application-specific configuration with a likewise standard based SW environment for efficient test generation and debug, inherently supporting virtual test and test synthesis from formal specification.
{"title":"The best of both worlds: Merging the benefits of Rack&Stack and universal ATE","authors":"Ping-Chuan Lu, D. Glaser, G. Uygur, K. Helmreich","doi":"10.1109/TEST.2009.5355593","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355593","url":null,"abstract":"Test cost is and will continue to be one of the most important issues, especially in testing analog, mixed-signal and RF devices. When considering overall test cost, the key factors are low cost test equipment, low cost of ownership and low test development cost. Universal ATE (`big iron') is associated with high equipment cost but its powerful SW enables cost-efficient test development. Rack&Stack systems, on the other hand, can be assembled from inexpensive components, but load test engineers with much higher effort for test development and debug. This paper describes a concept that promises to combine the respective advantages of Rack&Stack and universal test systems by establishing a versatile test platform in HW based on industry standards enabling modular, least-cost, application-specific configuration with a likewise standard based SW environment for efficient test generation and debug, inherently supporting virtual test and test synthesis from formal specification.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115583802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355696
Hsuan-Chung Ko, Deng-Yao Chang, Cheng-Nan Hu
This work proposes a novel ATE test approach to decrease RF testing yield loss. Background noise of the system-under-test is surveyed based on a prototype load-board equipped with a PCB antenna system to analyze the correlation between the test data and background noise in order to identify the root causes of yield loss. Experimental results of RF testing in the EMI environment correlate well with a low yield mass production scenario that is estimated to address the EMI issue.
{"title":"Cost-effective approach to improve EMI yield loss","authors":"Hsuan-Chung Ko, Deng-Yao Chang, Cheng-Nan Hu","doi":"10.1109/TEST.2009.5355696","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355696","url":null,"abstract":"This work proposes a novel ATE test approach to decrease RF testing yield loss. Background noise of the system-under-test is surveyed based on a prototype load-board equipped with a PCB antenna system to analyze the correlation between the test data and background noise in order to identify the root causes of yield loss. Experimental results of RF testing in the EMI environment correlate well with a low yield mass production scenario that is estimated to address the EMI issue.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121479348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355693
Jocelyn Moreau, Thomas Droniou, P. Lebourg, Paul Armagnat
Imagers are pretty little objects nowadays, their size is always shrinking and having only three standard digital pins available on their package is a most common thing. Looking back in 2006, only three years ago, people asked for a solution to run industrial structural test on such complex devices could though only reply “impossible” or “Do It Yourself”. STMicroelectronics did not escape the rule. An internal development and a partnered development were thus successively launched to address this issue. This article proposes to examine all the why and how of these developments along with the good results obtained during that time, in terms of test cost improvement, area overhead in silicon, design flow updates and industrialization process. Getting all sensors designed today equipped and test data volume (and time) improvements in the range of 25X to 30X just took that three years time. Now that the solution is industrially available, it's also time to share and look at the future of industrial scan test on three pins…
{"title":"Running scan test on three pins: yes we can!","authors":"Jocelyn Moreau, Thomas Droniou, P. Lebourg, Paul Armagnat","doi":"10.1109/TEST.2009.5355693","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355693","url":null,"abstract":"Imagers are pretty little objects nowadays, their size is always shrinking and having only three standard digital pins available on their package is a most common thing. Looking back in 2006, only three years ago, people asked for a solution to run industrial structural test on such complex devices could though only reply “impossible” or “Do It Yourself”. STMicroelectronics did not escape the rule. An internal development and a partnered development were thus successively launched to address this issue. This article proposes to examine all the why and how of these developments along with the good results obtained during that time, in terms of test cost improvement, area overhead in silicon, design flow updates and industrialization process. Getting all sensors designed today equipped and test data volume (and time) improvements in the range of 25X to 30X just took that three years time. Now that the solution is industrially available, it's also time to share and look at the future of industrial scan test on three pins…","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"378 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115908852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355668
S. Devadze, A. Jutman, I. Aleksejev, R. Ubar
This paper describes a new test access protocol for system-level testing of printed circuit boards for manufacturing defects. We show that the protocol can be based on standard Boundary Scan (BS) instructions and test access mechanism (TAM). It means that the methodology does not require any changes/redesign of hardware and can be immediately implemented in the electronic manufacturing. Our solution needs however a proper software support and availability of programmable devices (FPGAs, CPLDs, etc.) on the board under test. The new technique dramatically extends the applicability of BS testing in the reality of modern complex on-board data transfer buses and protocols. Potentially, it can also increase the speed of in-system programming of flash memories and other tasks that are traditionally performed using BS.
{"title":"Fast extended test access via JTAG and FPGAs","authors":"S. Devadze, A. Jutman, I. Aleksejev, R. Ubar","doi":"10.1109/TEST.2009.5355668","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355668","url":null,"abstract":"This paper describes a new test access protocol for system-level testing of printed circuit boards for manufacturing defects. We show that the protocol can be based on standard Boundary Scan (BS) instructions and test access mechanism (TAM). It means that the methodology does not require any changes/redesign of hardware and can be immediately implemented in the electronic manufacturing. Our solution needs however a proper software support and availability of programmable devices (FPGAs, CPLDs, etc.) on the board under test. The new technique dramatically extends the applicability of BS testing in the reality of modern complex on-board data transfer buses and protocols. Potentially, it can also increase the speed of in-system programming of flash memories and other tasks that are traditionally performed using BS.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123313889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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