Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355817
L. Losik
Product factory test is inadequate to identify 100% of the products that will fail within one year of use before shipment. Product infant mortality failures that would occur after delivery are eliminated by using prognostic analysis for illustrating and identifying deterministic behavior (failure precursors) in all products that will fail in the near future.
{"title":"Eliminating product infant mortality failures using prognostic analysis","authors":"L. Losik","doi":"10.1109/TEST.2009.5355817","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355817","url":null,"abstract":"Product factory test is inadequate to identify 100% of the products that will fail within one year of use before shipment. Product infant mortality failures that would occur after delivery are eliminated by using prognostic analysis for illustrating and identifying deterministic behavior (failure precursors) in all products that will fail in the near future.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"53 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114021623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355549
Sankar Gurumurthy, D. Bertanzetti, P. Jakobsen, J. Rearick
A technique is described for testing the I/O interfaces of a microprocessor through the use of cache-resident self-test. Experimental results show that this test application method executes much faster than traditional scan-based testing for both characterization and production versions of the tests. The addition of on-chip post-processing of test results further enhances the speedup. The method is compatible with low-cost testers.
{"title":"Cache-resident self-testing for I/O circuitry","authors":"Sankar Gurumurthy, D. Bertanzetti, P. Jakobsen, J. Rearick","doi":"10.1109/TEST.2009.5355549","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355549","url":null,"abstract":"A technique is described for testing the I/O interfaces of a microprocessor through the use of cache-resident self-test. Experimental results show that this test application method executes much faster than traditional scan-based testing for both characterization and production versions of the tests. The addition of on-chip post-processing of test results further enhances the speedup. The method is compatible with low-cost testers.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114669552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355543
F. Stellari, P. Song, J. Sylvestri, D. Miles, Orazio P. Forlenza, D. Forlenza
In this paper, a new emission-based method for measuring the amplitude of on-chip power supply noise is presented. This technique uses Time Resolved Emission (TRE) waveforms of Light Emission from Off-State Leakage Current (LEOSLC) from CMOS gates, which are used as local probe points for the noise. In order to demonstrate the capabilities of this technique, we discuss the results obtained for two early microprocessor chips fabricated in 65 nm and 45 nm Silicon On Insulator (SOI) technologies.
{"title":"On-chip power supply noise measurement using Time Resolved Emission (TRE) waveforms of Light Emission from Off-State Leakage Current (LEOSLC)","authors":"F. Stellari, P. Song, J. Sylvestri, D. Miles, Orazio P. Forlenza, D. Forlenza","doi":"10.1109/TEST.2009.5355543","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355543","url":null,"abstract":"In this paper, a new emission-based method for measuring the amplitude of on-chip power supply noise is presented. This technique uses Time Resolved Emission (TRE) waveforms of Light Emission from Off-State Leakage Current (LEOSLC) from CMOS gates, which are used as local probe points for the noise. In order to demonstrate the capabilities of this technique, we discuss the results obtained for two early microprocessor chips fabricated in 65 nm and 45 nm Silicon On Insulator (SOI) technologies.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114816880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355906
Bilal El Kassir, C. Kelma, B. Jarry, M. Campovecchio
In Wireless systems, the overall quality of transmission and reception is determined by various baseband and RF system specifications. The Error Vector Magnitude (EVM) is a measure of the digital modulation quality of the wireless system-under-test which is very sensitive to much impairment in the transceiver. However the EVM test takes a long time and requires expansive Automatic Test Equipment (ATE) in Production. The originality of the proposed approach lies in its ability to overcome two limitations being faced by available techniques (correction signal, reference synchronization, correlation analysis), in addition to length frame reduction. In order to decrease the test cost, time and length sequence, a new EVM measurement method using Built-in Self Test (BIST) is proposed in this paper. Using a digital phase shifter and a multiplier, a reduced QPSK data sequence minimizes the test time and covers the faults such as IQ impairments and amplification distortions. The BIST method demonstrates only 1% difference compared to the usual EVM method and is 1000 times faster than the traditional EVM test (it takes 200µs).
{"title":"Built-in Self Test for Error Vector Magnitude measurement of RF transceiver","authors":"Bilal El Kassir, C. Kelma, B. Jarry, M. Campovecchio","doi":"10.1109/TEST.2009.5355906","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355906","url":null,"abstract":"In Wireless systems, the overall quality of transmission and reception is determined by various baseband and RF system specifications. The Error Vector Magnitude (EVM) is a measure of the digital modulation quality of the wireless system-under-test which is very sensitive to much impairment in the transceiver. However the EVM test takes a long time and requires expansive Automatic Test Equipment (ATE) in Production. The originality of the proposed approach lies in its ability to overcome two limitations being faced by available techniques (correction signal, reference synchronization, correlation analysis), in addition to length frame reduction. In order to decrease the test cost, time and length sequence, a new EVM measurement method using Built-in Self Test (BIST) is proposed in this paper. Using a digital phase shifter and a multiplier, a reduced QPSK data sequence minimizes the test time and covers the faults such as IQ impairments and amplification distortions. The BIST method demonstrates only 1% difference compared to the usual EVM method and is 1000 times faster than the traditional EVM test (it takes 200µs).","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"331 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123516070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355701
D. Keezer, C. Gray, A. Majid, D. Minier, P. Ducharme
An adaptable platform for the development of customized ATE and test-support modules is described. The purpose of the platform is to provide a hardware framework for assembling combinations of specialized test modules for applications that are not well addressed by conventional general-purpose ATE alone. The platform can also be used to test, characterize, and calibrate individual modules prior to use within either a platform-based application or within a traditional ATE environment. The paper describes some of the salient features of the platform and one completed example for an all-optical packet-switching network called “Data Vortex” operating at 2.5Gbps on each of 18 channels (≫40Gbps aggregate burst data rate). Two other example modules demonstrate even higher data rates. One is a dual-channel, bidirectional 5Gbps FPGA-based module with loopback, jitter-injection, and 2:1 XOR multiplexing (up to 10Gbps). This module exploits recent advances in FPGA technology that enable very high data rates at relatively low cost. Another example module synthesizes two 10Gbps data streams using 16:1 SiGe serializers; and then combines these using an InP XOR gate to form a 20Gbps test stimulus channel. While the platform and modules have interesting characteristics, individually they do not form a complete solution. However the various possible combinations, together with special-purpose modules, may help solve some of the most difficult test applications in the near future. Therefore, this paper tries to present the key features in a way that the reader may extrapolate to future test challenges.
{"title":"A development platform and electronic modules for automated test up to 20 Gbps","authors":"D. Keezer, C. Gray, A. Majid, D. Minier, P. Ducharme","doi":"10.1109/TEST.2009.5355701","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355701","url":null,"abstract":"An adaptable platform for the development of customized ATE and test-support modules is described. The purpose of the platform is to provide a hardware framework for assembling combinations of specialized test modules for applications that are not well addressed by conventional general-purpose ATE alone. The platform can also be used to test, characterize, and calibrate individual modules prior to use within either a platform-based application or within a traditional ATE environment. The paper describes some of the salient features of the platform and one completed example for an all-optical packet-switching network called “Data Vortex” operating at 2.5Gbps on each of 18 channels (≫40Gbps aggregate burst data rate). Two other example modules demonstrate even higher data rates. One is a dual-channel, bidirectional 5Gbps FPGA-based module with loopback, jitter-injection, and 2:1 XOR multiplexing (up to 10Gbps). This module exploits recent advances in FPGA technology that enable very high data rates at relatively low cost. Another example module synthesizes two 10Gbps data streams using 16:1 SiGe serializers; and then combines these using an InP XOR gate to form a 20Gbps test stimulus channel. While the platform and modules have interesting characteristics, individually they do not form a complete solution. However the various possible combinations, together with special-purpose modules, may help solve some of the most difficult test applications in the near future. Therefore, this paper tries to present the key features in a way that the reader may extrapolate to future test challenges.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127853124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355814
Boyon Kim, Il-Chan Park, G. Song, Wooseong Choi, Byeong-Yun Kim, Kyu-Hoon Lee, Chi-young Choi
Same output frequencies at each DUT of the testing circuit are multiplied by different LO frequencies signals at mixers stages, which different frequency-translated spectrums were captured at capture port simultaneously for achieving fully parallel test of RF device.
{"title":"A novel multisite testing techniques by using frequency synthesizer","authors":"Boyon Kim, Il-Chan Park, G. Song, Wooseong Choi, Byeong-Yun Kim, Kyu-Hoon Lee, Chi-young Choi","doi":"10.1109/TEST.2009.5355814","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355814","url":null,"abstract":"Same output frequencies at each DUT of the testing circuit are multiplied by different LO frequencies signals at mixers stages, which different frequency-translated spectrums were captured at capture port simultaneously for achieving fully parallel test of RF device.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131650612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355742
Xiaoxiao Wang, M. Tehranipoor, R. Datta
As technology scales to 45nm and below, the deviation between predicted path delay using simulation and actual path delay on a manufactured chip increases. Hence, on-chip measurement architectures are now widely used due to their higher accuracy and lower cost compared to using external expensive testers. In this paper, we propose a novel path delay measurement architecture called Enhanced path-based ring oscillator (Path-RO) that takes into account variations. The proposed Enhanced Path-RO can accurately and quickly measure path delay on-chip under variations with nearly no impact on functional data path. Enhanced Path-RO is perfectly suitable for fast and accurate speed binning as well by targeting speed paths on-chip even in presence of clock skew. Simulation results under variations collected by the Enhanced Path-RO inserted into ITC'99 b19 circuit demonstrate its high accuracy and efficiency.
{"title":"A novel architecture for on-chip path delay measurement","authors":"Xiaoxiao Wang, M. Tehranipoor, R. Datta","doi":"10.1109/TEST.2009.5355742","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355742","url":null,"abstract":"As technology scales to 45nm and below, the deviation between predicted path delay using simulation and actual path delay on a manufactured chip increases. Hence, on-chip measurement architectures are now widely used due to their higher accuracy and lower cost compared to using external expensive testers. In this paper, we propose a novel path delay measurement architecture called Enhanced path-based ring oscillator (Path-RO) that takes into account variations. The proposed Enhanced Path-RO can accurately and quickly measure path delay on-chip under variations with nearly no impact on functional data path. Enhanced Path-RO is perfectly suitable for fast and accurate speed binning as well by targeting speed paths on-chip even in presence of clock skew. Simulation results under variations collected by the Enhanced Path-RO inserted into ITC'99 b19 circuit demonstrate its high accuracy and efficiency.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116827514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355904
Francisco Torres, Rohit Srivastava, Javier Ruiz, Charles H.-P. Wen, Mrinal Bose, J. Bhadra
Reuse of System-on-Chip (SoC) verification stimuli across various design models is a challenging problem. However, if used effectively, it significantly reduces verification time and quickly increases confidence in the robustness of a design. We use pseudo-random stimuli to drive tests on an SoC using simulation BFMs and reuse them on emulation-BFMs. Initial results on a Power Architecture™ Technology-based SoC demonstrate about a 100x speedup on the emulator vis-à-vis the simulator.
{"title":"Portable simulation/emulation stimulus on an industrial-strength SoC","authors":"Francisco Torres, Rohit Srivastava, Javier Ruiz, Charles H.-P. Wen, Mrinal Bose, J. Bhadra","doi":"10.1109/TEST.2009.5355904","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355904","url":null,"abstract":"Reuse of System-on-Chip (SoC) verification stimuli across various design models is a challenging problem. However, if used effectively, it significantly reduces verification time and quickly increases confidence in the robustness of a design. We use pseudo-random stimuli to drive tests on an SoC using simulation BFMs and reuse them on emulation-BFMs. Initial results on a Power Architecture™ Technology-based SoC demonstrate about a 100x speedup on the emulator vis-à-vis the simulator.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115651244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355620
Janine Chen, Li-C. Wang, Po-Hsien Chang, Jing Zeng, Stanley Yu, Michael Mateja
The question of whether or not structural test measurements can be used to predict functional or system Fmax, has been studied for many years. This paper presents a data learning approach to study the question. Given Fmax values and structural delay measurements on a set of sample chips, we propose a method called conformity check whose goal is to select a subset of conformal samples such that a more reliable predictor can be built on. Our predictor consists of two models, a conformal model that decides on a given chip if its Fmax is predictable or not, and a prediction model that outputs the predicted Fmax based on results obtained from structural test measurements. We explain the data learning methodology and study various data learning techniques using frequency data collected on a high-performance microprocessor design.
{"title":"Data learning techniques and methodology for Fmax prediction","authors":"Janine Chen, Li-C. Wang, Po-Hsien Chang, Jing Zeng, Stanley Yu, Michael Mateja","doi":"10.1109/TEST.2009.5355620","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355620","url":null,"abstract":"The question of whether or not structural test measurements can be used to predict functional or system Fmax, has been studied for many years. This paper presents a data learning approach to study the question. Given Fmax values and structural delay measurements on a set of sample chips, we propose a method called conformity check whose goal is to select a subset of conformal samples such that a more reliable predictor can be built on. Our predictor consists of two models, a conformal model that decides on a given chip if its Fmax is predictable or not, and a prediction model that outputs the predicted Fmax based on results obtained from structural test measurements. We explain the data learning methodology and study various data learning techniques using frequency data collected on a high-performance microprocessor design.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114316154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355599
P. Ahuja
We have found that logic, design, and architectural bugs do not control the difficulty of bringing up a new microprocessor. Anything that can be reproduced in simulation can be fixed rapidly. The bugs that are hard to reproduce, which occur sporadically, and which don't fail consistently with voltage or temperature are the ones we remember. We describe one such bug, called SSEL for the system error message it caused, which one test engineer said was the strangest bug seen in his long career. It was limited to only one output, and did not occur in other similar outputs. It never failed on a consistent schedule. Failure rates showed a strong correlation with wafer location. Finally, one of the best system level tests for the failure was letting the system sit at the command line prompt, since the failure was not related to system activity. We will describe the characteristics of the bug, the results of experiments with it, our mitigation strategy, our fix, and the root cause. Reliability and availability features built into our servers allowed us to protect customers from the impact of the problem. We will show a large amount of real data from the effort to find the cause of this problem.
{"title":"Post-silicon validation: It's the unique fails that hurt you","authors":"P. Ahuja","doi":"10.1109/TEST.2009.5355599","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355599","url":null,"abstract":"We have found that logic, design, and architectural bugs do not control the difficulty of bringing up a new microprocessor. Anything that can be reproduced in simulation can be fixed rapidly. The bugs that are hard to reproduce, which occur sporadically, and which don't fail consistently with voltage or temperature are the ones we remember. We describe one such bug, called SSEL for the system error message it caused, which one test engineer said was the strangest bug seen in his long career. It was limited to only one output, and did not occur in other similar outputs. It never failed on a consistent schedule. Failure rates showed a strong correlation with wafer location. Finally, one of the best system level tests for the failure was letting the system sit at the command line prompt, since the failure was not related to system activity. We will describe the characteristics of the bug, the results of experiments with it, our mitigation strategy, our fix, and the root cause. Reliability and availability features built into our servers allowed us to protect customers from the impact of the problem. We will show a large amount of real data from the effort to find the cause of this problem.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128118369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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