Pub Date : 2009-11-01DOI: 10.1109/TEST.2009.5355548
F. Yuan, Q. Xu
With technology scaling, the discrepancy between integrated circuits' activities in normal functional mode and that in structural test mode has an increasing adverse impact on the effectiveness of manufacturing test. By identifying functionally unreachable states in the circuit and avoiding them during the test generation process, pseudo-functional testing is an effective technique to address this problem. Pseudo-functional patterns, however, feature much less don't-care bits when compared to conventional structural patterns, making them less friendly to test compression techniques. In this paper, we propose novel solutions to address the above problem, which facilitate to apply pseudo-functional testing in linear decompressor-based test compression environment. Experimental results on ISCAS'89 benchmark circuits demonstrate the effectiveness of the proposed methodology.
{"title":"Compression-aware pseudo-functional testing","authors":"F. Yuan, Q. Xu","doi":"10.1109/TEST.2009.5355548","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355548","url":null,"abstract":"With technology scaling, the discrepancy between integrated circuits' activities in normal functional mode and that in structural test mode has an increasing adverse impact on the effectiveness of manufacturing test. By identifying functionally unreachable states in the circuit and avoiding them during the test generation process, pseudo-functional testing is an effective technique to address this problem. Pseudo-functional patterns, however, feature much less don't-care bits when compared to conventional structural patterns, making them less friendly to test compression techniques. In this paper, we propose novel solutions to address the above problem, which facilitate to apply pseudo-functional testing in linear decompressor-based test compression environment. Experimental results on ISCAS'89 benchmark circuits demonstrate the effectiveness of the proposed methodology.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122426487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-08DOI: 10.1109/TEST.2008.4700553
G. Giles, Jing Wang, Anuja Sehgal, K. J. Balakrishnan, James Wingfield
A new test access mechanism (TAM) for multiple identical embedded cores is proposed. It exploits the identical nature of the cores and modular pipelined circuitry to provide scalable and flexible capabilities to make tradeoffs between test time and diagnosis over the manufacturing maturity cycle from low-yield initial production to high-yield, high-volume production. The test throughput gains of various configurations of this TAM are analyzed. Forward and reverse protocol translations for core patterns applied with this TAM are described.
{"title":"Test access mechanism for multiple identical cores","authors":"G. Giles, Jing Wang, Anuja Sehgal, K. J. Balakrishnan, James Wingfield","doi":"10.1109/TEST.2008.4700553","DOIUrl":"https://doi.org/10.1109/TEST.2008.4700553","url":null,"abstract":"A new test access mechanism (TAM) for multiple identical embedded cores is proposed. It exploits the identical nature of the cores and modular pipelined circuitry to provide scalable and flexible capabilities to make tradeoffs between test time and diagnosis over the manufacturing maturity cycle from low-yield initial production to high-yield, high-volume production. The test throughput gains of various configurations of this TAM are analyzed. Forward and reverse protocol translations for core patterns applied with this TAM are described.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131915404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/test.2009.5355606
P. Ahuja
We have found that logic, design, and architectural bugs do not control the difficulty of bringing up a new microprocessor. Anything that can be reproduced in simulation can be fixed rapidly. The bugs that are hard to reproduce, which occur sporadically, and which don't fail consistently with voltage or temperature are the ones we remember. We describe one such bug, called SSEL for the system error message it caused, which one test engineer said was the strangest bug seen in his long career. It was limited to only one output, and did not occur in other similar outputs. It never failed on a consistent schedule. Failure rates showed a strong correlation with wafer location. Finally, one of the best system level tests for the failure was letting the system sit at the command line prompt, since the failure was not related to system activity. We will describe the characteristics of the bug, the results of experiments with it, our mitigation strategy, our fix, and the root cause. Reliability and availability features built into our servers allowed us to protect customers from the impact of the problem. We will show a large amount of real data from the effort to find the cause of this problem.
{"title":"Post-silicon validation: It's the unique fails that hurt you","authors":"P. Ahuja","doi":"10.1109/test.2009.5355606","DOIUrl":"https://doi.org/10.1109/test.2009.5355606","url":null,"abstract":"We have found that logic, design, and architectural bugs do not control the difficulty of bringing up a new microprocessor. Anything that can be reproduced in simulation can be fixed rapidly. The bugs that are hard to reproduce, which occur sporadically, and which don't fail consistently with voltage or temperature are the ones we remember. We describe one such bug, called SSEL for the system error message it caused, which one test engineer said was the strangest bug seen in his long career. It was limited to only one output, and did not occur in other similar outputs. It never failed on a consistent schedule. Failure rates showed a strong correlation with wafer location. Finally, one of the best system level tests for the failure was letting the system sit at the command line prompt, since the failure was not related to system activity. We will describe the characteristics of the bug, the results of experiments with it, our mitigation strategy, our fix, and the root cause. Reliability and availability features built into our servers allowed us to protect customers from the impact of the problem. We will show a large amount of real data from the effort to find the cause of this problem.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126159207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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