Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355810
Jim Vana, Alexander Barr, Richard Scherer, A. Joshi
This poster describes High Speed I/O Test Cable Interfaces for Next Generation Multi-Gigabit Serial Protocols such as PCI-Express incorporating 3M™ Shielded Controlled Impedance ( SCI ) Connector Systems, Spring Probe board interfaces and low loss Twinaxial Cable Assemblies with performance capabilities up to 12 Gbps.
{"title":"High Speed I/O Test Cable Assembly Interfaces for Next Generation Multi-Gigabit Serial Protocols","authors":"Jim Vana, Alexander Barr, Richard Scherer, A. Joshi","doi":"10.1109/TEST.2009.5355810","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355810","url":null,"abstract":"This poster describes High Speed I/O Test Cable Interfaces for Next Generation Multi-Gigabit Serial Protocols such as PCI-Express incorporating 3M™ Shielded Controlled Impedance ( SCI ) Connector Systems, Spring Probe board interfaces and low loss Twinaxial Cable Assemblies with performance capabilities up to 12 Gbps.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125338678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355667
J. Nejedlo, R. Khanna
Third generation Intel® IBIST (IBIST) is the first full featured edition of what was originally envisioned in 1999. The objective was to create a standard infrastructure for validating, debugging, and testing high speed IOs (Input/Output) which could be supported by a common software toolset. This vision was realized in 2009 on Intel products. The IBIST methodology has become a standard at Intel. Today, IBIST is utilized from the very beginning of the product verification including initial power-on silicon debug. It a staple throughout the back-end product validation process and is also utilized in end-customer validation and high volume testing. Intel's platform Reliability, Availability, Serviceability(collectively referred to as RAS) architecture exploits the technology on a number of fronts as well. The content of this paper includes an overview of the problems which mandated this paradigm shift away from the historical IO testing methodologies, an IBIST architectural overview, and the key application spaces addressed by this technology.
{"title":"Intel® IBIST, the full vision realized","authors":"J. Nejedlo, R. Khanna","doi":"10.1109/TEST.2009.5355667","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355667","url":null,"abstract":"Third generation Intel® IBIST (IBIST) is the first full featured edition of what was originally envisioned in 1999. The objective was to create a standard infrastructure for validating, debugging, and testing high speed IOs (Input/Output) which could be supported by a common software toolset. This vision was realized in 2009 on Intel products. The IBIST methodology has become a standard at Intel. Today, IBIST is utilized from the very beginning of the product verification including initial power-on silicon debug. It a staple throughout the back-end product validation process and is also utilized in end-customer validation and high volume testing. Intel's platform Reliability, Availability, Serviceability(collectively referred to as RAS) architecture exploits the technology on a number of fronts as well. The content of this paper includes an overview of the problems which mandated this paradigm shift away from the historical IO testing methodologies, an IBIST architectural overview, and the key application spaces addressed by this technology.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115966654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355644
Narendra Devta-Prasanna, S. Goel, A. Gunda, Mark Ward, P. Krishnamurthy
Small delay defect (SDD) testing is expected to become more prevalent as technology nodes continue to shrink and design frequencies continue to increase. In this paper, we critically examine previously published methods for evaluating SDD coverage and identify their shortcomings as an accurate and practical coverage metric. We propose an accurate method for measuring the coverage of small delay defects by any given pattern set. We demonstrate that the proposed metric overcomes the identified shortcomings of previously published approaches. For several ISCAS and industrial circuits, we generate test patterns and compare their SDD coverage values using different methods. Experimental results also demonstrate that the proposed method is several times faster to compute. Finally, we evaluate different testing strategies for screening small delay defects.
{"title":"Accurate measurement of small delay defect coverage of test patterns","authors":"Narendra Devta-Prasanna, S. Goel, A. Gunda, Mark Ward, P. Krishnamurthy","doi":"10.1109/TEST.2009.5355644","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355644","url":null,"abstract":"Small delay defect (SDD) testing is expected to become more prevalent as technology nodes continue to shrink and design frequencies continue to increase. In this paper, we critically examine previously published methods for evaluating SDD coverage and identify their shortcomings as an accurate and practical coverage metric. We propose an accurate method for measuring the coverage of small delay defects by any given pattern set. We demonstrate that the proposed metric overcomes the identified shortcomings of previously published approaches. For several ISCAS and industrial circuits, we generate test patterns and compare their SDD coverage values using different methods. Experimental results also demonstrate that the proposed method is several times faster to compute. Finally, we evaluate different testing strategies for screening small delay defects.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127085186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355662
S. Sunter, K. Parker
As printed circuit board dimensions continue to decrease, in-circuit tester (ICT) access using a bed-of-nails plus capacitive sensing is increasingly difficult. Stimulus injection using IEEE 1149.1 Boundary-Scan has been proposed as an alternative, but without modification it has significant limitations. An IEEE-supported Working Group is developing an extension entitled, “1149.8.1 - Draft Standard for Boundary-Scan-Based Stimulus of Interconnects to Passive and/or Active Components”. It would add capabilities to 1149.1 that facilitate testing of connections to non-Boundary-Scan components, especially passive components and vacant connectors that are connected to devices equipped with 1149.8.1 facilities. This paper describes existing limitations, IC design changes that would address them, some experimental results, and a summary of how this proposed standard is evolving.
{"title":"Testing bridges to nowhere - combining Boundary Scan and capacitive sensing","authors":"S. Sunter, K. Parker","doi":"10.1109/TEST.2009.5355662","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355662","url":null,"abstract":"As printed circuit board dimensions continue to decrease, in-circuit tester (ICT) access using a bed-of-nails plus capacitive sensing is increasingly difficult. Stimulus injection using IEEE 1149.1 Boundary-Scan has been proposed as an alternative, but without modification it has significant limitations. An IEEE-supported Working Group is developing an extension entitled, “1149.8.1 - Draft Standard for Boundary-Scan-Based Stimulus of Interconnects to Passive and/or Active Components”. It would add capabilities to 1149.1 that facilitate testing of connections to non-Boundary-Scan components, especially passive components and vacant connectors that are connected to devices equipped with 1149.8.1 facilities. This paper describes existing limitations, IC design changes that would address them, some experimental results, and a summary of how this proposed standard is evolving.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132507273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355633
Po-Han Wu, J. Rau
In this paper, new compression architecture is proposed for multiple scan-chains. We use buffers to hold back data, and use read enable signals to filter useless data. We use only four extra channels (which is less than [1]) and less hardware for largest ISCAS'89 circuits to reduce test data volume and shift-in power. The average of peak/WTC shift-in turns to 3x/6.6x, after comparing [1] and our method. The average of improvement/ hardware is 16%/6%.
{"title":"Low power multi-chains encoding scheme for SoC in low-cost environment","authors":"Po-Han Wu, J. Rau","doi":"10.1109/TEST.2009.5355633","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355633","url":null,"abstract":"In this paper, new compression architecture is proposed for multiple scan-chains. We use buffers to hold back data, and use read enable signals to filter useless data. We use only four extra channels (which is less than [1]) and less hardware for largest ISCAS'89 circuits to reduce test data volume and shift-in power. The average of peak/WTC shift-in turns to 3x/6.6x, after comparing [1] and our method. The average of improvement/ hardware is 16%/6%.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129860230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355747
Haoxing Ren, M. P. Kusko, Victor N. Kravets, Rona Yaari
This paper presents a new approach to improve random test coverage during physical synthesis for high performance design. This new approach performs test point insertion (TPI) to improve testability of random resistant nets. Conventional test point insertion approaches add extra registers either as control points or observation points to improve controllability or observability. However, adding extra registers has many disadvantages in high performance design. It might degrade the design performance in term of power and timing. It might also end up with even worse testability. The new approach does not add any registers; instead it only uses existing signals as test points. The test points are selected from logic paths with the most timing slack and physical placement proximity. This saves silicon area, reduces power consumption, and minimizes the design changes. The new approach also automates the test insertion process by integrating it in the physical synthesis flow. The integration helps reduce design closure turn around time significantly. Production results show nearly zero performance degradation from this approach and better testability improvement as compared to a manual test point insertion approach. Furthermore, this paper proposes a novel idea of exploiting unreachable states for test point insertion. Preliminary results on this idea are also given.
{"title":"Low cost test point insertion without using extra registers for high performance design","authors":"Haoxing Ren, M. P. Kusko, Victor N. Kravets, Rona Yaari","doi":"10.1109/TEST.2009.5355747","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355747","url":null,"abstract":"This paper presents a new approach to improve random test coverage during physical synthesis for high performance design. This new approach performs test point insertion (TPI) to improve testability of random resistant nets. Conventional test point insertion approaches add extra registers either as control points or observation points to improve controllability or observability. However, adding extra registers has many disadvantages in high performance design. It might degrade the design performance in term of power and timing. It might also end up with even worse testability. The new approach does not add any registers; instead it only uses existing signals as test points. The test points are selected from logic paths with the most timing slack and physical placement proximity. This saves silicon area, reduces power consumption, and minimizes the design changes. The new approach also automates the test insertion process by integrating it in the physical synthesis flow. The integration helps reduce design closure turn around time significantly. Production results show nearly zero performance degradation from this approach and better testability improvement as compared to a manual test point insertion approach. Furthermore, this paper proposes a novel idea of exploiting unreachable states for test point insertion. Preliminary results on this idea are also given.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128969570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355688
Joon-Sung Yang, B. Nadeau-Dostie, N. Touba
This paper presents a novel method for reducing the area overhead introduced by test point insertion. Test point locations are calculated as usual using a commercial tool. However, the proposed method uses functional flip-flops to drive control test points instead of test-dedicated flip-flops. Logic cone analysis that considers the distance and path inversion parity from candidate functional flip-flops to each control point is used to select an appropriate functional flip-flop to drive the control point which avoids adding additional timing constraints. Reconvergence is also checked to avoid degrading the testability. Experimental results indicate that the proposed method significantly reduces test point area overhead and achieves essentially the same fault coverage as the implementations using dedicated flip-flops driving the control points.
{"title":"Test point insertion using functional flip-flops to drive control points","authors":"Joon-Sung Yang, B. Nadeau-Dostie, N. Touba","doi":"10.1109/TEST.2009.5355688","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355688","url":null,"abstract":"This paper presents a novel method for reducing the area overhead introduced by test point insertion. Test point locations are calculated as usual using a commercial tool. However, the proposed method uses functional flip-flops to drive control test points instead of test-dedicated flip-flops. Logic cone analysis that considers the distance and path inversion parity from candidate functional flip-flops to each control point is used to select an appropriate functional flip-flop to drive the control point which avoids adding additional timing constraints. Reconvergence is also checked to avoid degrading the testability. Experimental results indicate that the proposed method significantly reduces test point area overhead and achieves essentially the same fault coverage as the implementations using dedicated flip-flops driving the control points.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127797479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355605
Baosheng Wang, G. Giles, Jayalakshmi Rajaraman, K. Sobti, Derrick Losli, D. Elvey, J. Fitzgerald, R. Walther, J. Rearick
Power-only defects do not cause logical failures in a chip but induce more power consumption. For battery-driven semiconductor chips and others with military-level quality requirements, power-only defects have to be screened out during manufacturing test. To reduce the associated test cost, structural test of those defects is a must. With a dedicated example, this paper demonstrates two methods to structurally detect such defects, i.e., testing them along with regular ATPG vectors and creating a special test mode for detection. This paper also compares the two proposals based on different tradeoff requirements. Finally, it summarizes general criteria for selecting structural test methods for detecting those power-only defects.
{"title":"Structural test of power-only defects: ATPG or ad-hoc?","authors":"Baosheng Wang, G. Giles, Jayalakshmi Rajaraman, K. Sobti, Derrick Losli, D. Elvey, J. Fitzgerald, R. Walther, J. Rearick","doi":"10.1109/TEST.2009.5355605","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355605","url":null,"abstract":"Power-only defects do not cause logical failures in a chip but induce more power consumption. For battery-driven semiconductor chips and others with military-level quality requirements, power-only defects have to be screened out during manufacturing test. To reduce the associated test cost, structural test of those defects is a must. With a dedicated example, this paper demonstrates two methods to structurally detect such defects, i.e., testing them along with regular ATPG vectors and creating a special test mode for detection. This paper also compares the two proposals based on different tradeoff requirements. Finally, it summarizes general criteria for selecting structural test methods for detecting those power-only defects.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133075118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355898
Pierre-Didier Mauroux, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, B. Godard
Embedded flash memories are dominated by the NOR architecture but NAND is becoming more and more adopted due to its high storage capacity. This paper presents a preliminary study on actual defects in NAND array.
{"title":"NAND flash testing: A preliminary study on actual defects","authors":"Pierre-Didier Mauroux, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, B. Godard","doi":"10.1109/TEST.2009.5355898","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355898","url":null,"abstract":"Embedded flash memories are dominated by the NOR architecture but NAND is becoming more and more adopted due to its high storage capacity. This paper presents a preliminary study on actual defects in NAND array.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130751445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355530
N. Mukherjee, Artur Pogiel, J. Rajski, J. Tyszer
The paper presents a BIST-based scheme for fault diagnosis that can be used to identify permanent and address independent failures in embedded read-only memories. The proposed approach offers a simple test flow and does not require intensive interactions between a BIST controller and a tester. The scheme rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of time-related faults.
{"title":"Fault diagnosis for embedded read-only memories","authors":"N. Mukherjee, Artur Pogiel, J. Rajski, J. Tyszer","doi":"10.1109/TEST.2009.5355530","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355530","url":null,"abstract":"The paper presents a BIST-based scheme for fault diagnosis that can be used to identify permanent and address independent failures in embedded read-only memories. The proposed approach offers a simple test flow and does not require intensive interactions between a BIST controller and a tester. The scheme rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of time-related faults.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115681819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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