Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355728
Rama Gudavalli, W. R. Daasch, P. Nigh, D. Heaberlin
This paper presents a method using only the rank of the measurements to separate a part's elevated response to parametric tests from its non-elevated response. The effectiveness of the proposed method is verified on the 130nm ASIC. Good die responses are correlated for same parametric tests at different conditions such as temperature, voltage and or other stress. Nonparametric correlation methods are used to calculate the intra-die correlation. When intra-die correlation is found to be low the elevated vectors that lower correlation are extracted and input to IDDQ-based diagnostic tools. Monte-Carlo simulations are described to obtain confidence bounds of the correlation for good die test response.
{"title":"Application of non-parametric statistics of the parametric response for defect diagnosis","authors":"Rama Gudavalli, W. R. Daasch, P. Nigh, D. Heaberlin","doi":"10.1109/TEST.2009.5355728","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355728","url":null,"abstract":"This paper presents a method using only the rank of the measurements to separate a part's elevated response to parametric tests from its non-elevated response. The effectiveness of the proposed method is verified on the 130nm ASIC. Good die responses are correlated for same parametric tests at different conditions such as temperature, voltage and or other stress. Nonparametric correlation methods are used to calculate the intra-die correlation. When intra-die correlation is found to be low the elevated vectors that lower correlation are extracted and input to IDDQ-based diagnostic tools. Monte-Carlo simulations are described to obtain confidence bounds of the correlation for good die test response.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114495543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355681
Y. Higami, Yosuke Kurose, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, T. Aikyo, Y. Takamatsu
This paper presents a diagnostic test generation method for transition faults. As two consecutive vectors application mechanism, launch on capture test is considered. The proposed algorithm generates test vectors for given fault pairs using a stuck-at ATPG tool so that they are distinguished. If a given fault pair is indistinguishable, it is identified. Therefore the proposed algorithm provides a complete test generation regarding the distinguishability. The conditions for distinguishing a fault pair are carefully considered, and they are transformed into the conditions of the detection of a stuck-at fault, and some additional logic are inserted in a CUT for the test generation. Experimental results show that the proposed method can generate test vectors for distinguishing the fault pairs that are not distinguished by commercial tools, and also identify all the indistinguishable fault pairs.
{"title":"Diagnostic test generation for transition faults using a stuck-at ATPG tool","authors":"Y. Higami, Yosuke Kurose, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, T. Aikyo, Y. Takamatsu","doi":"10.1109/TEST.2009.5355681","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355681","url":null,"abstract":"This paper presents a diagnostic test generation method for transition faults. As two consecutive vectors application mechanism, launch on capture test is considered. The proposed algorithm generates test vectors for given fault pairs using a stuck-at ATPG tool so that they are distinguished. If a given fault pair is indistinguishable, it is identified. Therefore the proposed algorithm provides a complete test generation regarding the distinguishability. The conditions for distinguishing a fault pair are carefully considered, and they are transformed into the conditions of the detection of a stuck-at fault, and some additional logic are inserted in a CUT for the test generation. Experimental results show that the proposed method can generate test vectors for distinguishing the fault pairs that are not distinguished by commercial tools, and also identify all the indistinguishable fault pairs.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121952162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355767
H. Okawara
In order to clear regulations on electro-magnetic interference (EMI), the serial ATA (SATA) standard recommends spread spectrum clocking (SSC) to reduce the significant peak in the spectrum of system clocks. Although testing of high-speed serial interface primarily addressed using digital testers, a SSC applied waveform is not an easy task for digital resources to generate and analyze, while analog resources in mixed signal testers can easily take care of such signals. The purpose of this work is to establish methodologies to generate a SSC applied data stream by using an arbitrary waveform generator (AWG) and to analyze the SSC frequency trend by using a waveform sampler. The AWG generates 750MHz clock, align primitives and pseudo random binary sequence (PRBS) stream with SSC. The sampler analyzes the clock and the align primitives reconstructing the SSC frequency trend.
{"title":"SSC applied serial ATA signal generation and analysis by analog tester resources","authors":"H. Okawara","doi":"10.1109/TEST.2009.5355767","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355767","url":null,"abstract":"In order to clear regulations on electro-magnetic interference (EMI), the serial ATA (SATA) standard recommends spread spectrum clocking (SSC) to reduce the significant peak in the spectrum of system clocks. Although testing of high-speed serial interface primarily addressed using digital testers, a SSC applied waveform is not an easy task for digital resources to generate and analyze, while analog resources in mixed signal testers can easily take care of such signals. The purpose of this work is to establish methodologies to generate a SSC applied data stream by using an arbitrary waveform generator (AWG) and to analyze the SSC frequency trend by using a waveform sampler. The AWG generates 750MHz clock, align primitives and pseudo random binary sequence (PRBS) stream with SSC. The sampler analyzes the clock and the align primitives reconstructing the SSC frequency trend.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130344071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355676
Min Li, M. Hsiao
In this paper, a novel heuristic for abstraction-guided state justification is proposed based on ant colony optimization (ACO). A probabilistic state transition model is developed to help formulate the state justification problem as a searching scheme of artificial ants. The amount of pheromone left by the ants is directly proportional to the quality of the search so that it can serve as an effective guidance for the search. In addition, the intelligence based on the collective behavior is capable of avoiding critical dead-end states as well as fast convergence to the target state. Experimental results demonstrated that our approach is superior in reaching hard-to-reach states in sequential circuit compared to other methods.
{"title":"An ant colony optimization technique for abstraction-guided state justification","authors":"Min Li, M. Hsiao","doi":"10.1109/TEST.2009.5355676","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355676","url":null,"abstract":"In this paper, a novel heuristic for abstraction-guided state justification is proposed based on ant colony optimization (ACO). A probabilistic state transition model is developed to help formulate the state justification problem as a searching scheme of artificial ants. The amount of pheromone left by the ants is directly proportional to the quality of the search so that it can serve as an effective guidance for the search. In addition, the intelligence based on the collective behavior is capable of avoiding critical dead-end states as well as fast convergence to the target state. Experimental results demonstrated that our approach is superior in reaching hard-to-reach states in sequential circuit compared to other methods.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129892362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355708
N. Callegari, Li-C. Wang, P. Bastani
In test and diagnosis, one often runs into the situation that after analyzing a set of samples, a few of these samples are identified as being “special”. Then, in a large population of samples one desires to identify all samples that are “similar” to the special samples. The process is called a similarity search. This paper presents a feature based similarity search approach and discusses three potential methods to implement this approach. These methods are (1) building a model to capture the characteristics of the non-special samples, (2) building a model to capture the characteristics of the special samples, and (3) searching for the hypotheses to explain individually why each sample is special. We apply similarity search to the speedpath analysis problem where special samples are special paths that limit the performance of silicon chips. The goal is to identify more paths in the design with similar characteristics to the speedpaths. The effectivenesses of the three methods are analyzed based on speedpath data collected from a high-performance microprocessor.
{"title":"Feature based similarity search with application to speedpath analysis","authors":"N. Callegari, Li-C. Wang, P. Bastani","doi":"10.1109/TEST.2009.5355708","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355708","url":null,"abstract":"In test and diagnosis, one often runs into the situation that after analyzing a set of samples, a few of these samples are identified as being “special”. Then, in a large population of samples one desires to identify all samples that are “similar” to the special samples. The process is called a similarity search. This paper presents a feature based similarity search approach and discusses three potential methods to implement this approach. These methods are (1) building a model to capture the characteristics of the non-special samples, (2) building a model to capture the characteristics of the special samples, and (3) searching for the hypotheses to explain individually why each sample is special. We apply similarity search to the speedpath analysis problem where special samples are special paths that limit the performance of silicon chips. The goal is to identify more paths in the design with similar characteristics to the speedpaths. The effectivenesses of the three methods are analyzed based on speedpath data collected from a high-performance microprocessor.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116962671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355713
Chia-Ling Chang, Charles H.-P. Wen, J. Bhadra
A learning-and-filtering algorithm is proposed to uncover cross-timeframe state-pair constraints for speeding up SAT solving of bounded sequential equivalence checking (BSEC) problems. First, relaxed Boolean functions for flip-flop states at respective timeframes are learned from a small number of simulation data to derive the initial set of the state-pair candidates. Next, each candidate is examined and removed if both values in such a candidate have coordinately appeared during the simulation. Then, the validity of the remaining candidates is checked against the corresponding augmented circuit. Last, only the true constraints are annotated to the BSEC problems to facilitate SAT solving. All benchmark circuits are synthesized under 10 configurations to produce different BSEC problems. Experimental results show that the new SAT solving runs 2-order faster in average compared to using MiniSAT 2.0 only. Moreover, given a time bound, the total number of timeframes can increase by 8X-20X on 4 larger circuits after applying the proposed framework.
{"title":"Speeding up bounded sequential equivalence checking with cross-timeframe state-pair constraints from data learning","authors":"Chia-Ling Chang, Charles H.-P. Wen, J. Bhadra","doi":"10.1109/TEST.2009.5355713","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355713","url":null,"abstract":"A learning-and-filtering algorithm is proposed to uncover cross-timeframe state-pair constraints for speeding up SAT solving of bounded sequential equivalence checking (BSEC) problems. First, relaxed Boolean functions for flip-flop states at respective timeframes are learned from a small number of simulation data to derive the initial set of the state-pair candidates. Next, each candidate is examined and removed if both values in such a candidate have coordinately appeared during the simulation. Then, the validity of the remaining candidates is checked against the corresponding augmented circuit. Last, only the true constraints are annotated to the BSEC problems to facilitate SAT solving. All benchmark circuits are synthesized under 10 configurations to produce different BSEC problems. Experimental results show that the new SAT solving runs 2-order faster in average compared to using MiniSAT 2.0 only. Moreover, given a time bound, the total number of timeframes can increase by 8X-20X on 4 larger circuits after applying the proposed framework.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129172355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-18DOI: 10.1109/TEST.2009.5355741
F. Hapke, Rene Krenz-Baath, Andreas Glowatz, J. Schlöffel, H. Hashempour, S. Eichenberger, C. Hora, Dan Adolfsson
Industry is facing increasingly tougher quality requirements for more complex ICs. To meet these quality requirements we need to improve the defect coverage. This paper presents a new methodology to significantly increase the defect coverage of the test patterns generated by ATPG tools. The fault model used during the ATPG is enhanced to directly target layout-based intra-cell faults. In contrast to previous techniques, such as Gate-Exhaustive, N-Detect, or Embedded-Multi-Detect, which either are too complex for real-world designs or merely improve the probability of detecting intra-cell defects, the new approach targets the actual root causes of intra-cell defects. The newly proposed Cell-Aware-methodology has been evaluated for 90nm and 65nm technologies on 1671 library cells and on 10 real industrial designs with up to 50 million faults. The experimental results show an average increase of 1.2% in defect coverage and a reduction of 420ppm in escape rate for a 50mm2 design.
{"title":"Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs","authors":"F. Hapke, Rene Krenz-Baath, Andreas Glowatz, J. Schlöffel, H. Hashempour, S. Eichenberger, C. Hora, Dan Adolfsson","doi":"10.1109/TEST.2009.5355741","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355741","url":null,"abstract":"Industry is facing increasingly tougher quality requirements for more complex ICs. To meet these quality requirements we need to improve the defect coverage. This paper presents a new methodology to significantly increase the defect coverage of the test patterns generated by ATPG tools. The fault model used during the ATPG is enhanced to directly target layout-based intra-cell faults. In contrast to previous techniques, such as Gate-Exhaustive, N-Detect, or Embedded-Multi-Detect, which either are too complex for real-world designs or merely improve the probability of detecting intra-cell defects, the new approach targets the actual root causes of intra-cell defects. The newly proposed Cell-Aware-methodology has been evaluated for 90nm and 65nm technologies on 1671 library cells and on 10 real industrial designs with up to 50 million faults. The experimental results show an average increase of 1.2% in defect coverage and a reduction of 420ppm in escape rate for a 50mm2 design.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115011978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-11-01DOI: 10.1109/TEST.2009.5355748
Lin Huang, Q. Xu
Homogeneous manycore systems that contain a large number of structurally identical cores are emerging for tera-scale computation. To ensure the required quality and reliability of such complex integrated circuits before supplying them to final users, extensive manufacturing tests need to be conducted and the associated test cost can account for a great share of the total production cost. By introducing spare cores on-chip, the burn-in test time can be shortened and the defect coverage requirements for core tests can be also relaxed, without sacrificing quality of the shipped products. The above test cost reduction is likely to exceed/compensate the manufacturing cost of the extra cores, thus reducing the total production cost of manycore systems. We develop novel analytical models that capture the above tradeoff in this paper and we verify the effectiveness of the proposed test economics model for hypothetical manycore systems with various configurations.
{"title":"Test economics for homogeneous manycore systems","authors":"Lin Huang, Q. Xu","doi":"10.1109/TEST.2009.5355748","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355748","url":null,"abstract":"Homogeneous manycore systems that contain a large number of structurally identical cores are emerging for tera-scale computation. To ensure the required quality and reliability of such complex integrated circuits before supplying them to final users, extensive manufacturing tests need to be conducted and the associated test cost can account for a great share of the total production cost. By introducing spare cores on-chip, the burn-in test time can be shortened and the defect coverage requirements for core tests can be also relaxed, without sacrificing quality of the shipped products. The above test cost reduction is likely to exceed/compensate the manufacturing cost of the extra cores, thus reducing the total production cost of manycore systems. We develop novel analytical models that capture the above tradeoff in this paper and we verify the effectiveness of the proposed test economics model for hypothetical manycore systems with various configurations.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115512585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-11-01DOI: 10.1109/TEST.2009.5355831
Xiao Liu, Q. Xu
Debugging electrical errors is the most challenging problem during the post-silicon validation process. We propose an automated trace signal selection methodology to facilitate this task, in which, by analyzing the layout of the circuit and carefully selecting trace signals, designers are with high probability to identify electrical errors.
{"title":"Trace signal selection for debugging electrical errors in post-silicon validation","authors":"Xiao Liu, Q. Xu","doi":"10.1109/TEST.2009.5355831","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355831","url":null,"abstract":"Debugging electrical errors is the most challenging problem during the post-silicon validation process. We propose an automated trace signal selection methodology to facilitate this task, in which, by analyzing the layout of the circuit and carefully selecting trace signals, designers are with high probability to identify electrical errors.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114307297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-11-01DOI: 10.1109/TEST.2009.5355554
Xiao Liu, Q. Xu
Growing test data volume and excessive test power consumption in scan-based testing are both serious concerns for the semiconductor industry. Various test data compression (TDC) schemes and low-power X-filling techniques were proposed to address the above problems. These methods, however, exploit the very same “don't-care” bits in the test cubes to achieve different objectives and hence may contradict to each other. In this work, we propose a generic framework for test power reduction in linear decompressor-based test compression environment, which is able to effectively reduce shift-and capture-power simultaneously. Experimental results on benchmark circuits demonstrate that our proposed techniques significantly outperform existing solutions.
{"title":"On simultaneous shift- and capture-power reduction in linear decompressor-based test compression environment","authors":"Xiao Liu, Q. Xu","doi":"10.1109/TEST.2009.5355554","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355554","url":null,"abstract":"Growing test data volume and excessive test power consumption in scan-based testing are both serious concerns for the semiconductor industry. Various test data compression (TDC) schemes and low-power X-filling techniques were proposed to address the above problems. These methods, however, exploit the very same “don't-care” bits in the test cubes to achieve different objectives and hence may contradict to each other. In this work, we propose a generic framework for test power reduction in linear decompressor-based test compression environment, which is able to effectively reduce shift-and capture-power simultaneously. Experimental results on benchmark circuits demonstrate that our proposed techniques significantly outperform existing solutions.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133787111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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