Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635269
Z. Lu, Y. Ye
A simple analytical model of MOSFETs channel noise is presented by considering short-channel effect of deep submicron MOSFETs, such as mobility degradation, channel length modulation. The model is explicit functions of MOSFETs geometry and biasing conditions, and hence is useful for circuit design purposes. Simulating results derived by using different channel noise model are compared and discussed.
{"title":"A Simple Model for Channel Noise of Deep Submicron MOSFETs","authors":"Z. Lu, Y. Ye","doi":"10.1109/EDSSC.2005.1635269","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635269","url":null,"abstract":"A simple analytical model of MOSFETs channel noise is presented by considering short-channel effect of deep submicron MOSFETs, such as mobility degradation, channel length modulation. The model is explicit functions of MOSFETs geometry and biasing conditions, and hence is useful for circuit design purposes. Simulating results derived by using different channel noise model are compared and discussed.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114085968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635310
C. Wong, H. Wong, M. Chan, C. Kok, H. Chan
This work reports a method for reducing hydrogen content in silicon oxynitride film for integrated optical applications. The silicon oxynitride (SiON) films were grown by plasma enhanced chemical vapor deposition (PECVD) with N2O, NH3and SiH4as precursor gases. Using higher flow rate of SiH4and NH3, Si-rich oxynitride films with high refractive index were obtained. Detailed ellipsometry and Fourier transform infrared (FTIR) spectroscopy characterization of the as-deposited samples and samples with thermal oxidation/annealing were conducted. Results showed that the silicon oxynitride deposited with gas flow rates of NH3/N2O/SiH4=20/500/20 (sccm) has favorable properties for integrated waveguide applications. The refractive index of this layer is about 1.57 at 632.8 nm wavelength and the layer has a comparative low density of N-H bonds. With a high temperature annealing treatment in oxygen ambient, the hydrogen content in the as-deposited SiON film was reduced by 87% as results of excess silicon oxidation and hydrogen bond removal.
{"title":"Fabrication of Optical Waveguide using Silicon Oxynitride Prepared by Thermal Oxidation of Silicon Rich Silicon Nitride","authors":"C. Wong, H. Wong, M. Chan, C. Kok, H. Chan","doi":"10.1109/EDSSC.2005.1635310","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635310","url":null,"abstract":"This work reports a method for reducing hydrogen content in silicon oxynitride film for integrated optical applications. The silicon oxynitride (SiON) films were grown by plasma enhanced chemical vapor deposition (PECVD) with N2O, NH3and SiH4as precursor gases. Using higher flow rate of SiH4and NH3, Si-rich oxynitride films with high refractive index were obtained. Detailed ellipsometry and Fourier transform infrared (FTIR) spectroscopy characterization of the as-deposited samples and samples with thermal oxidation/annealing were conducted. Results showed that the silicon oxynitride deposited with gas flow rates of NH3/N2O/SiH4=20/500/20 (sccm) has favorable properties for integrated waveguide applications. The refractive index of this layer is about 1.57 at 632.8 nm wavelength and the layer has a comparative low density of N-H bonds. With a high temperature annealing treatment in oxygen ambient, the hydrogen content in the as-deposited SiON film was reduced by 87% as results of excess silicon oxidation and hydrogen bond removal.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121919146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635392
W. Lau, C. Eng, K.M. Tee, S. Siah, D. Vigar, Y.T. Kim, M. Lal, M. Bhat, L. Chan
Our observation is that both the oncurrent and off-current of state-of- the-art pchannel MOS transistors tend to become larger when the spacer becomes smaller. In this paper, we propose 2 mechanisms involved in this on-current and offcurrent increase due to a slightly smaller spacer. Mechanism A is a decrease in the effective channel length. Because of a TED/BED (transient enhanced diffusion/boron enhanced diffusion) mechanism, the deep p-type D/S implant closer to the channel region makes the p-type D/S extension implant to diffuse farther into the channel region, resulting in a smaller effective channel length Leff. Mechanism B is a decrease in the series resistance. The deep ptype D/S implant moving closer into the channel region also causes a reduction in the D/S series resistance Rseries*The smaller Leffand Rseriestogether can produce a higher on-current. The smaller Leff also causes a significant increase in off-current.
{"title":"A mechanism of increase in the on-current and offcurrent due to a slightly smaller spacer in state-of- the-art p-channel MOS transistors during manufacturing","authors":"W. Lau, C. Eng, K.M. Tee, S. Siah, D. Vigar, Y.T. Kim, M. Lal, M. Bhat, L. Chan","doi":"10.1109/EDSSC.2005.1635392","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635392","url":null,"abstract":"Our observation is that both the oncurrent and off-current of state-of- the-art pchannel MOS transistors tend to become larger when the spacer becomes smaller. In this paper, we propose 2 mechanisms involved in this on-current and offcurrent increase due to a slightly smaller spacer. Mechanism A is a decrease in the effective channel length. Because of a TED/BED (transient enhanced diffusion/boron enhanced diffusion) mechanism, the deep p-type D/S implant closer to the channel region makes the p-type D/S extension implant to diffuse farther into the channel region, resulting in a smaller effective channel length Leff. Mechanism B is a decrease in the series resistance. The deep ptype D/S implant moving closer into the channel region also causes a reduction in the D/S series resistance Rseries*The smaller Leffand Rseriestogether can produce a higher on-current. The smaller Leff also causes a significant increase in off-current.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130001440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635385
Kwen-Siong Chong, B. Gwee, J.S. Chang
In this paper, we investigate the energy efficacy of the asynchronous (async) logic over its synchronous (sync) counterpart in a 128-point FFT/IFFT processor for low voltage (1.1V to 1.4V) energy-critical medium-to-low speed applications including hearing aids. Both async and sync designs are implemented using the same process (0.35μm CMOS) and having the same computational complexity. For the latter sync design, we consider both scenarios with and without the clock gating approach. Our async design features ∼23% and ∼39% lower energy compared to its sync counterpart with and without the clock gating approach respectively.
{"title":"A Low-Energy Asynchronous FFT/IFFT Processor for Hearing Aid Applications","authors":"Kwen-Siong Chong, B. Gwee, J.S. Chang","doi":"10.1109/EDSSC.2005.1635385","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635385","url":null,"abstract":"In this paper, we investigate the energy efficacy of the asynchronous (async) logic over its synchronous (sync) counterpart in a 128-point FFT/IFFT processor for low voltage (1.1V to 1.4V) energy-critical medium-to-low speed applications including hearing aids. Both async and sync designs are implemented using the same process (0.35μm CMOS) and having the same computational complexity. For the latter sync design, we consider both scenarios with and without the clock gating approach. Our async design features ∼23% and ∼39% lower energy compared to its sync counterpart with and without the clock gating approach respectively.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131470097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635202
Yo‐Sheng Lin, Hsiao-Bin Liang, Hung-Wei Chiu, K. Liu, Hsin-Hong Wu, Shey-Shi Lu, Mou‐shiung Lin
In this paper, we analyze the effects of temperature (from -50°C to 200°C), substrate impedance, and substrate thickness on the noise figure (NF) and quality factor (Q-factor) performances of monolithic RF inductors on silicon. A 0.45 dB (from 0.6 dB to 0.15 dB) reduction in minimum NF (NFmin) at 10 GHz, a 308% (from 11.6 to 47.3) increase in Q-factor at 10 GHz, and a 4% (from 20 GHz to 20.8 GHz) improvement in self-resonant frequency (fSR) were obtained if post-process of proton implantation had been done. In addition, a 0.36 dB reduction (from 0.6 dB to 0.24 dB) in NFminat 10 GHz, a 176% (from 11.6 to 32) increase in Q-factor at 10 GHz, and a 30% (from 20 GHz to 26 GHz) improvement in fSRwere achieved if the silicon substrate was thinned down from 750 μm to 20 μm. This means both the proton implantation and the silicon substrate thinning are effective in improving the NF and Q-factor performances of monolithic RF inductors on silicon. The present analyses are helpful for RF designers to design high-performance fully on-chip LNAs and VCOs for single-chip receiver front-end or 3.1-10.6 GHz ultra-wide-band (UWB) system applications.
{"title":"Wideband Modeling of Temperature and Substrate Effects in RF Inductors on Silicon for 3.1-10.6 GHz UWB System Applications","authors":"Yo‐Sheng Lin, Hsiao-Bin Liang, Hung-Wei Chiu, K. Liu, Hsin-Hong Wu, Shey-Shi Lu, Mou‐shiung Lin","doi":"10.1109/EDSSC.2005.1635202","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635202","url":null,"abstract":"In this paper, we analyze the effects of temperature (from -50°C to 200°C), substrate impedance, and substrate thickness on the noise figure (NF) and quality factor (Q-factor) performances of monolithic RF inductors on silicon. A 0.45 dB (from 0.6 dB to 0.15 dB) reduction in minimum NF (NFmin) at 10 GHz, a 308% (from 11.6 to 47.3) increase in Q-factor at 10 GHz, and a 4% (from 20 GHz to 20.8 GHz) improvement in self-resonant frequency (fSR) were obtained if post-process of proton implantation had been done. In addition, a 0.36 dB reduction (from 0.6 dB to 0.24 dB) in NFminat 10 GHz, a 176% (from 11.6 to 32) increase in Q-factor at 10 GHz, and a 30% (from 20 GHz to 26 GHz) improvement in fSRwere achieved if the silicon substrate was thinned down from 750 μm to 20 μm. This means both the proton implantation and the silicon substrate thinning are effective in improving the NF and Q-factor performances of monolithic RF inductors on silicon. The present analyses are helpful for RF designers to design high-performance fully on-chip LNAs and VCOs for single-chip receiver front-end or 3.1-10.6 GHz ultra-wide-band (UWB) system applications.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133714183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635285
Q. Zhou, M. Yu, Y. Ye
An on-chip DC-DC voltage down converter (VDC) is proposed. The converter adopts a reference voltage generator (RVG) based on a new current source, and a differential-amplifier-based follower. The architecture of the proposed VDC is simple and can be fabricated by conventional CMOS technology. For 5-V to 3-V conversion, it has characteristics such as a temperature dependency of only 2.6mV°C and a voltage deviation within±0.52% for±10% variation of supply voltage. The output voltage is stabilized with ±3mV for load current varying from 0 to 100mA.
{"title":"On-Chip Voltage Down Converter with Precision CMOS Current Source for VLSI Chip","authors":"Q. Zhou, M. Yu, Y. Ye","doi":"10.1109/EDSSC.2005.1635285","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635285","url":null,"abstract":"An on-chip DC-DC voltage down converter (VDC) is proposed. The converter adopts a reference voltage generator (RVG) based on a new current source, and a differential-amplifier-based follower. The architecture of the proposed VDC is simple and can be fabricated by conventional CMOS technology. For 5-V to 3-V conversion, it has characteristics such as a temperature dependency of only 2.6mV°C and a voltage deviation within±0.52% for±10% variation of supply voltage. The output voltage is stabilized with ±3mV for load current varying from 0 to 100mA.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131388715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635217
C. C. Yeo, M. Lee, C. Liu, K.J. Choi, T. Lee, B. Cho
Metal gate/High-K stack CMOSFETs on ultra thin Ge epi channel on relaxed Si, capped with ultra thin Si (Si/Ge/Si substrate) were evaluated. NMOSFET shows enhanced mobility at low field while pMOSFET shows degraded peak mobility, with enhancement observed only at high field.
{"title":"Metal Gate/High-K Dielectric Stack on Si Cap/Ultra-Thin Pure Ge epi/Si Substrate","authors":"C. C. Yeo, M. Lee, C. Liu, K.J. Choi, T. Lee, B. Cho","doi":"10.1109/EDSSC.2005.1635217","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635217","url":null,"abstract":"Metal gate/High-K stack CMOSFETs on ultra thin Ge epi channel on relaxed Si, capped with ultra thin Si (Si/Ge/Si substrate) were evaluated. NMOSFET shows enhanced mobility at low field while pMOSFET shows degraded peak mobility, with enhancement observed only at high field.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124384491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635210
F. J. Garcla-Satnchez, A. Ortiz-Conde, J. Muci
Undoped-body MOSFETs display peculiar semiconductor body thickness dependent subthreshold regions. The very concept of threshold voltage in undoped-body devices is affected by the interpretation given to this behavior. The fundamental subthreshold behavior is examined here from the point of view of its extension and slope factor. Its dependence on technological parameters is analyzed in light of phenomenological considerations. It is found that the subthreshold region may potentially exhibit two coexisting subregions with ideal slope factors of 60 and 120 mV/dec.
{"title":"Subthreshold Behavior of Undoped DG MOSFETs","authors":"F. J. Garcla-Satnchez, A. Ortiz-Conde, J. Muci","doi":"10.1109/EDSSC.2005.1635210","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635210","url":null,"abstract":"Undoped-body MOSFETs display peculiar semiconductor body thickness dependent subthreshold regions. The very concept of threshold voltage in undoped-body devices is affected by the interpretation given to this behavior. The fundamental subthreshold behavior is examined here from the point of view of its extension and slope factor. Its dependence on technological parameters is analyzed in light of phenomenological considerations. It is found that the subthreshold region may potentially exhibit two coexisting subregions with ideal slope factors of 60 and 120 mV/dec.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116374311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635405
K. Gan, Dong-Shong Liang, Chung-Chih Hsiao, Cher-Shiung Tsai, Y. Chen
A voltage-controlled ring oscillator (VCO) based on novel MOS-NDR circuit is described. This MOS-NDR circuit is made of metal-oxide-semiconductor emiconductor ield-effect-transistor ( MOS) devices that can exhibit the negative differential resistance (NDR) current-voltage characteristic by suitably arranging the MOS parameters. The VCO is constructed by three low-power ower MOS-NDR inverters. This novel VCO has a range of operation frequency from 38MHz to 162MHz. It consumes 24mW in its central frequency of 118MHz using a 2V power supply. This VCO is fabricated by 0.35μm CMOS process and occupy an area of 0.015 mm2.
{"title":"Investigation of MOS-NDR Voltage Controlled Ring Oscillator Fabricated by CMOS Process","authors":"K. Gan, Dong-Shong Liang, Chung-Chih Hsiao, Cher-Shiung Tsai, Y. Chen","doi":"10.1109/EDSSC.2005.1635405","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635405","url":null,"abstract":"A voltage-controlled ring oscillator (VCO) based on novel MOS-NDR circuit is described. This MOS-NDR circuit is made of metal-oxide-semiconductor emiconductor ield-effect-transistor ( MOS) devices that can exhibit the negative differential resistance (NDR) current-voltage characteristic by suitably arranging the MOS parameters. The VCO is constructed by three low-power ower MOS-NDR inverters. This novel VCO has a range of operation frequency from 38MHz to 162MHz. It consumes 24mW in its central frequency of 118MHz using a 2V power supply. This VCO is fabricated by 0.35μm CMOS process and occupy an area of 0.015 mm2.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122068177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635276
R. Barsatan, T. Y. Man, M. Chan
A Write-Once-Read-Many (WORM) memory using a CMOS-compatible Antifuse (AF) element for low-cost nonvolatile memory is presented. The AF device is formed on an NMOS with PLDD implants (MOS-channel AF) to enhance hot-carrier effects. The AF is programmed by applying a high voltage across the channel until breakdown such that it becomes resistor. The devices were fabricated in standard TSMC 0.18μm process without any process modification. The channel breakdown was observed between 4.5V to 5V. The programmed resistance is in the kΩ range at milliampere range of programming current. A 128-bit WORM architecture is presented based on an IO-select transistor and the AF memory cell. The architecture was designed and simulated in Cadence to verify the functionality of the device when formed in an array.
{"title":"A CMOS-Compatible WORM Memory for Low-Cost Non-Volatile Memory Applications","authors":"R. Barsatan, T. Y. Man, M. Chan","doi":"10.1109/EDSSC.2005.1635276","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635276","url":null,"abstract":"A Write-Once-Read-Many (WORM) memory using a CMOS-compatible Antifuse (AF) element for low-cost nonvolatile memory is presented. The AF device is formed on an NMOS with PLDD implants (MOS-channel AF) to enhance hot-carrier effects. The AF is programmed by applying a high voltage across the channel until breakdown such that it becomes resistor. The devices were fabricated in standard TSMC 0.18μm process without any process modification. The channel breakdown was observed between 4.5V to 5V. The programmed resistance is in the kΩ range at milliampere range of programming current. A 128-bit WORM architecture is presented based on an IO-select transistor and the AF memory cell. The architecture was designed and simulated in Cadence to verify the functionality of the device when formed in an array.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116810598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：