Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635282
Qiang Bian, Zushu Yan, Yuanfu Zhao, S. Yue
Using voltage controlled current source (VCCS) instead of electrical series resistance (ESR) of load capacitor to create a zero is a novel LDO frequency compensation scheme. This paper analyzes this compensation scheme, and reveals that the VCCS circuit conduces to the improvements of transient response and PSR performance of LDO. A new area compact VCCS circuit that has a nearly ideal performance in wide frequency spectrum up to 5MHzis also presented. Using VCCS, a LDO with 300mV dropout, 2.5V output voltage and l00mA output current is designed in 0.5μm CMOS technology with pretty frequency performance, transient response and PSR performance. The total on-chip capacitor employed in this LDO is less than 1pF.
{"title":"Analysis and Design of Voltage Controlled Current Source for LDO Frequency Compensation","authors":"Qiang Bian, Zushu Yan, Yuanfu Zhao, S. Yue","doi":"10.1109/EDSSC.2005.1635282","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635282","url":null,"abstract":"Using voltage controlled current source (VCCS) instead of electrical series resistance (ESR) of load capacitor to create a zero is a novel LDO frequency compensation scheme. This paper analyzes this compensation scheme, and reveals that the VCCS circuit conduces to the improvements of transient response and PSR performance of LDO. A new area compact VCCS circuit that has a nearly ideal performance in wide frequency spectrum up to 5MHzis also presented. Using VCCS, a LDO with 300mV dropout, 2.5V output voltage and l00mA output current is designed in 0.5μm CMOS technology with pretty frequency performance, transient response and PSR performance. The total on-chip capacitor employed in this LDO is less than 1pF.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123589690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635393
Xusheng Wu, P. Chan, S. Zhang, M. Chan
Capped trimming hard-mask (CTHM) patterning technique has been developed based on standard materials and processing equipments. By using the CTHM technique, sub-50nm feature sized pattern can be realized based on 0.5μm lithography technology. Imaging layer for capping and hard-mask layer shoul d have different etching selectivity and good contiguity to each other. Good control of trimming etching and hard-mask etching processes enable patterning of features with ultra-small dimension.
{"title":"A Capped Trimming Hard-Mask Patterning Technique for Integration of Nano-Devices and Conventional Integrated Circuits","authors":"Xusheng Wu, P. Chan, S. Zhang, M. Chan","doi":"10.1109/EDSSC.2005.1635393","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635393","url":null,"abstract":"Capped trimming hard-mask (CTHM) patterning technique has been developed based on standard materials and processing equipments. By using the CTHM technique, sub-50nm feature sized pattern can be realized based on 0.5μm lithography technology. Imaging layer for capping and hard-mask layer shoul d have different etching selectivity and good contiguity to each other. Good control of trimming etching and hard-mask etching processes enable patterning of features with ultra-small dimension.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122370260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635284
Guowen Wei, O. Trescases, W. Ng
For devices operating mainly in the standby or low power mode, energy saving from dynamic voltage scaling (DVS) is limited due to very poor efficiency of the PWM DC/DC converter operating at light load conditions, resulting in shorter than expected battery life. This paper first presents the design of a DVS controller - realized on a Xilinx CoolRunner 2 CPLD - having a 25μs worst case transient response and 15 mV average Vddstep size across an 1.30-1.90 V range. Next a scheme is proposed in which the DVS controller automatically selects between the PFM and PWM mode DC/DC conversion to realize maximum power saving across full range of load conditions.
{"title":"A Dynamic Voltage Scaling Controller for Maximum Energy Saving Across Full Range of Load Conditions","authors":"Guowen Wei, O. Trescases, W. Ng","doi":"10.1109/EDSSC.2005.1635284","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635284","url":null,"abstract":"For devices operating mainly in the standby or low power mode, energy saving from dynamic voltage scaling (DVS) is limited due to very poor efficiency of the PWM DC/DC converter operating at light load conditions, resulting in shorter than expected battery life. This paper first presents the design of a DVS controller - realized on a Xilinx CoolRunner 2 CPLD - having a 25μs worst case transient response and 15 mV average Vddstep size across an 1.30-1.90 V range. Next a scheme is proposed in which the DVS controller automatically selects between the PFM and PWM mode DC/DC conversion to realize maximum power saving across full range of load conditions.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"400 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115992338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635332
Y.S. Chi, J. Lu, S.Y. Zhang, Z. Wu, F. Huang
An analytical method to directly extract the MOSFET small-signal model parameters including non-quais-static and substrate effect from S-parameter is presented. This method only relies on S-parameter measured in active region and is verified by RF MOSFET fabricated in 0.13 μm CMOS technology. Good agreement is obtained between the simulated results and the measured data up to 30 GHz.
{"title":"An Analytical Parameter Extraction of the Small-Signal Model for RF MOSFETs","authors":"Y.S. Chi, J. Lu, S.Y. Zhang, Z. Wu, F. Huang","doi":"10.1109/EDSSC.2005.1635332","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635332","url":null,"abstract":"An analytical method to directly extract the MOSFET small-signal model parameters including non-quais-static and substrate effect from S-parameter is presented. This method only relies on S-parameter measured in active region and is verified by RF MOSFET fabricated in 0.13 μm CMOS technology. Good agreement is obtained between the simulated results and the measured data up to 30 GHz.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116881666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635377
Hongda Chen, Ming Gu, Jiale Huang, Peng Gao, L. Mao
A 1GHz monolithic photo-detector (PD) and trans-impedance amplifier (TIA) is designed with the standard 0.35μm CMOS technique. The design of the photo-detector is analyzed and the CMOS trans-impedance amplifier is also analyzed in the paper. The integrating method is described too. The die photograph is also showed in the paper.
{"title":"A Standard CMOS Compatible Monolithic Photo-Detector and Trans-impedance Amplifier","authors":"Hongda Chen, Ming Gu, Jiale Huang, Peng Gao, L. Mao","doi":"10.1109/EDSSC.2005.1635377","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635377","url":null,"abstract":"A 1GHz monolithic photo-detector (PD) and trans-impedance amplifier (TIA) is designed with the standard 0.35μm CMOS technique. The design of the photo-detector is analyzed and the CMOS trans-impedance amplifier is also analyzed in the paper. The integrating method is described too. The die photograph is also showed in the paper.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117166723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635194
R. Chau
This presentation will highlight the opportunities and challenges ofnon-Si materials such as i) carbon-nanotubes (CNTs), ii) semiconductor-nanowires, iii) Ge, and iv) Ill-V materials for future high-speed, low-power logic applications. These materials, in general, have significantly higher intrinsic mobility (either hole or electron mobility) than Si, and they can potentially be used to replace Si as the channel material of the transistor to both enhance speed and reduce power. In this talk, emerging nanoelectronic devices such as semiconductor-nanowire field effect transistors (FETs) [1,2], carbon-nanotube FETs [1-3], Ge MOSFETs [4], strained Ge quantum-well FETs [4], and III-V compound semiconductor quantum-well FETs [4-6], are assessed for their potential in future high-performance, low-power computation applications. These emerging devices are benchmarked against state-of-the-art Si CMOS technologies in terms ofboth speed and power dissipation. The three fundamental transistor benchmarking metrics utilized in this study are i) intrinsic gate delay versus transistor physical gate length, ii) energy-delay product versus transistor physical gate length, and iii) intrinsic gate-delay versus the on-current/off-state leakage ratio (Ion/loff). While intrinsic device speed and switching energy are emphasized in the first and second metrics respectively, the tradeoff between device speed versus off-state leakage is assessed in the third metric. For high-speed and low-power logic applications, both low gate delay and low energy-delay product, as well as high Ion/loff ratios are required. The current status of these emerging nanoelectronic devices in light of the above metrics will be described in this talk. In addition, the merits and shortcomings, as well as the physics of operation of these devices, will be described. In addition to the above device aspects, the material and integration (onto silicon) aspects of these emerging nanotechnologies are significant as well. These non-Si materials will not replace Si, rather they will need to be integrated onto the silicon substrate. Both CNTs and semiconductor nanowires are formed using "bottom-up" chemical syntheses, and they currently suffer from the fundamental placement problem, i.e., there exists no practical nor reliable way to precisely align and position them. On the other hand, Ill-V and Ge materials can be patterned into desirable device structures using conventional "top-down" lithographic and etch techniques. In this regard, III-Vs and Ge are considered far more practical than CNTs and nanowires for future high-speed, low-power nanoelectronic device applications. In fact, Ill-V materials have been used in communication and optoelectronic products for quite some time. However, many significant challenges remain for III-V materials to become applicable for future high-speed, low-power logic applications. These include (i) finding a gate dielectric compatible with III-Vs, (ii) demonstrating transi
{"title":"Opportunities and Challenges of Emerging Nanotechnologies for Future High-Speed and Low-Power Logic Applications","authors":"R. Chau","doi":"10.1109/EDSSC.2005.1635194","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635194","url":null,"abstract":"This presentation will highlight the opportunities and challenges ofnon-Si materials such as i) carbon-nanotubes (CNTs), ii) semiconductor-nanowires, iii) Ge, and iv) Ill-V materials for future high-speed, low-power logic applications. These materials, in general, have significantly higher intrinsic mobility (either hole or electron mobility) than Si, and they can potentially be used to replace Si as the channel material of the transistor to both enhance speed and reduce power. In this talk, emerging nanoelectronic devices such as semiconductor-nanowire field effect transistors (FETs) [1,2], carbon-nanotube FETs [1-3], Ge MOSFETs [4], strained Ge quantum-well FETs [4], and III-V compound semiconductor quantum-well FETs [4-6], are assessed for their potential in future high-performance, low-power computation applications. These emerging devices are benchmarked against state-of-the-art Si CMOS technologies in terms ofboth speed and power dissipation. The three fundamental transistor benchmarking metrics utilized in this study are i) intrinsic gate delay versus transistor physical gate length, ii) energy-delay product versus transistor physical gate length, and iii) intrinsic gate-delay versus the on-current/off-state leakage ratio (Ion/loff). While intrinsic device speed and switching energy are emphasized in the first and second metrics respectively, the tradeoff between device speed versus off-state leakage is assessed in the third metric. For high-speed and low-power logic applications, both low gate delay and low energy-delay product, as well as high Ion/loff ratios are required. The current status of these emerging nanoelectronic devices in light of the above metrics will be described in this talk. In addition, the merits and shortcomings, as well as the physics of operation of these devices, will be described. In addition to the above device aspects, the material and integration (onto silicon) aspects of these emerging nanotechnologies are significant as well. These non-Si materials will not replace Si, rather they will need to be integrated onto the silicon substrate. Both CNTs and semiconductor nanowires are formed using \"bottom-up\" chemical syntheses, and they currently suffer from the fundamental placement problem, i.e., there exists no practical nor reliable way to precisely align and position them. On the other hand, Ill-V and Ge materials can be patterned into desirable device structures using conventional \"top-down\" lithographic and etch techniques. In this regard, III-Vs and Ge are considered far more practical than CNTs and nanowires for future high-speed, low-power nanoelectronic device applications. In fact, Ill-V materials have been used in communication and optoelectronic products for quite some time. However, many significant challenges remain for III-V materials to become applicable for future high-speed, low-power logic applications. These include (i) finding a gate dielectric compatible with III-Vs, (ii) demonstrating transi","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115664977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635247
Shih-Chih Chen, Ruey-Lue Wang, Ming-Lung Kung, Hsiang-Chen Kuo
For the ultra-wide-band communication applications, this work presents a two-stage topology to implement a low noise amplifier (LNA) based on the 0.18 um TSMC CMOS technology. We adopt the voltage-current resistor feedback and shunt-peaked circuit to obtain measurement results of maximum gain in 14.0 dB, noise figure below 5.25 dB, input and output reflection coefficients below -11dB within the bandwidth between 3 GHz to 5 GHz.
对于超宽带通信应用，本文提出了一种基于0.18 um TSMC CMOS技术的两级拓扑结构来实现低噪声放大器(LNA)。我们采用压流电阻反馈和分峰电路，在3 GHz ~ 5 GHz的带宽范围内，获得了最大增益在14.0 dB，噪声系数在5.25 dB以下，输入输出反射系数在-11dB以下的测量结果。
{"title":"An Integrated CMOS Low Noise Amplifier for 3-5 GHz UWB Applications","authors":"Shih-Chih Chen, Ruey-Lue Wang, Ming-Lung Kung, Hsiang-Chen Kuo","doi":"10.1109/EDSSC.2005.1635247","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635247","url":null,"abstract":"For the ultra-wide-band communication applications, this work presents a two-stage topology to implement a low noise amplifier (LNA) based on the 0.18 um TSMC CMOS technology. We adopt the voltage-current resistor feedback and shunt-peaked circuit to obtain measurement results of maximum gain in 14.0 dB, noise figure below 5.25 dB, input and output reflection coefficients below -11dB within the bandwidth between 3 GHz to 5 GHz.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114190072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635349
Y. Yin, A. Miyachi, D. Niida, H. Sone, S. Hosaka
We investigated electrical properties on phase change and channel current control effect in phase-change channel transistors with a 10-nm- to 200-nm-thick Ge2Sb2Te5film channel by Joule heating and annealing. I-V characteristics showing a phase change by Joule heating were measured. The current switching from an amorphous to crystalline state is about 2μA. A channel current control effect by the gate voltage since Joule heating in 50-nm- to 200-nm-thick devices was observed but not strong. Switching to the lowly resistive state in devices with an ultrathin channel was difficult, which might be due to large voids forming in the heated Ge2Sb2Te5channel. After annealing, drain-source resistance of devices dropped by about 3 orders of magnitude owing to phase change. A clear channel current control effect was observed especially for devices with an ultrathin channel. There exists a strong thickness dependence of channel current control effect.
{"title":"Thickness Dependences of Phase Change and Channel Current Control in Phase-Change Channel Transistor","authors":"Y. Yin, A. Miyachi, D. Niida, H. Sone, S. Hosaka","doi":"10.1109/EDSSC.2005.1635349","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635349","url":null,"abstract":"We investigated electrical properties on phase change and channel current control effect in phase-change channel transistors with a 10-nm- to 200-nm-thick Ge2Sb2Te5film channel by Joule heating and annealing. I-V characteristics showing a phase change by Joule heating were measured. The current switching from an amorphous to crystalline state is about 2μA. A channel current control effect by the gate voltage since Joule heating in 50-nm- to 200-nm-thick devices was observed but not strong. Switching to the lowly resistive state in devices with an ultrathin channel was difficult, which might be due to large voids forming in the heated Ge2Sb2Te5channel. After annealing, drain-source resistance of devices dropped by about 3 orders of magnitude owing to phase change. A clear channel current control effect was observed especially for devices with an ultrathin channel. There exists a strong thickness dependence of channel current control effect.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"292 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115324878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635375
C. K. Wah, A. Bermak, F. Boussaid
In this paper, a second generation current mode active pixel sensor is presented. It uses a faster operating technique based on the simultaneous reset/read-out of pixels. It improves the voltage swing at the sensing node from 1.3V to 2.3V in a 3.3V CMOS process.
{"title":"Second Generation Current Mode Active Pixel Sensor","authors":"C. K. Wah, A. Bermak, F. Boussaid","doi":"10.1109/EDSSC.2005.1635375","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635375","url":null,"abstract":"In this paper, a second generation current mode active pixel sensor is presented. It uses a faster operating technique based on the simultaneous reset/read-out of pixels. It improves the voltage swing at the sensing node from 1.3V to 2.3V in a 3.3V CMOS process.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"240 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114714888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635258
S. Hui, Wu Xiaobo, Yan Xiaolang
Voltage reference with high PSRR (Power Supply Rejection Ratio) and thermal stability is of key importance to power management IC (integrated circuit). By building up a stable internal regulated supply and improving its circuit and layout design, especially that of matching, a bandgap reference with high PSRR was proposed. Simulation results showed that PSRR of the circuit at low frequency was 64dB, and the peak-to-peak output voltage variation was 7.2mV over -40°C to 80°C.
{"title":"A Precise Bandgap Reference with High PSRR","authors":"S. Hui, Wu Xiaobo, Yan Xiaolang","doi":"10.1109/EDSSC.2005.1635258","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635258","url":null,"abstract":"Voltage reference with high PSRR (Power Supply Rejection Ratio) and thermal stability is of key importance to power management IC (integrated circuit). By building up a stable internal regulated supply and improving its circuit and layout design, especially that of matching, a bandgap reference with high PSRR was proposed. Simulation results showed that PSRR of the circuit at low frequency was 64dB, and the peak-to-peak output voltage variation was 7.2mV over -40°C to 80°C.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126047637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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