Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635299
M. Zhigang, Wen Bi-yang, Wang Caijun, Y. Weidong
Design Method for UHF Surface Velocities Radar System is presented. This UHF Radar System is developed based on the successful OSMAR System. It was modified to operate at UHF (310MHz) and wide FM sweep width (5-10MHz) to match the expected water wavelengths and channel dimension. Transmit power is under 5w, and maximum range over fresh water will more than a kilometer. All hardware modules had been finished and simulation proves this system can be used successfully.
{"title":"UHF Surface Velocities Radar System Design","authors":"M. Zhigang, Wen Bi-yang, Wang Caijun, Y. Weidong","doi":"10.1109/EDSSC.2005.1635299","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635299","url":null,"abstract":"Design Method for UHF Surface Velocities Radar System is presented. This UHF Radar System is developed based on the successful OSMAR System. It was modified to operate at UHF (310MHz) and wide FM sweep width (5-10MHz) to match the expected water wavelengths and channel dimension. Transmit power is under 5w, and maximum range over fresh water will more than a kilometer. All hardware modules had been finished and simulation proves this system can be used successfully.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122739933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635248
Chih-Chang Lee, G. Ma
In this paper, a 250MHz, CMOS programmable gain low pass filter for ultra-wideband transmitter is presented. The programmable gain network that is programmed by decoder will be utilized to control the gain of filter. In order to reach sufficient attenuation, the 8rdGm-C chebyshev low pass filter base on leap-frog topology is employed. Simulation results with CMOS 0.18μm technology show that the gain can be programmed from-14dB to -32dB with 2dB step, step accuracy and absolute accuracy are ±0.15 and ±0.25. The THD of programmable gain filter is -40dB for lVpp input signal and power dissipation is 15.7mW under 1.8V power supply.
{"title":"A 1.8V 250MHz CMOS Programmable Gain Filter for Ultra-wideband Transmitter System","authors":"Chih-Chang Lee, G. Ma","doi":"10.1109/EDSSC.2005.1635248","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635248","url":null,"abstract":"In this paper, a 250MHz, CMOS programmable gain low pass filter for ultra-wideband transmitter is presented. The programmable gain network that is programmed by decoder will be utilized to control the gain of filter. In order to reach sufficient attenuation, the 8rdGm-C chebyshev low pass filter base on leap-frog topology is employed. Simulation results with CMOS 0.18μm technology show that the gain can be programmed from-14dB to -32dB with 2dB step, step accuracy and absolute accuracy are ±0.15 and ±0.25. The THD of programmable gain filter is -40dB for lVpp input signal and power dissipation is 15.7mW under 1.8V power supply.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123836602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635291
V. Pant, V. Pandit
Low injection profile of base current is of great importance while considering power-efficient system design. The base current in SiGe HBT at low VBEis higher than Si-BJT base current. This shows the adverse side of using the otherwise superior heterojunction SiGe-HBT over Si-BJT. This paper presents a physical model of low-injection base current and discusses the way this model can be used to estimate defect density in SiGe device.
{"title":"Low Injection Base Current Model for SiGe HBT in E-B Depletion Region","authors":"V. Pant, V. Pandit","doi":"10.1109/EDSSC.2005.1635291","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635291","url":null,"abstract":"Low injection profile of base current is of great importance while considering power-efficient system design. The base current in SiGe HBT at low VBEis higher than Si-BJT base current. This shows the adverse side of using the otherwise superior heterojunction SiGe-HBT over Si-BJT. This paper presents a physical model of low-injection base current and discusses the way this model can be used to estimate defect density in SiGe device.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128311317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635337
Ling Li, H. Kosina
An analytical model that describes the DC characteristics of organic thin film transistors (OTFTs) is presented. The model is based on the variable range hopping theory, i.e. thermally activated tunneling of carriers between localized states. As verified by published data, the model provides an accurate and efficient prediction for transfer characteristics and output characteristics of OTFT via simple formulations.
{"title":"An analytical model for organic thin film transistors","authors":"Ling Li, H. Kosina","doi":"10.1109/EDSSC.2005.1635337","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635337","url":null,"abstract":"An analytical model that describes the DC characteristics of organic thin film transistors (OTFTs) is presented. The model is based on the variable range hopping theory, i.e. thermally activated tunneling of carriers between localized states. As verified by published data, the model provides an accurate and efficient prediction for transfer characteristics and output characteristics of OTFT via simple formulations.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127060766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635214
Yu-Sheng Lin, Chia‐Hong Lin, J. Kuo, K. Su
This paper reports the CGS(D)/CS(D)Gcapacitance phenomenon of 100nm fully-depleted (FD) SOI CMOS devices with HfO2high-k gate dielectric considering vertical and fringing displacement effect. According to the 2D simulation results, a unique two-step CS(D)G/CGSversus VGcurve exists for the device with the 1.5nm HfO2gate dielectric due to the vertical and fringing displacement effects.
本文报道了考虑垂直位移效应和边缘位移效应的hfo2高k栅极介质的100nm满耗尽(FD) SOI CMOS器件的CGS(D)/CS(D) g电容现象。二维仿真结果表明，由于垂直位移和边缘位移效应，1.5nm hfo2栅极介质器件存在独特的两步CS(D)G/ cgsvs . vg曲线。
{"title":"CGS(D)/CS(D)GCapacitance Phenomenon of 100nm Fully-Depleted SOI CMOS Devices with HfO2High-K Gate Dielectric Considering Vertical and Fringing Displacement Effects","authors":"Yu-Sheng Lin, Chia‐Hong Lin, J. Kuo, K. Su","doi":"10.1109/EDSSC.2005.1635214","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635214","url":null,"abstract":"This paper reports the C<inf>GS(D)</inf>/C<inf>S(D)G</inf>capacitance phenomenon of 100nm fully-depleted (FD) SOI CMOS devices with HfO<inf>2</inf>high-k gate dielectric considering vertical and fringing displacement effect. According to the 2D simulation results, a unique two-step C<inf>S(D)G</inf>/C<inf>GS</inf>versus V<inf>G</inf>curve exists for the device with the 1.5nm HfO<inf>2</inf>gate dielectric due to the vertical and fringing displacement effects.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130713375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635200
Yue Fu, H. Wong, J. Liou
The noise behaviors of the junction field-effect transistor (JFET) fabricated with self-aligned planer technology are studied. The device structure being considered has a wide separation between source-gate and drain-gate with a shallow trench isolation (STI) technique. High noise level is found in the devices with STI and the normalized drain noise is found to be gate bias dependent. The excess noise is identified as the surface noise generated in the STI regions and a model is developed to explain the bias dependence of the noise characteristics. To reduce the noise level, the STI region should be kept small and better oxidation technique should be employed for the STI passivation.
{"title":"Modeling of Low-Frequency Noise in Junction Field-Effect Transistor with Self-Aligned Planer Technology","authors":"Yue Fu, H. Wong, J. Liou","doi":"10.1109/EDSSC.2005.1635200","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635200","url":null,"abstract":"The noise behaviors of the junction field-effect transistor (JFET) fabricated with self-aligned planer technology are studied. The device structure being considered has a wide separation between source-gate and drain-gate with a shallow trench isolation (STI) technique. High noise level is found in the devices with STI and the normalized drain noise is found to be gate bias dependent. The excess noise is identified as the surface noise generated in the STI regions and a model is developed to explain the bias dependence of the noise characteristics. To reduce the noise level, the STI region should be kept small and better oxidation technique should be employed for the STI passivation.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129802585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635325
D. Prasertsom, T. Pukkalanun, W. Tangsrirat, W. Surakampontom
A realization of a current-mode second-order notch filter using current followers (CFs) and a minimum number of passive elements is proposed. The proposed filter has a high output impedance, consequently it can be cascaded without using additional buffers. The filter displays low incremental passive sensitivities. Moreover, if the passive element values are properly chosen, the circuit permits also the realization of allpass response. The SPICE simulation results are given to verify the theoretical predicted behaviors.
{"title":"Low Passive Component-Count Current Follower-Based Current-Mode Second-Order Notch Filter","authors":"D. Prasertsom, T. Pukkalanun, W. Tangsrirat, W. Surakampontom","doi":"10.1109/EDSSC.2005.1635325","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635325","url":null,"abstract":"A realization of a current-mode second-order notch filter using current followers (CFs) and a minimum number of passive elements is proposed. The proposed filter has a high output impedance, consequently it can be cascaded without using additional buffers. The filter displays low incremental passive sensitivities. Moreover, if the passive element values are properly chosen, the circuit permits also the realization of allpass response. The SPICE simulation results are given to verify the theoretical predicted behaviors.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"21 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132483911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635326
Hoi Lee, K. Leung, P. Mok
Techniques of bias-current re-utilization, self-biasing and signal superposition for low-voltage analog circuit designs are presented in this paper. When these techniques are adopted in a three-stage active-feedback compensated amplifier by using a self-cascode common-gate structure, the circuit complexity of the amplifier is simplified. In addition, the power consumption, parasitic capacitance and systematic offset voltage of the amplifier can be greatly reduced. The effectiveness of the proposed design methodologies is verified by remarkable HSPICE simulation results.
{"title":"Low-Voltage Analog Circuit Techniques Using Bias-Current Re-Utilization, Self-Biasing and Signal Superposition","authors":"Hoi Lee, K. Leung, P. Mok","doi":"10.1109/EDSSC.2005.1635326","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635326","url":null,"abstract":"Techniques of bias-current re-utilization, self-biasing and signal superposition for low-voltage analog circuit designs are presented in this paper. When these techniques are adopted in a three-stage active-feedback compensated amplifier by using a self-cascode common-gate structure, the circuit complexity of the amplifier is simplified. In addition, the power consumption, parasitic capacitance and systematic offset voltage of the amplifier can be greatly reduced. The effectiveness of the proposed design methodologies is verified by remarkable HSPICE simulation results.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"494 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114203095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635286
Somjai Arayawat, S. Pongswatd, P. Ukakimapurn, Thanit Trisuwannawat
This paper proposes the design and technique for controlling DC voltage of DC-DC converter using isolated current feedback. When testing with different loads [1], the output obtained has good voltage regulator, a wide input voltage range, quick response and safe. This research uses phototransistor to detect output current signal and send feedback with isolated electrical signal to PWM (Pulse Width Modulation) circuit to control the duty cycle fed to switch. Buck converter is a step down voltage converter, which results in the current at output higher than that of input [2]. This research uses output current fed through Opto and select only linear interval current ratio fed to control and feedback. The experiment is performed using Buck-Type DC-DC converter to level the output voltage as desired.Results are satisfying and a simplest circuit.
{"title":"Isolated Current Feedback Control for Buck Converter","authors":"Somjai Arayawat, S. Pongswatd, P. Ukakimapurn, Thanit Trisuwannawat","doi":"10.1109/EDSSC.2005.1635286","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635286","url":null,"abstract":"This paper proposes the design and technique for controlling DC voltage of DC-DC converter using isolated current feedback. When testing with different loads [1], the output obtained has good voltage regulator, a wide input voltage range, quick response and safe. This research uses phototransistor to detect output current signal and send feedback with isolated electrical signal to PWM (Pulse Width Modulation) circuit to control the duty cycle fed to switch. Buck converter is a step down voltage converter, which results in the current at output higher than that of input [2]. This research uses output current fed through Opto and select only linear interval current ratio fed to control and feedback. The experiment is performed using Buck-Type DC-DC converter to level the output voltage as desired.Results are satisfying and a simplest circuit.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114819043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635366
Fan Zhou, R. Huang, X. An, A. Guo, X.Y. Xu, X. Zhang, D.C. Zhang, Y.Y. Wang
40-nm and 32-nm channel length vertical nMOSFETs with an asymmetric graded low doped drain (AGLDD) structure (the LDD region only on the drain side) were experimentally demonstrated. Due to remarkably reduced peak electric field near the drain junction compared with conventional LDD structure, the vertical AGLDD structure can reduce the off-state leakage current and suppress the short channel effects dramatically. The fabricated device with 32-nm channel length, 4.0-nm gate oxide thickness still shows excellent short channel performance as the off-state leakage current (Ioff) and the ratio of the on-state driving current (Ion) to Ioffare 3.7 X 10-11μA/μm and 2.1 X 106, respectively.
{"title":"Sub-50-nm Asymmetric Graded Low Doped Drain (AGLDD) Vertical Channel nMOSFET","authors":"Fan Zhou, R. Huang, X. An, A. Guo, X.Y. Xu, X. Zhang, D.C. Zhang, Y.Y. Wang","doi":"10.1109/EDSSC.2005.1635366","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635366","url":null,"abstract":"40-nm and 32-nm channel length vertical nMOSFETs with an asymmetric graded low doped drain (AGLDD) structure (the LDD region only on the drain side) were experimentally demonstrated. Due to remarkably reduced peak electric field near the drain junction compared with conventional LDD structure, the vertical AGLDD structure can reduce the off-state leakage current and suppress the short channel effects dramatically. The fabricated device with 32-nm channel length, 4.0-nm gate oxide thickness still shows excellent short channel performance as the off-state leakage current (Ioff) and the ratio of the on-state driving current (Ion) to Ioffare 3.7 X 10-11μA/μm and 2.1 X 106, respectively.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128489452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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