Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635270
D. Lee, I.-S.M. Sun, W. Ng
A methodology for modelling a novel highfrequency lateral bipolar junction transistor (LBJT) is described. A modified SPICE-Gummel-Poon (SGP) model is used to simulate the device, with the SGP parameters determined based on the transistor's physical geometry. DC, AC, and S-parameter simulations using this model are verified against measured data. The results show good matching and demonstrates that the novel geometry of the LBJT facilitates modelling by reducing the influence of second order effects.
{"title":"RF Model of Lateral Bipolar Junction Transistor on Silicon-on-Insulator Substrate","authors":"D. Lee, I.-S.M. Sun, W. Ng","doi":"10.1109/EDSSC.2005.1635270","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635270","url":null,"abstract":"A methodology for modelling a novel highfrequency lateral bipolar junction transistor (LBJT) is described. A modified SPICE-Gummel-Poon (SGP) model is used to simulate the device, with the SGP parameters determined based on the transistor's physical geometry. DC, AC, and S-parameter simulations using this model are verified against measured data. The results show good matching and demonstrates that the novel geometry of the LBJT facilitates modelling by reducing the influence of second order effects.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115818154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635306
Jie Fan, Ju Tang, G. Yan, Yacong Zhang, L. Ji
In this paper, a novel high-accuracy and high-speed current comparator using gain boosting structures in parallel is proposed based on CSMC 0.5μm standard CMOS process. Two amplifiers are employed in the circuit whose open-loop gain has been fully used to improve the comparing accuracy. Simulation results reveal that a high resolution better than 0.01μA can be easily obtained by this approach. Some comparisons were made when amplifier open -loop gain retrogressed, power supply voltage scaled down or reference current varied. Detailed discussions about its average power dissipation and propagation delay are presented. The response delay is less than 16ns for ±0.1μA current difference at the supply voltage of 2V, which is expected to be further improved with 0.18μm standard CMOS process.
{"title":"Circuit Design of a High Performance CMOS Continuous-time Current Comparator with Gain Boosting Structures in Parallel","authors":"Jie Fan, Ju Tang, G. Yan, Yacong Zhang, L. Ji","doi":"10.1109/EDSSC.2005.1635306","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635306","url":null,"abstract":"In this paper, a novel high-accuracy and high-speed current comparator using gain boosting structures in parallel is proposed based on CSMC 0.5μm standard CMOS process. Two amplifiers are employed in the circuit whose open-loop gain has been fully used to improve the comparing accuracy. Simulation results reveal that a high resolution better than 0.01μA can be easily obtained by this approach. Some comparisons were made when amplifier open -loop gain retrogressed, power supply voltage scaled down or reference current varied. Detailed discussions about its average power dissipation and propagation delay are presented. The response delay is less than 16ns for ±0.1μA current difference at the supply voltage of 2V, which is expected to be further improved with 0.18μm standard CMOS process.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126762802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635341
Liu Dan, Tang Ju, Lu Wengao, Chen Zhongjian, Zhao Baoying, Ji Lijiu
A novel column readout architecture for infrared (IR) readout integrated circuit (ROIC) is proposed in this paper. When the readout rate is 5M Hz, by applying master-slave column amplifier and the technology of divided-output-bus, the power of the column readout stage has been reduced from more than 47mw to 6.74mw, which reduced more than 85%. In the master-slave readout structure, master amplifiers convert the charge to voltage, which have relaxed time limit. Slave amplifiers drive the output bus and ensure the readout rate, which adopts low power standby work mode. The technology of divided-output-bus is to divide the 320 pairs of switches to 20 groups and reduces the switches connected to the output bus, which does help to reduce power dissipation of slave amplifiers. A 320X288 IR ROIC with pixel size of 30X30μm2has been designed with this architecture which based on CSMC 0.5μm DPDM n-well CMOS process.
提出了一种用于红外读出集成电路(ROIC)的柱式读出结构。当读出速率为5M Hz时，采用主从列放大器和分输出总线技术，使列读出级功率从47mw以上降低到6.74mw，降低幅度达85%以上。在主从读出结构中，主放大器将电荷转换为电压，时间限制放宽。从放大器驱动输出总线，保证读出速率，采用低功耗待机工作模式。分输出总线技术是将320对开关分成20组，减少连接在输出总线上的开关，这样有助于降低从放大器的功耗。基于CSMC 0.5μm DPDM n阱CMOS工艺，设计了像素尺寸为30x30 μm2的320X288 IR ROIC。
{"title":"Low Power Design of Column Readout Stage for 320x288 Snapshot Infrared ROIC","authors":"Liu Dan, Tang Ju, Lu Wengao, Chen Zhongjian, Zhao Baoying, Ji Lijiu","doi":"10.1109/EDSSC.2005.1635341","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635341","url":null,"abstract":"A novel column readout architecture for infrared (IR) readout integrated circuit (ROIC) is proposed in this paper. When the readout rate is 5M Hz, by applying master-slave column amplifier and the technology of divided-output-bus, the power of the column readout stage has been reduced from more than 47mw to 6.74mw, which reduced more than 85%. In the master-slave readout structure, master amplifiers convert the charge to voltage, which have relaxed time limit. Slave amplifiers drive the output bus and ensure the readout rate, which adopts low power standby work mode. The technology of divided-output-bus is to divide the 320 pairs of switches to 20 groups and reduces the switches connected to the output bus, which does help to reduce power dissipation of slave amplifiers. A 320X288 IR ROIC with pixel size of 30X30μm2has been designed with this architecture which based on CSMC 0.5μm DPDM n-well CMOS process.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134345301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635257
T. Zhao, Dacheng Zhang
Since the sensitivity of a piezoresistive device has a large negative temperature coefficient, the device output decreases with the increase of the temperature. It is necessary to design a voltage reference which has the same temperature coefficient with the sensitivity of piezoresistive device to inhabit the temperature drift. The temperature coefficient of the designed voltage reference is calculated to be -2200ppm/°C and the output voltage is 1.5874v in room temperature, which can satisfy with the compensation requirements of the piezeresistive device.
{"title":"Design of Fixed Temperature Coefficient Bandgap Reference","authors":"T. Zhao, Dacheng Zhang","doi":"10.1109/EDSSC.2005.1635257","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635257","url":null,"abstract":"Since the sensitivity of a piezoresistive device has a large negative temperature coefficient, the device output decreases with the increase of the temperature. It is necessary to design a voltage reference which has the same temperature coefficient with the sensitivity of piezoresistive device to inhabit the temperature drift. The temperature coefficient of the designed voltage reference is calculated to be -2200ppm/°C and the output voltage is 1.5874v in room temperature, which can satisfy with the compensation requirements of the piezeresistive device.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133012781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635355
S. Hwang, S. Hong, Sang Won Park, Jee-Young Yoon, M. Sung
CMOS Read-Out IC (ROIC) for the micro Bolometer type Infrared Sensor is to estimate voltage or current when resistance in bolometer sensor varies as infrared light radiates. Implemented ROIC patterns cannot be exactly same with LAYOUT pattern CMOS Read-out IC process. Also each bolometer pixel resistance is variable by process variation in uncooled Infrared Sensor process. Bolometer sensor is not only heated by the incident IR, but also by current flowing through it, which generates the bias-heating noise. In this paper, we present CMOS Read-out IC which used a fully differential input stage to reduce process variation and bias heating noise problems. We designed and fabricated a prototype readout integrated circuit intended for uncooled bolometer infrared focal plane array. The design is demonstrated by the fabrication of a prototype consisting of an array of 32 x 32 pixels. The prototypes are fabricated in 0.25μm CMOS process.
微辐射热计型红外传感器的CMOS读出IC (ROIC)是当辐射热计传感器中的电阻随红外光辐射而变化时，估计电压或电流。实现的ROIC模式不能与布局模式CMOS读出IC工艺完全相同。在非制冷红外传感器过程中，每个热计像素电阻随工艺变化而变化。测热计传感器不仅受到入射红外线的加热，而且受到流过它的电流的加热，从而产生偏热噪声。在本文中，我们提出了CMOS读出集成电路，它使用全差分输入级来减少工艺变化和偏置加热噪声问题。设计并制作了一种用于非制冷热计红外焦平面阵列的读出集成电路原型。通过制造一个由32 x 32像素阵列组成的原型来证明该设计。原型机采用0.25μm CMOS工艺制造。
{"title":"A Noise Immunity Effective Read-Out Architecture for Uncooled Infrared Detector","authors":"S. Hwang, S. Hong, Sang Won Park, Jee-Young Yoon, M. Sung","doi":"10.1109/EDSSC.2005.1635355","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635355","url":null,"abstract":"CMOS Read-Out IC (ROIC) for the micro Bolometer type Infrared Sensor is to estimate voltage or current when resistance in bolometer sensor varies as infrared light radiates. Implemented ROIC patterns cannot be exactly same with LAYOUT pattern CMOS Read-out IC process. Also each bolometer pixel resistance is variable by process variation in uncooled Infrared Sensor process. Bolometer sensor is not only heated by the incident IR, but also by current flowing through it, which generates the bias-heating noise. In this paper, we present CMOS Read-out IC which used a fully differential input stage to reduce process variation and bias heating noise problems. We designed and fabricated a prototype readout integrated circuit intended for uncooled bolometer infrared focal plane array. The design is demonstrated by the fabrication of a prototype consisting of an array of 32 x 32 pixels. The prototypes are fabricated in 0.25μm CMOS process.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115186674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635390
Wenwei Yang, Guoxuan Qin, X. Shao, Zhiping Yu, L. Tian
The mechanical stress induced by shallow trench isolation (STI) signifilcantly affects the device behavior in the advanced CMOS technology. This paper presents an STI-dependent gate-induced drain leakage (GIDL) model and investigates the physical mechanisms in this phenomenon. Our simulation indicates that STI-induced compressive stress causes energy band gap narrowing. As a consequence, the effective tunneling barrier height becomes lower and intrinsic carrier concentration increases. These two factors enhance band-to-band tunneling (BBT) and trap-assisted tunneling (TAT), respectively. And an asymmetric layout is proposed to reduce the GIDL current.
{"title":"Analysis of GIDL Dependence on STI-induced Mechanical Stress","authors":"Wenwei Yang, Guoxuan Qin, X. Shao, Zhiping Yu, L. Tian","doi":"10.1109/EDSSC.2005.1635390","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635390","url":null,"abstract":"The mechanical stress induced by shallow trench isolation (STI) signifilcantly affects the device behavior in the advanced CMOS technology. This paper presents an STI-dependent gate-induced drain leakage (GIDL) model and investigates the physical mechanisms in this phenomenon. Our simulation indicates that STI-induced compressive stress causes energy band gap narrowing. As a consequence, the effective tunneling barrier height becomes lower and intrinsic carrier concentration increases. These two factors enhance band-to-band tunneling (BBT) and trap-assisted tunneling (TAT), respectively. And an asymmetric layout is proposed to reduce the GIDL current.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115411240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635289
Zhi-Yuan Cui, J. Liou
Continuing down scaling in CMOS technology has resulted in an increasing and urgent need for a Spice-like reliability model that is capable of predicting the long-term degradation of MOS devices and ICs. In this paper, we develop such a model based on the industry standard BSIM3 model and empirical degradation expressions for the threshold voltage and mobility of MOSFETs. The model is implemented in Cadence Spectre via Verilog-A, and measured data obtained from devices fabricated from the 0.18-μm CMOS technology have been included in support of the model development.
{"title":"A Compact Model for Reliability Simulation of Deep-Submicron MOS Devices and Circuits","authors":"Zhi-Yuan Cui, J. Liou","doi":"10.1109/EDSSC.2005.1635289","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635289","url":null,"abstract":"Continuing down scaling in CMOS technology has resulted in an increasing and urgent need for a Spice-like reliability model that is capable of predicting the long-term degradation of MOS devices and ICs. In this paper, we develop such a model based on the industry standard BSIM3 model and empirical degradation expressions for the threshold voltage and mobility of MOSFETs. The model is implemented in Cadence Spectre via Verilog-A, and measured data obtained from devices fabricated from the 0.18-μm CMOS technology have been included in support of the model development.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122413228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635328
B. Fong, A. Fong, G. Hong
This paper presents a system on chip architecture for mobile telemedicine systems utilizing a wireless local area network at 5 GHz. The chip is designed to perform demodulation and filtering functions that supports a data throughput rate of 50 Mbps and is integrated in a wideband compressive receiver with very high mobility that supports paramedics attending an accident scene. It utilizes an adjustable on-chip clocking circuitry with external dynamic random access memory.
{"title":"A Low Power Receiver Architecture for Mobile Biomedicine Systems","authors":"B. Fong, A. Fong, G. Hong","doi":"10.1109/EDSSC.2005.1635328","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635328","url":null,"abstract":"This paper presents a system on chip architecture for mobile telemedicine systems utilizing a wireless local area network at 5 GHz. The chip is designed to perform demodulation and filtering functions that supports a data throughput rate of 50 Mbps and is integrated in a wideband compressive receiver with very high mobility that supports paramedics attending an accident scene. It utilizes an adjustable on-chip clocking circuitry with external dynamic random access memory.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123722856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635318
Y. Tiao, Meng-Lieh Sheu, Yen-Po Chen
This paper presents a circuit design of ground referenced low voltage differential signal (GLVDS) I/O interface operating at 1 Gb/s. A GLVS transmitter /receiver chip is realized by using TSMC 3.3V 0.35μm 2P4M CMOS process, and its core size is 185μm*85μm.
{"title":"lGb/s Ground Referenced Low Voltage Differential Signal I/O Interface in 0.35μm CMOS","authors":"Y. Tiao, Meng-Lieh Sheu, Yen-Po Chen","doi":"10.1109/EDSSC.2005.1635318","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635318","url":null,"abstract":"This paper presents a circuit design of ground referenced low voltage differential signal (GLVDS) I/O interface operating at 1 Gb/s. A GLVS transmitter /receiver chip is realized by using TSMC 3.3V 0.35μm 2P4M CMOS process, and its core size is 185μm*85μm.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117038480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635290
J. Kuo, C. Hsu, C.P. Yang
This paper reports the gate-misalignment-effect related capacitance behavior of a 100nm double-gate (DG) fully-depleted (FD) SOI NMOS device with the n+p+poly top/bottom gate. Based on the 2D simulation result, with the gate misalignment, the sudden fall in the gate-drain/source capacitance (CGD/CGS) of the device at VG=0.5V is mitigated due to the reduced hole accumulation/ depletion in the bottom channel controlled by the p+bottom gate with the increased fringing electric field effect.
本文报道了带有n+p+聚顶/底栅极的100nm双栅(DG)满耗尽(FD) SOI NMOS器件的栅极失调效应相关电容行为。二维仿真结果表明，当栅极错位时，器件在VG=0.5V时的栅极-漏极/源极电容(CGD/CGS)的突然下降得到了缓解，这是由于p+底栅极控制的底沟道空穴积累/耗尽减少，边缘电场效应增强。
{"title":"Gate-Misalignment-Effect Related Capacitance Behavior of a 100nm Double-Gate FD SOI NMOS Device with n+/p+Poly Top/Bottom Gate","authors":"J. Kuo, C. Hsu, C.P. Yang","doi":"10.1109/EDSSC.2005.1635290","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635290","url":null,"abstract":"This paper reports the gate-misalignment-effect related capacitance behavior of a 100nm double-gate (DG) fully-depleted (FD) SOI NMOS device with the n<sup>+</sup>p<sup>+</sup>poly top/bottom gate. Based on the 2D simulation result, with the gate misalignment, the sudden fall in the gate-drain/source capacitance (C<inf>GD</inf>/C<inf>GS</inf>) of the device at V<inf>G</inf>=0.5V is mitigated due to the reduced hole accumulation/ depletion in the bottom channel controlled by the p<sup>+</sup>bottom gate with the increased fringing electric field effect.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116718822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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