Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635313
N. Liu, Y. R. Li, LH. Deng, Y. S. Sun, X. Zhou, H. J. Wu
The photoluminescence properties of ZnO single-crystal microtubes grown on Si substrate by hydrothermal method were investigated. An anomalous Z-shaped red-shift was found in the photoluminescence spectra, implying a new temperature switch characteristics. These results are considered to be from the competition among three kinds of excitons, which are localized excitons due to trapping in the intrinsic impurities and interface states at low temperatures; localized excitons and bound from thermally activated and transferred into bound states at intermediate temperatures; and, free excitons and unknown exciton complexes by thermal energy (kT) transfer part of the bound excitons into free excitons at high temperatures. As a result, free excitonsand interface states-excitons strongly overlaped.
{"title":"Investigation of Z-shaped Photoluminescence of Exciton in ZnO Single-crystal Microtubes","authors":"N. Liu, Y. R. Li, LH. Deng, Y. S. Sun, X. Zhou, H. J. Wu","doi":"10.1109/EDSSC.2005.1635313","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635313","url":null,"abstract":"The photoluminescence properties of ZnO single-crystal microtubes grown on Si substrate by hydrothermal method were investigated. An anomalous Z-shaped red-shift was found in the photoluminescence spectra, implying a new temperature switch characteristics. These results are considered to be from the competition among three kinds of excitons, which are localized excitons due to trapping in the intrinsic impurities and interface states at low temperatures; localized excitons and bound from thermally activated and transferred into bound states at intermediate temperatures; and, free excitons and unknown exciton complexes by thermal energy (kT) transfer part of the bound excitons into free excitons at high temperatures. As a result, free excitonsand interface states-excitons strongly overlaped.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133725029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635400
B. Mazhari, M. Sinha, J. Dixit
We propose use of heterostructures in PIN rectifiler diodes for obtaining faster switching speed. It is shown that by employing a small bandgap material in the heavily doped P layer and a wide bandgap material in the intrinsic region, reverse recovery time can be significantly lowered without compromising either the breakdown or the forward ON voltage.
{"title":"Heterostructure PIN Rectifier Diode For Power Applications","authors":"B. Mazhari, M. Sinha, J. Dixit","doi":"10.1109/EDSSC.2005.1635400","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635400","url":null,"abstract":"We propose use of heterostructures in PIN rectifiler diodes for obtaining faster switching speed. It is shown that by employing a small bandgap material in the heavily doped P layer and a wide bandgap material in the intrinsic region, reverse recovery time can be significantly lowered without compromising either the breakdown or the forward ON voltage.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132129639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635253
Jin He, Zhang Xing, Yangyuan Wang
A complete carrier-based non-charge-sheet analytic model for nano-scale undoped symmetric doublegate MOSFETs is presented in this paper. The formulation is based on the Poisson's equation to solve for the carrier (electron) concentration directly rather than relying on the surface potential alone. Therefore, the distribution of the potential, the field, and the charge density in the channel away from the surface is also expressed in terms of the carrier concentration, giving a complete carrier-based noncharge-sheet model for nano-scale undoped symmetric double-gate MOSFETs including the short-channel effects. The model formulation has an analytic form that does not need to solve for the transcendent equation as in the conventional surface potential model or classical Pao-Sah formulation. As a result, the model can analytically predict the analytical I-V and C-V characteristics of the undoped symmetric double-gate MOSFETs. The validity of the model results has also been demonstrated by the extensive comparison with the 2-D numerical simulation and experimental data.
{"title":"A Complete Carrier-Based Non-Charge-Sheet Analytic Model for Nano-Scale Undoped Symmetric Double-Gate MOSFETs","authors":"Jin He, Zhang Xing, Yangyuan Wang","doi":"10.1109/EDSSC.2005.1635253","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635253","url":null,"abstract":"A complete carrier-based non-charge-sheet analytic model for nano-scale undoped symmetric doublegate MOSFETs is presented in this paper. The formulation is based on the Poisson's equation to solve for the carrier (electron) concentration directly rather than relying on the surface potential alone. Therefore, the distribution of the potential, the field, and the charge density in the channel away from the surface is also expressed in terms of the carrier concentration, giving a complete carrier-based noncharge-sheet model for nano-scale undoped symmetric double-gate MOSFETs including the short-channel effects. The model formulation has an analytic form that does not need to solve for the transcendent equation as in the conventional surface potential model or classical Pao-Sah formulation. As a result, the model can analytically predict the analytical I-V and C-V characteristics of the undoped symmetric double-gate MOSFETs. The validity of the model results has also been demonstrated by the extensive comparison with the 2-D numerical simulation and experimental data.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134536734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635379
J. Fang, Z.W. Liu, Z.M. Chen, L.T. Liu, Z.J. Li
An Integrated Planar LC LPF(Low-Pass Filter) is designed and fabricated with Modified Surface Micromachining. The LPF is accomplished on low-resistance silicon substrate. To increase the performance of the filter, the substrate underneath the devices is modified with OPS (oxided porous silicon) technology. Measurement results give -3dB bandwidth of 2.925GHz and midband insertion loss of 0.874dB at 500MHz.
{"title":"Realization of an Integrated Planar LC Low-Pass Filter with Modified Surface Micromachining Technology","authors":"J. Fang, Z.W. Liu, Z.M. Chen, L.T. Liu, Z.J. Li","doi":"10.1109/EDSSC.2005.1635379","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635379","url":null,"abstract":"An Integrated Planar LC LPF(Low-Pass Filter) is designed and fabricated with Modified Surface Micromachining. The LPF is accomplished on low-resistance silicon substrate. To increase the performance of the filter, the substrate underneath the devices is modified with OPS (oxided porous silicon) technology. Measurement results give -3dB bandwidth of 2.925GHz and midband insertion loss of 0.874dB at 500MHz.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133069686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635327
Bao-jun Zhang, Yin-Tang Yang, Hai-jun Zhang
A CMOS fully differential integrator based on quasi-floating gate technique is proposed. Its detailed structure, transfer characteristic and integral performance are analyzed. Using the integrator circuit, a fully balanced fifth-order Chebyshev low-pass filter, which have a 2MHz cutoff frequency and 346.1μW power dissipation, is designed by the RLC ladder simulation method. Theoretical analysis and the feasibility of the filter have been verified by the simulation results.
{"title":"A Fully Balanced Fifth-Order Low-Pass Chebyshev Filter Based On Quasi-Floating Gate Transistors","authors":"Bao-jun Zhang, Yin-Tang Yang, Hai-jun Zhang","doi":"10.1109/EDSSC.2005.1635327","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635327","url":null,"abstract":"A CMOS fully differential integrator based on quasi-floating gate technique is proposed. Its detailed structure, transfer characteristic and integral performance are analyzed. Using the integrator circuit, a fully balanced fifth-order Chebyshev low-pass filter, which have a 2MHz cutoff frequency and 346.1μW power dissipation, is designed by the RLC ladder simulation method. Theoretical analysis and the feasibility of the filter have been verified by the simulation results.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133371440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635391
W. Lau, K. See, C. Eng, W. K. Awl, K. Jo, K. Tee, J.Y. Lee, E. Quek, H. Kim, S.T.H. Chan, L. Chan
NMOS surface-channel transistors using shallow trench isolation (STI) is known to show reverse narrow width effect (RNWE) such that the threshold voltage becomes smaller when the channel width decreases. We found that by using a phosphorus deep S/D implant in addition to an arsenic deep S/D implant, the threshold voltage first becomes larger when the channel width decreases and then later becomes smaller when the channel width further decreases for NMOS transistors with very small gate lengths. We attribute such an anomalous narrow width effect to an enhancement of TED due to Si interstitials generated by the phosphorus implant. PMOS transistors show up a much stronger anomalous narrow width effect compared to NMOS transistors. We attribute such an anomalous narrow width effect to an enhancement of phosphorus and arsenic TED due to Si interstitials generated by the deep boron S/D implant.
{"title":"Anomalous Narrow Width Effect in NMOS and PMOS Surface Channel Transistors Using Shallow Trench Isolation","authors":"W. Lau, K. See, C. Eng, W. K. Awl, K. Jo, K. Tee, J.Y. Lee, E. Quek, H. Kim, S.T.H. Chan, L. Chan","doi":"10.1109/EDSSC.2005.1635391","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635391","url":null,"abstract":"NMOS surface-channel transistors using shallow trench isolation (STI) is known to show reverse narrow width effect (RNWE) such that the threshold voltage becomes smaller when the channel width decreases. We found that by using a phosphorus deep S/D implant in addition to an arsenic deep S/D implant, the threshold voltage first becomes larger when the channel width decreases and then later becomes smaller when the channel width further decreases for NMOS transistors with very small gate lengths. We attribute such an anomalous narrow width effect to an enhancement of TED due to Si interstitials generated by the phosphorus implant. PMOS transistors show up a much stronger anomalous narrow width effect compared to NMOS transistors. We attribute such an anomalous narrow width effect to an enhancement of phosphorus and arsenic TED due to Si interstitials generated by the deep boron S/D implant.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125675186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635277
S. Hosaka, H. Sano, A. Miyachi, K. Itoh, H. Sone
Fabrication of ultrahigh packed pit and dot arrays have been studied using conventional electron beam (EB) writing, and positive and negative EB resists, ZEP520 and calixarene, respectively. Using fine electron beam with high probe current and very thinner resists, we demonstrate that the negative resist has a potential to achieve an ultrahigh density storage with both bit pitch (BP) and track pitch (TP) of <30 nm and a dot diameter of <15 nm, although the positive resist has a limitation at a BP of 60nm and a TP of 40nm. This dot array opens a way toward >1 trillion bits per inch2(Tb/in2) storage technology.
{"title":"Formation of very fine pit and dot arrays using EB writing for ultrahigh density storage toward 1 Tb/in2","authors":"S. Hosaka, H. Sano, A. Miyachi, K. Itoh, H. Sone","doi":"10.1109/EDSSC.2005.1635277","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635277","url":null,"abstract":"Fabrication of ultrahigh packed pit and dot arrays have been studied using conventional electron beam (EB) writing, and positive and negative EB resists, ZEP520 and calixarene, respectively. Using fine electron beam with high probe current and very thinner resists, we demonstrate that the negative resist has a potential to achieve an ultrahigh density storage with both bit pitch (BP) and track pitch (TP) of <30 nm and a dot diameter of <15 nm, although the positive resist has a limitation at a BP of 60nm and a TP of 40nm. This dot array opens a way toward >1 trillion bits per inch2(Tb/in2) storage technology.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133531789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635374
Chi Lok Wong, H. Ho, K. Lei, W. Li, K. Chan, W. Law, Shu-yuen Wu, S. Kong, Chinlon Lin
The integration between 2D SPR differential phase imaging sensor and microfluidic flow circuit is presented. It provides the advantages of high throughput, high sensitivity and label free detection to meet the present needs in biomechnical market. The differential phase scheme between p- and s- polarization enable elimination of all common-path phase noise while keeping the phase change caused by SPR effect. System sensitivity of the detection sensitivity of our setup is 0.44μg /ml is obtained for salt / water mixture sensing. BSA antigen and antibody binding reaction detection is further demonstrated. The system shows the capability of simultaneous detection for both specific and non-specific binding reactions in a micro-chamber array.
{"title":"Two dimensional phase sensitive surface plasmon resonance biosensor array using microfluidic flow circuit platform","authors":"Chi Lok Wong, H. Ho, K. Lei, W. Li, K. Chan, W. Law, Shu-yuen Wu, S. Kong, Chinlon Lin","doi":"10.1109/EDSSC.2005.1635374","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635374","url":null,"abstract":"The integration between 2D SPR differential phase imaging sensor and microfluidic flow circuit is presented. It provides the advantages of high throughput, high sensitivity and label free detection to meet the present needs in biomechnical market. The differential phase scheme between p- and s- polarization enable elimination of all common-path phase noise while keeping the phase change caused by SPR effect. System sensitivity of the detection sensitivity of our setup is 0.44μg /ml is obtained for salt / water mixture sensing. BSA antigen and antibody binding reaction detection is further demonstrated. The system shows the capability of simultaneous detection for both specific and non-specific binding reactions in a micro-chamber array.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"755 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132706435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635246
T. Tong, Chih-An Lin, O. K. Jensen, J. Mikkelsen, T. Larsen
A low power RF multiplier with ultra-wide signal response band is presented for ultra-wide band system applications such as an UWB demodulator (FM-UWB) or RF-correlator (impulse-radio). The principle of operation and the bandwidth theory is presented and discussed. The practical circuit is implemented using a 0.25μm CMOS process from UMC. The test results show an average gain of 22.5dBV-1at 1.2 GHz and 20.8dBV-1at 3 GHz. Across a full bandwidth of more than 700 MHz the design provides high in-band gain flatness. The circuit consumes a total of 1.3 mA from a 2.5V supply. The total circuit area is 200μmx300μm.
{"title":"A 0.25μm CMOS Low Power RF Multiplier for Ultra-wide Band System Applications","authors":"T. Tong, Chih-An Lin, O. K. Jensen, J. Mikkelsen, T. Larsen","doi":"10.1109/EDSSC.2005.1635246","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635246","url":null,"abstract":"A low power RF multiplier with ultra-wide signal response band is presented for ultra-wide band system applications such as an UWB demodulator (FM-UWB) or RF-correlator (impulse-radio). The principle of operation and the bandwidth theory is presented and discussed. The practical circuit is implemented using a 0.25μm CMOS process from UMC. The test results show an average gain of 22.5dBV-1at 1.2 GHz and 20.8dBV-1at 3 GHz. Across a full bandwidth of more than 700 MHz the design provides high in-band gain flatness. The circuit consumes a total of 1.3 mA from a 2.5V supply. The total circuit area is 200μmx300μm.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132944189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635293
Tao Li, Zhiping Yu, Yan Wang, Lei Huang, Cailan Xiang
Negative differential resistance (NDR) characteristics in the current-voltage curve of a p-type Si/Si1-χGeχresonant tunnelling diode (RTD) are simulated with the quantum hydrodynamic (QHD) model. An integrated difference scheme including Schafetter-Gummel (SG) method, second upwind method and second-order central difference method is used to discretize the QHD equations, which maintains both accuracy and stability. This work is the first to simulate hole transport in RTD using the QHD model. Investigations of some structure modifications have been carried out. Analysis of the results indicates that both quantum barrier thickness and hole effective mass have an impact on NDR characteristics for Si/Si1-χGeχRTD. The simulated peak-to-valley current ratio (PVCR) of 1.14 at T=293K agrees quantitatively with the experimental result when x=0.23.
{"title":"Numerical Simulation of Negative Differential Resistance Characteristics in Si/Si1-χGeχRTD at Room Temperature","authors":"Tao Li, Zhiping Yu, Yan Wang, Lei Huang, Cailan Xiang","doi":"10.1109/EDSSC.2005.1635293","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635293","url":null,"abstract":"Negative differential resistance (NDR) characteristics in the current-voltage curve of a p-type Si/Si1-χGeχresonant tunnelling diode (RTD) are simulated with the quantum hydrodynamic (QHD) model. An integrated difference scheme including Schafetter-Gummel (SG) method, second upwind method and second-order central difference method is used to discretize the QHD equations, which maintains both accuracy and stability. This work is the first to simulate hole transport in RTD using the QHD model. Investigations of some structure modifications have been carried out. Analysis of the results indicates that both quantum barrier thickness and hole effective mass have an impact on NDR characteristics for Si/Si1-χGeχRTD. The simulated peak-to-valley current ratio (PVCR) of 1.14 at T=293K agrees quantitatively with the experimental result when x=0.23.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117177496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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