Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635204
Zhiqiang Gao, Mingyan Yu, Y. Ye, Jianguo Ma
A 2ndorder RF bandpass filter with high-Q active inductor using low-voltage is presented. In the filter, a design technique for a tunable high-Q CMOS active inductor operating in the wide RF-band is described. Simulated performance is presented showing that the center frequency of filter using a 0.25-um CMOS process can be operated at the 1.60G∼2.45GHz frequency band under a 1.8V power supply and quality factor is adjusted from 30∼200 when fc≈2.45GHz.
提出了一种低压高q有源电感的二阶射频带通滤波器。在滤波器中，描述了一种可调谐高q CMOS有源电感器的设计技术，该电感器工作在宽射频波段。仿真结果表明，在1.8V电源下，采用0.25 um CMOS工艺的滤波器的中心频率可工作在1.60G ~ 2.45GHz频段，当fc≈2.45GHz时，质量因子可从30 ~ 200调整。
{"title":"Wide Tuning Range of A CMOS RF Bandpass Filter For Wireless Applications","authors":"Zhiqiang Gao, Mingyan Yu, Y. Ye, Jianguo Ma","doi":"10.1109/EDSSC.2005.1635204","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635204","url":null,"abstract":"A 2ndorder RF bandpass filter with high-Q active inductor using low-voltage is presented. In the filter, a design technique for a tunable high-Q CMOS active inductor operating in the wide RF-band is described. Simulated performance is presented showing that the center frequency of filter using a 0.25-um CMOS process can be operated at the 1.60G∼2.45GHz frequency band under a 1.8V power supply and quality factor is adjusted from 30∼200 when fc≈2.45GHz.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121084388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635300
Yo‐Sheng Lin, Hsiao-Bin Liang, Yan-Ru Tzeng
In this paper, we propose a single-turn multiple-layer interlaced stacked transformer structure with nearly perfect magnetic-coupling factor (kIM∼ 1) using standard mixed-signal/RF CMOS (or BiCMOS) technology. A single-turn six-layer interlaced stacked transformer was implemented to demonstrate the proposed structure. Temperature dependence (from -25 °C to 175°C) of the quality-factor (Q-factor), kIm, resistive-coupling factor (kRe), maximum available power gain (GAmax), and minimum noise figure (NFmin) performances of the transformer are reported. State-of-the-art GAmaxof 0.762 and 0.904 (i.e. NFminof 1.181 dB and 0.437 dB) have been achieved at 5.2 GHz and 8 GHz, respectively, at room temperature, mainly due to the perfect magnetic-coupling factor and the high resistive-coupling factor. The present analysis is helpful for RF engineers to design ultra-low-voltage high-performance transformer-feedback LNAs and VCOs, and other RF-ICs which include transformers.
{"title":"Implementation of Perfect-Magnetic-Coupling Ultra-Low-Loss Transformer in Standard RFCMOS Technology","authors":"Yo‐Sheng Lin, Hsiao-Bin Liang, Yan-Ru Tzeng","doi":"10.1109/EDSSC.2005.1635300","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635300","url":null,"abstract":"In this paper, we propose a single-turn multiple-layer interlaced stacked transformer structure with nearly perfect magnetic-coupling factor (kIM∼ 1) using standard mixed-signal/RF CMOS (or BiCMOS) technology. A single-turn six-layer interlaced stacked transformer was implemented to demonstrate the proposed structure. Temperature dependence (from -25 °C to 175°C) of the quality-factor (Q-factor), kIm, resistive-coupling factor (kRe), maximum available power gain (GAmax), and minimum noise figure (NFmin) performances of the transformer are reported. State-of-the-art GAmaxof 0.762 and 0.904 (i.e. NFminof 1.181 dB and 0.437 dB) have been achieved at 5.2 GHz and 8 GHz, respectively, at room temperature, mainly due to the perfect magnetic-coupling factor and the high resistive-coupling factor. The present analysis is helpful for RF engineers to design ultra-low-voltage high-performance transformer-feedback LNAs and VCOs, and other RF-ICs which include transformers.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116053740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635350
N. Chen, Hongchin Lin, N. Chen, R. Wu, T. Chou, H. Chien
Low cost is the trend for consumer electronics. However, the challenges of the LCD-TV processor using cost-effective two-layer ball grid array (BGA) packages suffer from serious crosstalk and return loss due to lack of a solid plane to suppress the coupling effect and control the trace impedance. Two types of two-layer BGA packages were measured and simulated using a 3D full-wave electromagnetic field solver and an EM-based 3D parasitic extractor to analyze their speed limitations and power coupling between the signals and the power net. The results indicated the signal coupling is the dominant factor for insertion loss. Thus, the design guidelines and specifications using two-layer BGA packages are proposed for development of the next generation processors.
{"title":"Integration Design of Chip and Package for Cost-Effective High-Speed Applications","authors":"N. Chen, Hongchin Lin, N. Chen, R. Wu, T. Chou, H. Chien","doi":"10.1109/EDSSC.2005.1635350","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635350","url":null,"abstract":"Low cost is the trend for consumer electronics. However, the challenges of the LCD-TV processor using cost-effective two-layer ball grid array (BGA) packages suffer from serious crosstalk and return loss due to lack of a solid plane to suppress the coupling effect and control the trace impedance. Two types of two-layer BGA packages were measured and simulated using a 3D full-wave electromagnetic field solver and an EM-based 3D parasitic extractor to analyze their speed limitations and power coupling between the signals and the power net. The results indicated the signal coupling is the dominant factor for insertion loss. Thus, the design guidelines and specifications using two-layer BGA packages are proposed for development of the next generation processors.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115354797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635304
Shun Yao, Xiaobo Wu, Xiaolang Yan
One of the possible solutions to the low voltage applications of modern integrated circuit, which was widely demanded by recently developed submicron CMOS technology, is the bootstrapped switch technique. In order to overcome its drawbacks such like the reliability issue on the main signal switch during the clock transition, three different approaches were proposed in this paper along with the simulation results. The oxide lifetime can benefit from these modifications without much circuit degradation.
{"title":"Modifications for Reliability of Bootstrapped Switches in Low Voltage Switched-Capacitor Circuits","authors":"Shun Yao, Xiaobo Wu, Xiaolang Yan","doi":"10.1109/EDSSC.2005.1635304","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635304","url":null,"abstract":"One of the possible solutions to the low voltage applications of modern integrated circuit, which was widely demanded by recently developed submicron CMOS technology, is the bootstrapped switch technique. In order to overcome its drawbacks such like the reliability issue on the main signal switch during the clock transition, three different approaches were proposed in this paper along with the simulation results. The oxide lifetime can benefit from these modifications without much circuit degradation.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128299167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635195
X. Guan, Zhiping Yu
The Tight-Binding (TB) model has been applied to investigate the bandstructures for semiconductor nanowires. With a specific implementation of SP3d5s* in the TB method, the orientation dependence of nanowire bandstructures can be quickly and accurately evaluated. It is found that while most axial directions of nanowires preserve the indirect band gap of bulk silicon, particular orientation can render direct band gap feature. In this paper, a [112] oriented silicon nanowire has been simulated using supercell approach and compared to the available measured data. The good agreement shows the proposed method is highy reliable and efficient.
{"title":"Orientation-Dependent Energy Bandstructure Calculation for Silicon Nanowires Using Supercell Approach with the Tight-Binding Method","authors":"X. Guan, Zhiping Yu","doi":"10.1109/EDSSC.2005.1635195","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635195","url":null,"abstract":"The Tight-Binding (TB) model has been applied to investigate the bandstructures for semiconductor nanowires. With a specific implementation of SP3d5s* in the TB method, the orientation dependence of nanowire bandstructures can be quickly and accurately evaluated. It is found that while most axial directions of nanowires preserve the indirect band gap of bulk silicon, particular orientation can render direct band gap feature. In this paper, a [112] oriented silicon nanowire has been simulated using supercell approach and compared to the available measured data. The good agreement shows the proposed method is highy reliable and efficient.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125559269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635340
Zhang Ya-cong, Chen Zhongjian, Lu Wengao, Gao Jun, Ji Lijiu, Zhao Baoying
A fast-settling, temperature-insensitive voltage buffer is analyzed and designed. Class AB output stage in the buffer leads to high slew rate with relatively low power dissipation. The current switch not only sets the quiescent current of the output transistors, but also compensates the variation of Vth with temperature, which makes the buffer workable in a wide range of temperature. Simulation results show that the 0.1% settling time with 2V input step and 2OpF load is always less than 165ns when the temperature varies from 0°C to 100°C while the dissipation is less than 3mW. The die area without pads in 0.5um CMOS process is 350* 150um2.
{"title":"A Fast-settling Temperature-Insensitive Voltage Buffer","authors":"Zhang Ya-cong, Chen Zhongjian, Lu Wengao, Gao Jun, Ji Lijiu, Zhao Baoying","doi":"10.1109/EDSSC.2005.1635340","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635340","url":null,"abstract":"A fast-settling, temperature-insensitive voltage buffer is analyzed and designed. Class AB output stage in the buffer leads to high slew rate with relatively low power dissipation. The current switch not only sets the quiescent current of the output transistors, but also compensates the variation of Vth with temperature, which makes the buffer workable in a wide range of temperature. Simulation results show that the 0.1% settling time with 2V input step and 2OpF load is always less than 165ns when the temperature varies from 0°C to 100°C while the dissipation is less than 3mW. The die area without pads in 0.5um CMOS process is 350* 150um2.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125785329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635199
Yuhua Cheng
As the semiconductor industry continually drives our life into 21st century with increased productivity and improved convenience throughout the economy, both foundries and EDA vendors are heavily investing in developing the technology platform for nano-scale and RF technologies, in order to support the significantly increased demand for compact, low cost, and low power IC design. With a lot of fundamentals to be understood and a lot of technical barriers to be overcome in process technologies, device modeling advanced design methodologies, and system architecture, this technology platform is becoming crucial in providing an accurate and efficient design environment for RF SoC design. This paper will try to outline this technology platform and review in general device modeling and its role as a foundation of the advanced technology platform for RF SoC design.
{"title":"Technology Platform Based On Comprehensive Device Modeling For RF SoC Design","authors":"Yuhua Cheng","doi":"10.1109/EDSSC.2005.1635199","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635199","url":null,"abstract":"As the semiconductor industry continually drives our life into 21st century with increased productivity and improved convenience throughout the economy, both foundries and EDA vendors are heavily investing in developing the technology platform for nano-scale and RF technologies, in order to support the significantly increased demand for compact, low cost, and low power IC design. With a lot of fundamentals to be understood and a lot of technical barriers to be overcome in process technologies, device modeling advanced design methodologies, and system architecture, this technology platform is becoming crucial in providing an accurate and efficient design environment for RF SoC design. This paper will try to outline this technology platform and review in general device modeling and its role as a foundation of the advanced technology platform for RF SoC design.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114075526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635255
M. Reyboz, O. Rozeau, T. Poiroux, P. Martín, G. Lecarval, J. Jomaah
This paper provides an explicit analytical charge-based model of Asymmetrical Double Gate (ADG) MOSFET. Its is based on Poisson equation resolution and field continuity equations, and gives explicit analytical expressions of the inversion charge and the drain current considering a long undoped transistor. There are no charge-sheet approximation and no fitting parameter. Consequently, this is a fully analytical and predictive model allowing to describe planar DG MOSFET as well as FinFET. The validity of this model is demonstrated by comparisons with Atlas simulations.
{"title":"Explicit Analytical Charge-Based Model of Asymmetrical Double Gate MOSFET","authors":"M. Reyboz, O. Rozeau, T. Poiroux, P. Martín, G. Lecarval, J. Jomaah","doi":"10.1109/EDSSC.2005.1635255","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635255","url":null,"abstract":"This paper provides an explicit analytical charge-based model of Asymmetrical Double Gate (ADG) MOSFET. Its is based on Poisson equation resolution and field continuity equations, and gives explicit analytical expressions of the inversion charge and the drain current considering a long undoped transistor. There are no charge-sheet approximation and no fitting parameter. Consequently, this is a fully analytical and predictive model allowing to describe planar DG MOSFET as well as FinFET. The validity of this model is demonstrated by comparisons with Atlas simulations.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121927166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635362
Hengfang Zhu, Xiaobo Wu, Xiaolang Yan
The power and area formulas for four popular Sinc-filter structures used in decimation filters were discussed in this paper. It was proved that the formulas are very useful in power or area estimation and comparison. The circuit implementations of each structure are illustrated. And the power and area comparisons of the four structures were simulated and analyzed. A further optimization technology for one of the efficient filter structures was also proposed.
{"title":"Low-Power and Hardware Efficient Decimation Filters in Sigma-Delta A/D Converters","authors":"Hengfang Zhu, Xiaobo Wu, Xiaolang Yan","doi":"10.1109/EDSSC.2005.1635362","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635362","url":null,"abstract":"The power and area formulas for four popular Sinc-filter structures used in decimation filters were discussed in this paper. It was proved that the formulas are very useful in power or area estimation and comparison. The circuit implementations of each structure are illustrated. And the power and area comparisons of the four structures were simulated and analyzed. A further optimization technology for one of the efficient filter structures was also proposed.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122895297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635314
R. Anand, A. Giri, R. Prasad
Polymer Light Emitting Diodes (PLEDs) and Organic Light Emitting Diodes (OLEDs) have made great progress in terms of efficiency, brightness and lifetimes during its last few years of development. The technology looks mature enough to produce real commercial products like high-resolution flat panel displays for cell phones, computers and televisions. However, it is also quite promising for low information content displays. In this work, the technology of low information content displays like 7-segment and simple billboard type of displays using polymer and small molecules has been developed. The processes, structures, characteristics and advantages of OLEDsand PLEDs over LCDs and inorganic LEDs are presented.
{"title":"Polymer and Small Molecules Light Emitting Diodes - A Technology for Large Area Low Information Contents Displays","authors":"R. Anand, A. Giri, R. Prasad","doi":"10.1109/EDSSC.2005.1635314","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635314","url":null,"abstract":"Polymer Light Emitting Diodes (PLEDs) and Organic Light Emitting Diodes (OLEDs) have made great progress in terms of efficiency, brightness and lifetimes during its last few years of development. The technology looks mature enough to produce real commercial products like high-resolution flat panel displays for cell phones, computers and televisions. However, it is also quite promising for low information content displays. In this work, the technology of low information content displays like 7-segment and simple billboard type of displays using polymer and small molecules has been developed. The processes, structures, characteristics and advantages of OLEDsand PLEDs over LCDs and inorganic LEDs are presented.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123064807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：