Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611284
Xufan Wu, Jun Yang, Longxing Shi
Inserting bus buffer is one significant method for solving the collisions in the microprocessor. And it is pivotal to determine the buffer size because of the performance and hardware resource constraints. This paper proposes a method for estimating the buffer size based on a prioritized M/G/1 queuing model and a high-level simulation model according to a RISC microprocessor. Both the results of queuing network model and the results of simulation model were found to be valuable. With the help of proposed simulation and estimating method, bus buffer size can be determined fast and accurately for the implementation
{"title":"Bus buffer modeling and optimization for a microprocessor","authors":"Xufan Wu, Jun Yang, Longxing Shi","doi":"10.1109/ICASIC.2005.1611284","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611284","url":null,"abstract":"Inserting bus buffer is one significant method for solving the collisions in the microprocessor. And it is pivotal to determine the buffer size because of the performance and hardware resource constraints. This paper proposes a method for estimating the buffer size based on a prioritized M/G/1 queuing model and a high-level simulation model according to a RISC microprocessor. Both the results of queuing network model and the results of simulation model were found to be valuable. With the help of proposed simulation and estimating method, bus buffer size can be determined fast and accurately for the implementation","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133776441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611364
Chunjiang Tu, Boan Liu, Hongyi Chen
A CMOS analog correlator designed using SMIC/spl reg/ 0.18/spl mu/m CMOS mixed and RF technology is proposed in this paper. The correlator is mainly composed of a Gilbert cell, common mode feedback (CMFB) circuit, capacitor load and buffer. The correlator can be used in the ultra wideband (UWB) receivers.
本文提出了一种采用SMIC/spl reg/ 0.18/spl μ m CMOS混合射频技术设计的CMOS模拟相关器。该相关器主要由吉尔伯特单元、共模反馈(CMFB)电路、电容负载和缓冲器组成。该相关器可用于超宽带(UWB)接收机。
{"title":"A CMOS correlator for UWB front-end circuit","authors":"Chunjiang Tu, Boan Liu, Hongyi Chen","doi":"10.1109/ICASIC.2005.1611364","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611364","url":null,"abstract":"A CMOS analog correlator designed using SMIC/spl reg/ 0.18/spl mu/m CMOS mixed and RF technology is proposed in this paper. The correlator is mainly composed of a Gilbert cell, common mode feedback (CMFB) circuit, capacitor load and buffer. The correlator can be used in the ultra wideband (UWB) receivers.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131901687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A low power content addressable memory is presented in this paper. Two-stage comparison is used to get good performance in TLB and the best low power structure is put forward based on the power model. Lower voltage swing is also applied to reduce the power dissipation. This circuit is implemented in 0.18 mum 1P6M CMOS process. Simulation results indicate that it only consumes 4.59 muw/bit with the maximum delay of 0.983 ns in a 64-entry TLB
本文提出了一种低功耗内容可寻址存储器。采用两级比较的方法获得了较好的TLB性能，并在功率模型的基础上提出了最佳的低功耗结构。此外，还采用了较低的电压摆幅来降低功耗。该电路采用0.18 μ m 1P6M CMOS工艺实现。仿真结果表明，在64入口的TLB中，它的功耗仅为4.59 muw/bit，最大延迟为0.983 ns
{"title":"Design of a high-speed low-power CAM","authors":"Canghai Gu, Hefei Zhu, Xiaofang Zhou, Hao Min, Dian Zhou","doi":"10.1109/ICASIC.2005.1611281","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611281","url":null,"abstract":"A low power content addressable memory is presented in this paper. Two-stage comparison is used to get good performance in TLB and the best low power structure is put forward based on the power model. Lower voltage swing is also applied to reduce the power dissipation. This circuit is implemented in 0.18 mum 1P6M CMOS process. Simulation results indicate that it only consumes 4.59 muw/bit with the maximum delay of 0.983 ns in a 64-entry TLB","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133464258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611238
Pengfei Zhang
RF-CMOS is considered more favorable primarily for the following two reasons: Firstly, capitalizing on the fabrication maturity and manufacture volume, one would justifiably expect the lowest possible cost. Secondly, it has undoubtedly the best potential for wireless system-on-chip (SOC) for its seamless compatibility with digital baseband circuit fabrication process. This paper reviewed system architectures of receiver design with emphasis on suitability of CMOS implementation. Circuit design issues for various building blocks in a typical receiver have been discussed. Finally, a design example of a 5-GHz receiver for WLAN application has been demonstrated
{"title":"CMOS RF receiver: from system architecture to circuit implementation","authors":"Pengfei Zhang","doi":"10.1109/ICASIC.2005.1611238","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611238","url":null,"abstract":"RF-CMOS is considered more favorable primarily for the following two reasons: Firstly, capitalizing on the fabrication maturity and manufacture volume, one would justifiably expect the lowest possible cost. Secondly, it has undoubtedly the best potential for wireless system-on-chip (SOC) for its seamless compatibility with digital baseband circuit fabrication process. This paper reviewed system architectures of receiver design with emphasis on suitability of CMOS implementation. Circuit design issues for various building blocks in a typical receiver have been discussed. Finally, a design example of a 5-GHz receiver for WLAN application has been demonstrated","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"300 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132742314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611437
S. C. Maruvada, A. Berkman, K. Krishnamoorthy, F. Balasa
This paper presents a novel algorithm for device-level analog placement with symmetry constraints. Based on the exploration of symmetric-feasible (S-F) binary tree representations (Balasa et al., 2004) of the layout, the novel approach employs 1-3 deterministic skip lists (Munro et al., 1992) and (Papadakis, 1993), exhibiting running times at least 20-30% better than previous (nonslicing) topological algorithms for analog placement, and significantly better (typically, over 100%) than more traditional approaches based on the absolute representation
提出了一种具有对称约束的器件级模拟放置算法。基于对布局的对称可行(S-F)二叉树表示(Balasa et al.， 2004)的探索，这种新方法采用了1-3个确定性跳跃表(Munro et al.， 1992)和(Papadakis, 1993)，在模拟放置方面，其运行时间至少比以前(非切片)拓扑算法好20-30%，并且比基于绝对表示的更传统的方法明显更好(通常超过100%)
{"title":"Deterministic skip lists in analog topological placement","authors":"S. C. Maruvada, A. Berkman, K. Krishnamoorthy, F. Balasa","doi":"10.1109/ICASIC.2005.1611437","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611437","url":null,"abstract":"This paper presents a novel algorithm for device-level analog placement with symmetry constraints. Based on the exploration of symmetric-feasible (S-F) binary tree representations (Balasa et al., 2004) of the layout, the novel approach employs 1-3 deterministic skip lists (Munro et al., 1992) and (Papadakis, 1993), exhibiting running times at least 20-30% better than previous (nonslicing) topological algorithms for analog placement, and significantly better (typically, over 100%) than more traditional approaches based on the absolute representation","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133618175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611301
Yu Qian, Wang Dong-hui, Zhang Tie-jun, Hou Chao-huan
Register file is needed to work in high speed for high performance superscalar processors to execute multiple parallel instructions. A 10-read 6-write write-through register file, customized in 1.8V 0.18mum CMOS technology, is introduced here, every port of which can be accessed individually. It comprises two arrays of modified 16-port memory cells, some low-power SCL decoders and a local clock generator, which is designed to enhance the range of working frequency. The results of the function verification and the performance analysis show that the register file can work in 500MHz with 46mW power consumption. The macro block's area is 0.19mm. It can meet the requirements of both high performance processors and embedded ones
{"title":"A design of 500MHz 10-read 6-write register file","authors":"Yu Qian, Wang Dong-hui, Zhang Tie-jun, Hou Chao-huan","doi":"10.1109/ICASIC.2005.1611301","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611301","url":null,"abstract":"Register file is needed to work in high speed for high performance superscalar processors to execute multiple parallel instructions. A 10-read 6-write write-through register file, customized in 1.8V 0.18mum CMOS technology, is introduced here, every port of which can be accessed individually. It comprises two arrays of modified 16-port memory cells, some low-power SCL decoders and a local clock generator, which is designed to enhance the range of working frequency. The results of the function verification and the performance analysis show that the register file can work in 500MHz with 46mW power consumption. The macro block's area is 0.19mm. It can meet the requirements of both high performance processors and embedded ones","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121055552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611489
Junhao Shi Gorschwin, Fey Rolf Drechsler, Andreas Glowatz, Juirgen Schloffel, F. Hapke
Due to the ever increasing size of integrated circuits classical methods for automatic test pattern generation (ATPG) reach their limits. On the other hand recent advances in algorithms to solve the Boolean satisfiability (SAT) problem allow the application to large instances. This suggests to exploit modern SAT techniques for ATPG. Here, we present a SAT-based ATPG tool that is applicable to large industrial circuits. The performances of different SAT-solvers are experimentally evaluated and the potential for problem specific heuristics is shown. Further experiments show that most of the faults can be classified very efficiently independently of the circuit size
{"title":"Experimental studies on SAT-based test pattern generation for industrial circuits","authors":"Junhao Shi Gorschwin, Fey Rolf Drechsler, Andreas Glowatz, Juirgen Schloffel, F. Hapke","doi":"10.1109/ICASIC.2005.1611489","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611489","url":null,"abstract":"Due to the ever increasing size of integrated circuits classical methods for automatic test pattern generation (ATPG) reach their limits. On the other hand recent advances in algorithms to solve the Boolean satisfiability (SAT) problem allow the application to large instances. This suggests to exploit modern SAT techniques for ATPG. Here, we present a SAT-based ATPG tool that is applicable to large industrial circuits. The performances of different SAT-solvers are experimentally evaluated and the potential for problem specific heuristics is shown. Further experiments show that most of the faults can be classified very efficiently independently of the circuit size","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116138081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611391
Lai Xin-quan, Guo Jianping, Yu Weixue, Cao Yu
A new CMOS-compatible digital soft-start circuit for DC-DC switching regulator is presented in this paper, for which the technical is adopted to eliminate the inrush current and avoid the overshoot of the output voltage. It's fully integrated on chip, so that the external soft-start capacitor is not in need, which leads to the reduction of the required board space and component cost. Hspice simulation shows that, while the system has an output voltage of 1.5V at a load of 6A, the envelop of inductor current increases placidly at approximately 1.43A/ms and output voltage increases about 16mV every cycle
{"title":"A novel digital soft-start circuit for DC-DC switching regulator","authors":"Lai Xin-quan, Guo Jianping, Yu Weixue, Cao Yu","doi":"10.1109/ICASIC.2005.1611391","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611391","url":null,"abstract":"A new CMOS-compatible digital soft-start circuit for DC-DC switching regulator is presented in this paper, for which the technical is adopted to eliminate the inrush current and avoid the overshoot of the output voltage. It's fully integrated on chip, so that the external soft-start capacitor is not in need, which leads to the reduction of the required board space and component cost. Hspice simulation shows that, while the system has an output voltage of 1.5V at a load of 6A, the envelop of inductor current increases placidly at approximately 1.43A/ms and output voltage increases about 16mV every cycle","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114914964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611458
Choonseung Lee, S. Ha
The cosynthesis problem addressed in this paper involves three subproblems: selection of appropriate processing elements, mapping and scheduling of function blocks to the selected processing elements, and schedulability analysis. We have presented a cosynthesis framework in our earlier work (Oh and Ha, 1999) that defines an iteration loop of three steps that attack the subproblems separately. Despite many good features, our previous technique has a severe restriction that a task monopolizes the entire system once activated. But in general we may obtain higher performance if multiple tasks can be running concurrently on different processor cores. It is the main contribution of this paper that we extend the previous framework to be applicable for general multiprocessor systems with diverse operating policies. We demonstrate the performance improvement from the proposed work with a multi-media real-time application, DVR system, and randomly generated multi-task graphs
本文研究的协同综合问题包括三个子问题:适当加工元素的选择、功能块到所选加工元素的映射和调度以及可调度性分析。我们在早期的工作(Oh and Ha, 1999)中提出了一个共合成框架，它定义了一个由三个步骤组成的迭代循环，分别攻击子问题。尽管我们以前的技术有很多好的特性，但它有一个严重的限制，即任务一旦被激活就会垄断整个系统。但一般来说，如果多个任务可以在不同的处理器内核上并发运行，我们可能会获得更高的性能。本文的主要贡献在于我们扩展了以前的框架，使其适用于具有不同操作策略的通用多处理器系统。我们通过多媒体实时应用程序、DVR系统和随机生成的多任务图演示了所提出的工作的性能改进
{"title":"Hardware-software cosynthesis of multitask MPSoCs with real-time constraints","authors":"Choonseung Lee, S. Ha","doi":"10.1109/ICASIC.2005.1611458","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611458","url":null,"abstract":"The cosynthesis problem addressed in this paper involves three subproblems: selection of appropriate processing elements, mapping and scheduling of function blocks to the selected processing elements, and schedulability analysis. We have presented a cosynthesis framework in our earlier work (Oh and Ha, 1999) that defines an iteration loop of three steps that attack the subproblems separately. Despite many good features, our previous technique has a severe restriction that a task monopolizes the entire system once activated. But in general we may obtain higher performance if multiple tasks can be running concurrently on different processor cores. It is the main contribution of this paper that we extend the previous framework to be applicable for general multiprocessor systems with diverse operating policies. We demonstrate the performance improvement from the proposed work with a multi-media real-time application, DVR system, and randomly generated multi-task graphs","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116551442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
3D integration is a potential solution to solve complex problem caused by interconnect delay that dominates the total budgets. In this placer, we bring up a 3D placement algorithm and focus on two issues: the effect of vertical channels and the constraint that cells can not leave the plane after assigned to it. Firstly, we develop an algorithm to verify the effect of vertical channels in wire length optimization. Secondly, because of the constraint presented above the placement quality is restricted badly. We research the possibility of improving placement quality by importing an initial solution. Experiments on a set of benchmarks prove our algorithm efficient and effective.
{"title":"3D placement algorithm considering vertical channels and guided by 2D placement solution","authors":"Guilin Liu, Zhuoyuan Li, Qiang Zhou, Xianlong Hong, Hannah Honghua Yang","doi":"10.1109/ICASIC.2005.1611446","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611446","url":null,"abstract":"3D integration is a potential solution to solve complex problem caused by interconnect delay that dominates the total budgets. In this placer, we bring up a 3D placement algorithm and focus on two issues: the effect of vertical channels and the constraint that cells can not leave the plane after assigned to it. Firstly, we develop an algorithm to verify the effect of vertical channels in wire length optimization. Secondly, because of the constraint presented above the placement quality is restricted badly. We research the possibility of improving placement quality by importing an initial solution. Experiments on a set of benchmarks prove our algorithm efficient and effective.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121451961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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