Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611387
Xiao Du, Wei-min Li, Xiao-fei Zhu, Xiao-dong Fu
A curvature-compensated current mode bandgap reference with improved PSRR is presented. The circuit takes advantage of a simplified straightforward implementation of the curvature compensation method, the reference achieves a temperature coefficient of 7ppm/ degC over the temperature range of -20degC to +80 degC. And by using negative feedback to generate a regulated supply, the power supply rejection ration (PSRR) of the proposed circuit can be increased up to 90dB at 10kHz.The circuit is designed using 0.8 mum BiCMOS technology and silicon area is 1.07 times 0.92 mm2
提出了一种改进PSRR的曲率补偿型电流模带隙基准电路。该电路利用曲率补偿方法的简化直接实现，基准温度系数在-20℃至+80℃的温度范围内达到7ppm/℃。通过使用负反馈产生稳压电源，该电路的电源抑制比(PSRR)在10kHz时可提高到90dB。电路采用0.8 μ m BiCMOS技术设计，硅面积为1.07 × 0.92 mm2
{"title":"A curvature-compensated bandgap reference with improved PSRR","authors":"Xiao Du, Wei-min Li, Xiao-fei Zhu, Xiao-dong Fu","doi":"10.1109/ICASIC.2005.1611387","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611387","url":null,"abstract":"A curvature-compensated current mode bandgap reference with improved PSRR is presented. The circuit takes advantage of a simplified straightforward implementation of the curvature compensation method, the reference achieves a temperature coefficient of 7ppm/ degC over the temperature range of -20degC to +80 degC. And by using negative feedback to generate a regulated supply, the power supply rejection ration (PSRR) of the proposed circuit can be increased up to 90dB at 10kHz.The circuit is designed using 0.8 mum BiCMOS technology and silicon area is 1.07 times 0.92 mm2","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122052818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611301
Yu Qian, Wang Dong-hui, Zhang Tie-jun, Hou Chao-huan
Register file is needed to work in high speed for high performance superscalar processors to execute multiple parallel instructions. A 10-read 6-write write-through register file, customized in 1.8V 0.18mum CMOS technology, is introduced here, every port of which can be accessed individually. It comprises two arrays of modified 16-port memory cells, some low-power SCL decoders and a local clock generator, which is designed to enhance the range of working frequency. The results of the function verification and the performance analysis show that the register file can work in 500MHz with 46mW power consumption. The macro block's area is 0.19mm. It can meet the requirements of both high performance processors and embedded ones
{"title":"A design of 500MHz 10-read 6-write register file","authors":"Yu Qian, Wang Dong-hui, Zhang Tie-jun, Hou Chao-huan","doi":"10.1109/ICASIC.2005.1611301","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611301","url":null,"abstract":"Register file is needed to work in high speed for high performance superscalar processors to execute multiple parallel instructions. A 10-read 6-write write-through register file, customized in 1.8V 0.18mum CMOS technology, is introduced here, every port of which can be accessed individually. It comprises two arrays of modified 16-port memory cells, some low-power SCL decoders and a local clock generator, which is designed to enhance the range of working frequency. The results of the function verification and the performance analysis show that the register file can work in 500MHz with 46mW power consumption. The macro block's area is 0.19mm. It can meet the requirements of both high performance processors and embedded ones","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121055552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611461
Shengtian Sang, Xiaoming Li, Y. Ye
By extending the baseline processor with application specific instructions, an application specific co-processor can meet the computational demands of the application. Working with the traditional co-processor interface, it doesn't require the extensible processor core and has least impact on the existing hardware and software. This paper proposes a framework for design space exploration and automatic co-processor instructions generation, in which application profiling, instruction identification and evaluation proceed seamlessly and iteratively. The optimal instruction set of the co-processor under given constraints is automatically generated from the source code of the application. To demonstrate the effectiveness of the method we generate the instruction set of a SPARC V8 co-processor for a VoIP application. The experiment gives promising results with the speedup of factor 2.3
{"title":"Automatic instruction generation for application specific co-processor","authors":"Shengtian Sang, Xiaoming Li, Y. Ye","doi":"10.1109/ICASIC.2005.1611461","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611461","url":null,"abstract":"By extending the baseline processor with application specific instructions, an application specific co-processor can meet the computational demands of the application. Working with the traditional co-processor interface, it doesn't require the extensible processor core and has least impact on the existing hardware and software. This paper proposes a framework for design space exploration and automatic co-processor instructions generation, in which application profiling, instruction identification and evaluation proceed seamlessly and iteratively. The optimal instruction set of the co-processor under given constraints is automatically generated from the source code of the application. To demonstrate the effectiveness of the method we generate the instruction set of a SPARC V8 co-processor for a VoIP application. The experiment gives promising results with the speedup of factor 2.3","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122681280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611432
Shengyan Hong, Pushan Tang, Jiarong Tong
In this paper, the new technology placement software for FPGA with bus resources is presented. This software, FPLACEMENT, can handle complex connection structure in the chip with a new cost function, while VPR fails to do it. Besides the FPLACEMENT has special part to deal with the bus resources in the chip. The test result of FPLACEMENT is presented to substantiate the feasibility of the software.
{"title":"FPLACEMENT: new placement software for FPGA with bus resources","authors":"Shengyan Hong, Pushan Tang, Jiarong Tong","doi":"10.1109/ICASIC.2005.1611432","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611432","url":null,"abstract":"In this paper, the new technology placement software for FPGA with bus resources is presented. This software, FPLACEMENT, can handle complex connection structure in the chip with a new cost function, while VPR fails to do it. Besides the FPLACEMENT has special part to deal with the bus resources in the chip. The test result of FPLACEMENT is presented to substantiate the feasibility of the software.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122825251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611431
Du Yuyuan
The basic structure and features of a 16-bit real time stack processor is introduced. The design and implementation method of the 16-bit stack processor is presented in the paper. The behavioral description and state machine description is applied to program design using VHDL. The 16-bit real time stack processor implemented by Spartan-II XC2S200 FPGA chip, and is successfully adopted in frequency spectrum controller system of MRI
{"title":"Design of a 16-bit real time stack processor in FPGA","authors":"Du Yuyuan","doi":"10.1109/ICASIC.2005.1611431","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611431","url":null,"abstract":"The basic structure and features of a 16-bit real time stack processor is introduced. The design and implementation method of the 16-bit stack processor is presented in the paper. The behavioral description and state machine description is applied to program design using VHDL. The 16-bit real time stack processor implemented by Spartan-II XC2S200 FPGA chip, and is successfully adopted in frequency spectrum controller system of MRI","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129935291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611245
S. Leibson
SOCs solve complex, data-intensive application problems by delivering high performance with good power-efficiency. Configurable, application-specific processor cores used as task blocks in an SOC deliver hardware-like performance and programmability, which reduces design effort and risk when compared to manual RTL block-design techniques.
{"title":"SOC logic development using configurable, application-specific processors","authors":"S. Leibson","doi":"10.1109/ICASIC.2005.1611245","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611245","url":null,"abstract":"SOCs solve complex, data-intensive application problems by delivering high performance with good power-efficiency. Configurable, application-specific processor cores used as task blocks in an SOC deliver hardware-like performance and programmability, which reduces design effort and risk when compared to manual RTL block-design techniques.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124523439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611296
Zhang Yu, Ling Ming, Pu Hanlai, Zhou Fan
The access operation between CPU and off-chip memory, such as SDRAM, is very frequent in embedded system. This being the case, we try to take full advantage of SDRAM by developing a novel SDRAM-controller architecture. The architecture is based on the SDRAM characteristics with full instruction flow analysis. Three techniques are employed for auto adaptive prefetch instruction, overlapping read latency, locality of reference and reduction of row miss mainly aroused by accessing stack data. The results using benchmark programs show that developed architecture reduce the memory latency by 71% on average
{"title":"Performance exploration and optimization of SDRAM-controller architecture on SDRAM access","authors":"Zhang Yu, Ling Ming, Pu Hanlai, Zhou Fan","doi":"10.1109/ICASIC.2005.1611296","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611296","url":null,"abstract":"The access operation between CPU and off-chip memory, such as SDRAM, is very frequent in embedded system. This being the case, we try to take full advantage of SDRAM by developing a novel SDRAM-controller architecture. The architecture is based on the SDRAM characteristics with full instruction flow analysis. Three techniques are employed for auto adaptive prefetch instruction, overlapping read latency, locality of reference and reduction of row miss mainly aroused by accessing stack data. The results using benchmark programs show that developed architecture reduce the memory latency by 71% on average","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120879189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A direct conversion receiver for WLAN 802.11b is presented in 0.18/spl mu/m CMOS technology. It contains a complete receiver chain with low noise amplifier, I/Q mixer, programmable gain amplifier and base band filter. A 4.8GHz divider is used to generate 2.4GHz quadrature clock for I/Q mixer. The reception path is dc coupled and a feed back low pass filter is added to reduce the dc-offset and 1/f noise. The noise figure of receiver is 5.2dB, the IIP3 is -14.5dBm at high gain setting. With the supply voltage of 1.8V, the over all power consummation is about 100mW. The chip area with pads is 2.6mm/spl times/2.5mm.
{"title":"A direct conversion WLAN receiver","authors":"Jingguang Wang, Jinju Wang, Yumei Huang, Weilun Shen, Xiaofeng Yi, Zhiliang Hong","doi":"10.1109/ICASIC.2005.1611341","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611341","url":null,"abstract":"A direct conversion receiver for WLAN 802.11b is presented in 0.18/spl mu/m CMOS technology. It contains a complete receiver chain with low noise amplifier, I/Q mixer, programmable gain amplifier and base band filter. A 4.8GHz divider is used to generate 2.4GHz quadrature clock for I/Q mixer. The reception path is dc coupled and a feed back low pass filter is added to reduce the dc-offset and 1/f noise. The noise figure of receiver is 5.2dB, the IIP3 is -14.5dBm at high gain setting. With the supply voltage of 1.8V, the over all power consummation is about 100mW. The chip area with pads is 2.6mm/spl times/2.5mm.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127217069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611275
C. Zang, S. Imai, S. Kimura
In modern microprocessors, the access time of register file becomes a critical part in total delay. Instruction level or thread level parallelism improves instructions per cycle (IPC) by executing multiple instructions in one cycle. Such multiple instructions need to read or write data from/to register files simultaneously. To satisfy that, register file with sufficient ports should be designed. However, the area and access time of register file with large ports will increase sharply. Duplicated register file (DupRF) architecture can reduce access time by distributing read ports. In this paper, we propose a new kind of DupRF architecture for embedded simultaneous multithreading (SMT) microprocessor and estimate the effect with respect to the area and access time. Especially, we measure the product of area and access time as computation cost. For a SMT microprocessor with 6 threads, 64-bit data-width and 6 function units, 3-duplicate register file architecture can reduce access time by 12.61% with a slight increase of computation cost by 3.35% compared with the central register file architecture
{"title":"Duplicated register file design for embedded simultaneous multithreading microprocessor","authors":"C. Zang, S. Imai, S. Kimura","doi":"10.1109/ICASIC.2005.1611275","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611275","url":null,"abstract":"In modern microprocessors, the access time of register file becomes a critical part in total delay. Instruction level or thread level parallelism improves instructions per cycle (IPC) by executing multiple instructions in one cycle. Such multiple instructions need to read or write data from/to register files simultaneously. To satisfy that, register file with sufficient ports should be designed. However, the area and access time of register file with large ports will increase sharply. Duplicated register file (DupRF) architecture can reduce access time by distributing read ports. In this paper, we propose a new kind of DupRF architecture for embedded simultaneous multithreading (SMT) microprocessor and estimate the effect with respect to the area and access time. Especially, we measure the product of area and access time as computation cost. For a SMT microprocessor with 6 threads, 64-bit data-width and 6 function units, 3-duplicate register file architecture can reduce access time by 12.61% with a slight increase of computation cost by 3.35% compared with the central register file architecture","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127219134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611315
Yizhen Zhang, Chao Xu, L. Chen
This paper presents a flexible dual-symbol coding arithmetic coder (MQ coder) architecture design for the parallel coding engines of embedded block coding with optimization truncation (EBCOT) tier-1 in JPEG2000. The flexible MQ coder (FMQ) can encode two symbols simultaneously per clock cycle by using the optimized combination method. It increases the throughput rate of the arithmetic coding, which can match the high throughput rate of the parallel context modeling modules. Experimental results show that one FMQ are able to handle two bit-planes/data-pairs for the bit-plane parallel EBCOT coding engine, and the computation time is decreased about 24% compared with the engine by using the regular MQ coder
{"title":"A dual-symbol coding arithmetic coder architecture design for high speed EBCOT coding engine in JPEG2000","authors":"Yizhen Zhang, Chao Xu, L. Chen","doi":"10.1109/ICASIC.2005.1611315","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611315","url":null,"abstract":"This paper presents a flexible dual-symbol coding arithmetic coder (MQ coder) architecture design for the parallel coding engines of embedded block coding with optimization truncation (EBCOT) tier-1 in JPEG2000. The flexible MQ coder (FMQ) can encode two symbols simultaneously per clock cycle by using the optimized combination method. It increases the throughput rate of the arithmetic coding, which can match the high throughput rate of the parallel context modeling modules. Experimental results show that one FMQ are able to handle two bit-planes/data-pairs for the bit-plane parallel EBCOT coding engine, and the computation time is decreased about 24% compared with the engine by using the regular MQ coder","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125216605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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