Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507115
R. Weerasekera, J. R. Cubillo, G. Katti
This paper describes the electrical characteristics of the fine pitch interconnects in silicon carrier systems. The characteristics of such interconnects are explored and a typical FPGA-memory system is compared viz-a-viz with a traditional PCB system from low data rates to higher data rates. Our case-study shows that even though highly resistive wires are used in silicon carrier the interconnects are SI robust due to the shorter die to die interconnect length and the absence of package parasitics.
{"title":"Analysis of signal integrity(SI) robustness in through-silicon interposer (TSI) interconnects","authors":"R. Weerasekera, J. R. Cubillo, G. Katti","doi":"10.1109/EPTC.2012.6507115","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507115","url":null,"abstract":"This paper describes the electrical characteristics of the fine pitch interconnects in silicon carrier systems. The characteristics of such interconnects are explored and a typical FPGA-memory system is compared viz-a-viz with a traditional PCB system from low data rates to higher data rates. Our case-study shows that even though highly resistive wires are used in silicon carrier the interconnects are SI robust due to the shorter die to die interconnect length and the absence of package parasitics.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127908703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507143
J. N. Tey, E. Kok, Haijing Lu, Jun Wei
Three carbon nanotubes post treatment methods were evaluated for their impacts on film conductivity. Acid treatment was found to be the most impactful treatment for conductivity improvement, with >3 times reduction in sheet resistance for long hour soaking in 9M sulfuric acid. Carbon nanotube sorting with agarose gel method for metallic single walled carbon nanotube enrichment also showed great improvement with ∼2.5 to 3 times reduction in sheet resistance by simply enhancing the % M-SWNT from 33% to 60%.
{"title":"Carbon nanotubes post processing methods for improved film conductivity","authors":"J. N. Tey, E. Kok, Haijing Lu, Jun Wei","doi":"10.1109/EPTC.2012.6507143","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507143","url":null,"abstract":"Three carbon nanotubes post treatment methods were evaluated for their impacts on film conductivity. Acid treatment was found to be the most impactful treatment for conductivity improvement, with >3 times reduction in sheet resistance for long hour soaking in 9M sulfuric acid. Carbon nanotube sorting with agarose gel method for metallic single walled carbon nanotube enrichment also showed great improvement with ∼2.5 to 3 times reduction in sheet resistance by simply enhancing the % M-SWNT from 33% to 60%.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"51 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134491038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507144
Y. Lim, Yee Mey Goh, Changqing Liu
Interest in body area networks (BAN) operating in the millimeter-wave regime (60 GHz) is increasing due to concerns over the security of data transfer. Obtaining low loss in the higher frequencies is important for high performance interconnects. In this paper, two materials deposition techniques — inkjet printing and stencil printing are being investigated for creating conductive traces on fabrics to enable high frequency (up to 20 GHz) applications. In the inkjet printing, various surface treatments were considered and utilized to improve the ink-substrate interaction for the enhancement of adhesion of the deposited structures. Finally the RF losses of printed microstrip lines using the above techniques were analyzed, compared against the copper traces which are conventionally achieved by etching process.
{"title":"RF performance of inkjet and stencil printed traces for flexible electronics applications","authors":"Y. Lim, Yee Mey Goh, Changqing Liu","doi":"10.1109/EPTC.2012.6507144","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507144","url":null,"abstract":"Interest in body area networks (BAN) operating in the millimeter-wave regime (60 GHz) is increasing due to concerns over the security of data transfer. Obtaining low loss in the higher frequencies is important for high performance interconnects. In this paper, two materials deposition techniques — inkjet printing and stencil printing are being investigated for creating conductive traces on fabrics to enable high frequency (up to 20 GHz) applications. In the inkjet printing, various surface treatments were considered and utilized to improve the ink-substrate interaction for the enhancement of adhesion of the deposited structures. Finally the RF losses of printed microstrip lines using the above techniques were analyzed, compared against the copper traces which are conventionally achieved by etching process.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"249 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130458176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507119
Mark Huang, C. Chu, F. Lim
In this paper, a new method is utilized to develop the hermetic thermoplastics through modification of conventional LCP resins. Thermoplastic materials are synthesized for producing a hermetic barrier with a cavity structure made based on the materials compositions: near-hermetic liquid crystalline polymers (LCP), nano-sized mineral fillers, adhesion promoters, compatibilizers, inorganic microparticles and anti-oxidants. Near-hermetic LCP is used as the matrix resin to provide robust mechanical strength, heat resistant stability and electrical insulation. Nano-sized mineral fillers with large aspect ratio are incorporated into LCP matrix resin to increase its hermeticity without sacrificing the outstanding performance of LCP resins and simultaneously reduce the coefficient of thermal expansion (CTE) of LCP resins. Adhesion promoters are added into the LCP resin systems in order to improve the bonding strength with metallic substrates (copper / alloy 42 lead frame etc.) that provide the electrical input/output (I/O) path to electronic packages. Compatibilizers are used to modify the above-mentioned LCP systems with potential multicomponent phase separation and hence (to the fullest) make use of the benefits from each component in the composites. Inorganic microparticles are optional to either solve the processability or promote the functionality of the hermetic LCP systems. The synthetic methods are based on the mechanical blending through injection molding process at an elevated temperature. Anti-oxidants are required to prevent the thermo-oxidative degradation in synthesis of modified LCP nano-composites and subsequent applications, for example, pre-molded cavity quad flat no-lead (QFN) packages. The as-formed LCP resin systems possess high hermetic performance which is comparable to electrical glass with excellent dimensional stability in a wide range of application, especially for advanced electronic packages such as the open cavity QFN substrates for MEMS packages. The hermeticity of 8.0∗ 10"11 atm-cc/s can be achieved. The adhesion of modified LCP to Ni/Pd/Au-coated copper lead frame can also meet the requirement for MEMS packaging.
{"title":"Development of hermetic LCP for electronic device packages","authors":"Mark Huang, C. Chu, F. Lim","doi":"10.1109/EPTC.2012.6507119","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507119","url":null,"abstract":"In this paper, a new method is utilized to develop the hermetic thermoplastics through modification of conventional LCP resins. Thermoplastic materials are synthesized for producing a hermetic barrier with a cavity structure made based on the materials compositions: near-hermetic liquid crystalline polymers (LCP), nano-sized mineral fillers, adhesion promoters, compatibilizers, inorganic microparticles and anti-oxidants. Near-hermetic LCP is used as the matrix resin to provide robust mechanical strength, heat resistant stability and electrical insulation. Nano-sized mineral fillers with large aspect ratio are incorporated into LCP matrix resin to increase its hermeticity without sacrificing the outstanding performance of LCP resins and simultaneously reduce the coefficient of thermal expansion (CTE) of LCP resins. Adhesion promoters are added into the LCP resin systems in order to improve the bonding strength with metallic substrates (copper / alloy 42 lead frame etc.) that provide the electrical input/output (I/O) path to electronic packages. Compatibilizers are used to modify the above-mentioned LCP systems with potential multicomponent phase separation and hence (to the fullest) make use of the benefits from each component in the composites. Inorganic microparticles are optional to either solve the processability or promote the functionality of the hermetic LCP systems. The synthetic methods are based on the mechanical blending through injection molding process at an elevated temperature. Anti-oxidants are required to prevent the thermo-oxidative degradation in synthesis of modified LCP nano-composites and subsequent applications, for example, pre-molded cavity quad flat no-lead (QFN) packages. The as-formed LCP resin systems possess high hermetic performance which is comparable to electrical glass with excellent dimensional stability in a wide range of application, especially for advanced electronic packages such as the open cavity QFN substrates for MEMS packages. The hermeticity of 8.0∗ 10\"11 atm-cc/s can be achieved. The adhesion of modified LCP to Ni/Pd/Au-coated copper lead frame can also meet the requirement for MEMS packaging.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131852272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507101
F. Starzer, A. Fischer, H. Knapp, R. Lachner, M. Wojnowski, L. Maurer, A. Stelzer
A chip-package co-design for a voltage controlled oscillator (VCO) designed in a 200-GHz SiGe:C technology is presented. The VCO is frequency-adjustable using a package defined inductor. An overall bandwidth of 21% supports the frequency bands for three different radar applications with a single silicon device. The VCO is accompanied by a buffer, a down-converter mixer (D-Cm) as well as a prescaler. The VCO is assembled in an embedded wafer level ball grid array (eWLB) package with its inductor in the packages fan-in area. It obtains a center frequency as high as 18GHz and achieves phase noise (PN) values of −92 dBc/Hz at 100 kHz offset frequency and an overall bandwidth of 21.7%.
{"title":"A low phase noise VCO in eWLB package","authors":"F. Starzer, A. Fischer, H. Knapp, R. Lachner, M. Wojnowski, L. Maurer, A. Stelzer","doi":"10.1109/EPTC.2012.6507101","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507101","url":null,"abstract":"A chip-package co-design for a voltage controlled oscillator (VCO) designed in a 200-GHz SiGe:C technology is presented. The VCO is frequency-adjustable using a package defined inductor. An overall bandwidth of 21% supports the frequency bands for three different radar applications with a single silicon device. The VCO is accompanied by a buffer, a down-converter mixer (D-Cm) as well as a prescaler. The VCO is assembled in an embedded wafer level ball grid array (eWLB) package with its inductor in the packages fan-in area. It obtains a center frequency as high as 18GHz and achieves phase noise (PN) values of −92 dBc/Hz at 100 kHz offset frequency and an overall bandwidth of 21.7%.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129587904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507163
Y. B. Yang, N. Kumar, D. John, R. Hyman, F. Clive, S. Nathapong, William G. Ramroth
In recent years, many OSAT (Outsourced Semiconductor Assembly and Test) companies start to explore copper wire bond process, which is believed to be able to reduce the IC packaging cost. Copper wire also shows better electrical performance especially for fine wire. However, the reliability maintenance is not as easy as gold wire. Some companies encountered numerous problems in mass production although the copper wire is qualified in engineering stage. This paper is an attempt to understand the bond pad design impact on pad stress as well as the low K layer stress. In this paper, an axisymmetric transient nonlinear dynamic finite element analysis is developed to assist the understanding of copper wire bond process. In the modeling, only Aluminum pad and low-K layers of the bond pad structure are focused. 4 bond pad structures are selected for the stress comparison from Aluminum pad surface to chip low-K layer. Firstly, the stress on Al pad and low K layer is studied with our standard capillary design and bond pad at different stage. Then the capillary inner chamfer angle is varied from 50° to 120 ° to see the impact. Lastly, 4 bond pad structures are presented for comparison.
{"title":"A dynamic study of pad structure impact on bond pad/low-K layer stress in copper wire bond","authors":"Y. B. Yang, N. Kumar, D. John, R. Hyman, F. Clive, S. Nathapong, William G. Ramroth","doi":"10.1109/EPTC.2012.6507163","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507163","url":null,"abstract":"In recent years, many OSAT (Outsourced Semiconductor Assembly and Test) companies start to explore copper wire bond process, which is believed to be able to reduce the IC packaging cost. Copper wire also shows better electrical performance especially for fine wire. However, the reliability maintenance is not as easy as gold wire. Some companies encountered numerous problems in mass production although the copper wire is qualified in engineering stage. This paper is an attempt to understand the bond pad design impact on pad stress as well as the low K layer stress. In this paper, an axisymmetric transient nonlinear dynamic finite element analysis is developed to assist the understanding of copper wire bond process. In the modeling, only Aluminum pad and low-K layers of the bond pad structure are focused. 4 bond pad structures are selected for the stress comparison from Aluminum pad surface to chip low-K layer. Firstly, the stress on Al pad and low K layer is studied with our standard capillary design and bond pad at different stage. Then the capillary inner chamfer angle is varied from 50° to 120 ° to see the impact. Lastly, 4 bond pad structures are presented for comparison.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132088845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507054
Gerhard Domanti, R. Houbertz, J. Bahr, Christine Spitzlei
Material innovation is one of the key enablers in order to produce improved, high performance microelectronic devices with enhanced reliability. Polyimides, cyclobutenes and epoxy-based materials are widely spread to be applied as polymer films for electronic packing, interlayer dielectrics, underfillers and passivation materials. However, requirements on materials continuously increase due to miniaturization of electronic devices, their use in harsh conditions and their employment of novel manufacturing and assembly techniques. In order to meet the more demanding specifications, inorganic-organic hybrid polymers offer a tremendous opportunity since they can be tuned to both, their intrinsic material properties and their capability to be processed by numerous process and patterning techniques.
{"title":"Improvements of inorganic-organic hybrid polymers as dielectric and passivation material","authors":"Gerhard Domanti, R. Houbertz, J. Bahr, Christine Spitzlei","doi":"10.1109/EPTC.2012.6507054","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507054","url":null,"abstract":"Material innovation is one of the key enablers in order to produce improved, high performance microelectronic devices with enhanced reliability. Polyimides, cyclobutenes and epoxy-based materials are widely spread to be applied as polymer films for electronic packing, interlayer dielectrics, underfillers and passivation materials. However, requirements on materials continuously increase due to miniaturization of electronic devices, their use in harsh conditions and their employment of novel manufacturing and assembly techniques. In order to meet the more demanding specifications, inorganic-organic hybrid polymers offer a tremendous opportunity since they can be tuned to both, their intrinsic material properties and their capability to be processed by numerous process and patterning techniques.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133655046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507044
M. Ding, L. Wai, Shiyun Zhang, V. S. Rao
Due to the perpetual push in microelectronic industry for miniaturization and better performance, the density of input/output counts on the electronic packages is multiplying within a given area. Conventional flux-based solder ball attachment process is fast reaching its bottleneck in satisfying the more restrictive pitch tolerances, and assembling challenges in optoelectronics and micro-electromechanical systems (MEMS) packages. To meet the new packaging requirements, a new flux-less laser solder ball jetting technology has been developed. Despite the various advantages which laser solder ball jetting can offer, it has not been extensively reported. In this paper, fine pitch laser solder ball jetting at 200μm pitch was demonstrated using 120μm SAC305 solder spheres. The reliability of the laser jetted bumps was evaluated and compared against the flux-based reflowed bumps, by subjecting the bumps under high temperature storage (1250C for 24hrs, 500hrs and 1000 hrs) and multiple reflow (5 and 10 times). The quality and reliability of the solder joints were quantified through the solder ball shear test, cross-sectioning, energy dispersive x-ray (EDX) spectroscopy analysis and scanning electron microscopy (SEM) imaging. From our results, laser jetted bumps showed high initial average shear strength of 10.70g/mil2, which eventually decreased to 6.96g/mil2 after 24 hours. Comparing the laser jetted bumps against the flux-based reflowed bumps after 1000 hours of thermal aging and 10 times of reflow, the average shear strength values were persistently higher and the measurements of the IMC thickness were constantly lower. Hence, laser solder ball jetting has proven to be an attractive and alternative solder ball attachment method for strong and reliable solder interconnections.
{"title":"Evaluation of laser solder ball jetting for solder ball attachment process","authors":"M. Ding, L. Wai, Shiyun Zhang, V. S. Rao","doi":"10.1109/EPTC.2012.6507044","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507044","url":null,"abstract":"Due to the perpetual push in microelectronic industry for miniaturization and better performance, the density of input/output counts on the electronic packages is multiplying within a given area. Conventional flux-based solder ball attachment process is fast reaching its bottleneck in satisfying the more restrictive pitch tolerances, and assembling challenges in optoelectronics and micro-electromechanical systems (MEMS) packages. To meet the new packaging requirements, a new flux-less laser solder ball jetting technology has been developed. Despite the various advantages which laser solder ball jetting can offer, it has not been extensively reported. In this paper, fine pitch laser solder ball jetting at 200μm pitch was demonstrated using 120μm SAC305 solder spheres. The reliability of the laser jetted bumps was evaluated and compared against the flux-based reflowed bumps, by subjecting the bumps under high temperature storage (1250C for 24hrs, 500hrs and 1000 hrs) and multiple reflow (5 and 10 times). The quality and reliability of the solder joints were quantified through the solder ball shear test, cross-sectioning, energy dispersive x-ray (EDX) spectroscopy analysis and scanning electron microscopy (SEM) imaging. From our results, laser jetted bumps showed high initial average shear strength of 10.70g/mil2, which eventually decreased to 6.96g/mil2 after 24 hours. Comparing the laser jetted bumps against the flux-based reflowed bumps after 1000 hours of thermal aging and 10 times of reflow, the average shear strength values were persistently higher and the measurements of the IMC thickness were constantly lower. Hence, laser solder ball jetting has proven to be an attractive and alternative solder ball attachment method for strong and reliable solder interconnections.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115021341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507043
Awet Yemane Weldezion, Roshan Weerasekara, H. Tenhunen
In this paper, we explore the cost of clock pumping techniques implemented for scalable 3-D Integrated Systems in the complexity of interconnect, circuit, and architecture level changes. Their effect in terms of area and power for comparable performance is estimated. Our results show that by using 50% of the number of TSVs, we achieve the same performance as standard implementation with insignificant area and power overhead from the overall system cost. The proposed pumping technique can be used as one of the components in 3-D systems design for several applications that require logic-on-logic or memory-on-logic stacking.
{"title":"Design space exploration of clock-pumping techniques to reduce through-silicon-via (TSV) manufacturing cost in 3-d integration","authors":"Awet Yemane Weldezion, Roshan Weerasekara, H. Tenhunen","doi":"10.1109/EPTC.2012.6507043","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507043","url":null,"abstract":"In this paper, we explore the cost of clock pumping techniques implemented for scalable 3-D Integrated Systems in the complexity of interconnect, circuit, and architecture level changes. Their effect in terms of area and power for comparable performance is estimated. Our results show that by using 50% of the number of TSVs, we achieve the same performance as standard implementation with insignificant area and power overhead from the overall system cost. The proposed pumping technique can be used as one of the components in 3-D systems design for several applications that require logic-on-logic or memory-on-logic stacking.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115194280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507174
Oliver Albrecht, A. Klemm, M. Oppermann, K. Wolter
For electronic products there are distinct and very high reliability requirements, in particular for applications within aeronautics, medicine and automotive sectors. In order to prove the reliability of integrated circuits packages and their solder joints accelerated aging tests are mandatory (e.g. thermal shock cycles, isothermal storage and vibration stress). Additionally electrical characterization methods are needed and are employing so called daisy chain circuits for the electrical failure detection on solder joints during the experiments while using serial circuits with a permanent monitoring of the impressed current for the to be examined electrical connections of the package. Thus, the described methods for the electrical investigation of the reliability are commonly using dummy packages which include additional internal circuits assembled under laboratory conditions. These methods do not allow the investigation of real integrated circuits. This paper will discuss a new method for electrical characterization of real and soldered high pin count integrated circuits due to the utilization of the included ESD-protective circuit like it is common on wafer level or using advanced boundary scan techniques [1]. This method allows the test of the whole interconnect chain (e.g. PCB connections, bonding connections, interposer connections, soldered connections).
{"title":"Electrical test method and realized system for high pin count components during reliability tests","authors":"Oliver Albrecht, A. Klemm, M. Oppermann, K. Wolter","doi":"10.1109/EPTC.2012.6507174","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507174","url":null,"abstract":"For electronic products there are distinct and very high reliability requirements, in particular for applications within aeronautics, medicine and automotive sectors. In order to prove the reliability of integrated circuits packages and their solder joints accelerated aging tests are mandatory (e.g. thermal shock cycles, isothermal storage and vibration stress). Additionally electrical characterization methods are needed and are employing so called daisy chain circuits for the electrical failure detection on solder joints during the experiments while using serial circuits with a permanent monitoring of the impressed current for the to be examined electrical connections of the package. Thus, the described methods for the electrical investigation of the reliability are commonly using dummy packages which include additional internal circuits assembled under laboratory conditions. These methods do not allow the investigation of real integrated circuits. This paper will discuss a new method for electrical characterization of real and soldered high pin count integrated circuits due to the utilization of the included ESD-protective circuit like it is common on wafer level or using advanced boundary scan techniques [1]. This method allows the test of the whole interconnect chain (e.g. PCB connections, bonding connections, interposer connections, soldered connections).","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"122 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129470464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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