Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507054
Gerhard Domanti, R. Houbertz, J. Bahr, Christine Spitzlei
Material innovation is one of the key enablers in order to produce improved, high performance microelectronic devices with enhanced reliability. Polyimides, cyclobutenes and epoxy-based materials are widely spread to be applied as polymer films for electronic packing, interlayer dielectrics, underfillers and passivation materials. However, requirements on materials continuously increase due to miniaturization of electronic devices, their use in harsh conditions and their employment of novel manufacturing and assembly techniques. In order to meet the more demanding specifications, inorganic-organic hybrid polymers offer a tremendous opportunity since they can be tuned to both, their intrinsic material properties and their capability to be processed by numerous process and patterning techniques.
{"title":"Improvements of inorganic-organic hybrid polymers as dielectric and passivation material","authors":"Gerhard Domanti, R. Houbertz, J. Bahr, Christine Spitzlei","doi":"10.1109/EPTC.2012.6507054","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507054","url":null,"abstract":"Material innovation is one of the key enablers in order to produce improved, high performance microelectronic devices with enhanced reliability. Polyimides, cyclobutenes and epoxy-based materials are widely spread to be applied as polymer films for electronic packing, interlayer dielectrics, underfillers and passivation materials. However, requirements on materials continuously increase due to miniaturization of electronic devices, their use in harsh conditions and their employment of novel manufacturing and assembly techniques. In order to meet the more demanding specifications, inorganic-organic hybrid polymers offer a tremendous opportunity since they can be tuned to both, their intrinsic material properties and their capability to be processed by numerous process and patterning techniques.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133655046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507144
Y. Lim, Yee Mey Goh, Changqing Liu
Interest in body area networks (BAN) operating in the millimeter-wave regime (60 GHz) is increasing due to concerns over the security of data transfer. Obtaining low loss in the higher frequencies is important for high performance interconnects. In this paper, two materials deposition techniques — inkjet printing and stencil printing are being investigated for creating conductive traces on fabrics to enable high frequency (up to 20 GHz) applications. In the inkjet printing, various surface treatments were considered and utilized to improve the ink-substrate interaction for the enhancement of adhesion of the deposited structures. Finally the RF losses of printed microstrip lines using the above techniques were analyzed, compared against the copper traces which are conventionally achieved by etching process.
{"title":"RF performance of inkjet and stencil printed traces for flexible electronics applications","authors":"Y. Lim, Yee Mey Goh, Changqing Liu","doi":"10.1109/EPTC.2012.6507144","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507144","url":null,"abstract":"Interest in body area networks (BAN) operating in the millimeter-wave regime (60 GHz) is increasing due to concerns over the security of data transfer. Obtaining low loss in the higher frequencies is important for high performance interconnects. In this paper, two materials deposition techniques — inkjet printing and stencil printing are being investigated for creating conductive traces on fabrics to enable high frequency (up to 20 GHz) applications. In the inkjet printing, various surface treatments were considered and utilized to improve the ink-substrate interaction for the enhancement of adhesion of the deposited structures. Finally the RF losses of printed microstrip lines using the above techniques were analyzed, compared against the copper traces which are conventionally achieved by etching process.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"249 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130458176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507115
R. Weerasekera, J. R. Cubillo, G. Katti
This paper describes the electrical characteristics of the fine pitch interconnects in silicon carrier systems. The characteristics of such interconnects are explored and a typical FPGA-memory system is compared viz-a-viz with a traditional PCB system from low data rates to higher data rates. Our case-study shows that even though highly resistive wires are used in silicon carrier the interconnects are SI robust due to the shorter die to die interconnect length and the absence of package parasitics.
{"title":"Analysis of signal integrity(SI) robustness in through-silicon interposer (TSI) interconnects","authors":"R. Weerasekera, J. R. Cubillo, G. Katti","doi":"10.1109/EPTC.2012.6507115","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507115","url":null,"abstract":"This paper describes the electrical characteristics of the fine pitch interconnects in silicon carrier systems. The characteristics of such interconnects are explored and a typical FPGA-memory system is compared viz-a-viz with a traditional PCB system from low data rates to higher data rates. Our case-study shows that even though highly resistive wires are used in silicon carrier the interconnects are SI robust due to the shorter die to die interconnect length and the absence of package parasitics.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127908703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507119
Mark Huang, C. Chu, F. Lim
In this paper, a new method is utilized to develop the hermetic thermoplastics through modification of conventional LCP resins. Thermoplastic materials are synthesized for producing a hermetic barrier with a cavity structure made based on the materials compositions: near-hermetic liquid crystalline polymers (LCP), nano-sized mineral fillers, adhesion promoters, compatibilizers, inorganic microparticles and anti-oxidants. Near-hermetic LCP is used as the matrix resin to provide robust mechanical strength, heat resistant stability and electrical insulation. Nano-sized mineral fillers with large aspect ratio are incorporated into LCP matrix resin to increase its hermeticity without sacrificing the outstanding performance of LCP resins and simultaneously reduce the coefficient of thermal expansion (CTE) of LCP resins. Adhesion promoters are added into the LCP resin systems in order to improve the bonding strength with metallic substrates (copper / alloy 42 lead frame etc.) that provide the electrical input/output (I/O) path to electronic packages. Compatibilizers are used to modify the above-mentioned LCP systems with potential multicomponent phase separation and hence (to the fullest) make use of the benefits from each component in the composites. Inorganic microparticles are optional to either solve the processability or promote the functionality of the hermetic LCP systems. The synthetic methods are based on the mechanical blending through injection molding process at an elevated temperature. Anti-oxidants are required to prevent the thermo-oxidative degradation in synthesis of modified LCP nano-composites and subsequent applications, for example, pre-molded cavity quad flat no-lead (QFN) packages. The as-formed LCP resin systems possess high hermetic performance which is comparable to electrical glass with excellent dimensional stability in a wide range of application, especially for advanced electronic packages such as the open cavity QFN substrates for MEMS packages. The hermeticity of 8.0∗ 10"11 atm-cc/s can be achieved. The adhesion of modified LCP to Ni/Pd/Au-coated copper lead frame can also meet the requirement for MEMS packaging.
{"title":"Development of hermetic LCP for electronic device packages","authors":"Mark Huang, C. Chu, F. Lim","doi":"10.1109/EPTC.2012.6507119","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507119","url":null,"abstract":"In this paper, a new method is utilized to develop the hermetic thermoplastics through modification of conventional LCP resins. Thermoplastic materials are synthesized for producing a hermetic barrier with a cavity structure made based on the materials compositions: near-hermetic liquid crystalline polymers (LCP), nano-sized mineral fillers, adhesion promoters, compatibilizers, inorganic microparticles and anti-oxidants. Near-hermetic LCP is used as the matrix resin to provide robust mechanical strength, heat resistant stability and electrical insulation. Nano-sized mineral fillers with large aspect ratio are incorporated into LCP matrix resin to increase its hermeticity without sacrificing the outstanding performance of LCP resins and simultaneously reduce the coefficient of thermal expansion (CTE) of LCP resins. Adhesion promoters are added into the LCP resin systems in order to improve the bonding strength with metallic substrates (copper / alloy 42 lead frame etc.) that provide the electrical input/output (I/O) path to electronic packages. Compatibilizers are used to modify the above-mentioned LCP systems with potential multicomponent phase separation and hence (to the fullest) make use of the benefits from each component in the composites. Inorganic microparticles are optional to either solve the processability or promote the functionality of the hermetic LCP systems. The synthetic methods are based on the mechanical blending through injection molding process at an elevated temperature. Anti-oxidants are required to prevent the thermo-oxidative degradation in synthesis of modified LCP nano-composites and subsequent applications, for example, pre-molded cavity quad flat no-lead (QFN) packages. The as-formed LCP resin systems possess high hermetic performance which is comparable to electrical glass with excellent dimensional stability in a wide range of application, especially for advanced electronic packages such as the open cavity QFN substrates for MEMS packages. The hermeticity of 8.0∗ 10\"11 atm-cc/s can be achieved. The adhesion of modified LCP to Ni/Pd/Au-coated copper lead frame can also meet the requirement for MEMS packaging.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131852272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507163
Y. B. Yang, N. Kumar, D. John, R. Hyman, F. Clive, S. Nathapong, William G. Ramroth
In recent years, many OSAT (Outsourced Semiconductor Assembly and Test) companies start to explore copper wire bond process, which is believed to be able to reduce the IC packaging cost. Copper wire also shows better electrical performance especially for fine wire. However, the reliability maintenance is not as easy as gold wire. Some companies encountered numerous problems in mass production although the copper wire is qualified in engineering stage. This paper is an attempt to understand the bond pad design impact on pad stress as well as the low K layer stress. In this paper, an axisymmetric transient nonlinear dynamic finite element analysis is developed to assist the understanding of copper wire bond process. In the modeling, only Aluminum pad and low-K layers of the bond pad structure are focused. 4 bond pad structures are selected for the stress comparison from Aluminum pad surface to chip low-K layer. Firstly, the stress on Al pad and low K layer is studied with our standard capillary design and bond pad at different stage. Then the capillary inner chamfer angle is varied from 50° to 120 ° to see the impact. Lastly, 4 bond pad structures are presented for comparison.
{"title":"A dynamic study of pad structure impact on bond pad/low-K layer stress in copper wire bond","authors":"Y. B. Yang, N. Kumar, D. John, R. Hyman, F. Clive, S. Nathapong, William G. Ramroth","doi":"10.1109/EPTC.2012.6507163","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507163","url":null,"abstract":"In recent years, many OSAT (Outsourced Semiconductor Assembly and Test) companies start to explore copper wire bond process, which is believed to be able to reduce the IC packaging cost. Copper wire also shows better electrical performance especially for fine wire. However, the reliability maintenance is not as easy as gold wire. Some companies encountered numerous problems in mass production although the copper wire is qualified in engineering stage. This paper is an attempt to understand the bond pad design impact on pad stress as well as the low K layer stress. In this paper, an axisymmetric transient nonlinear dynamic finite element analysis is developed to assist the understanding of copper wire bond process. In the modeling, only Aluminum pad and low-K layers of the bond pad structure are focused. 4 bond pad structures are selected for the stress comparison from Aluminum pad surface to chip low-K layer. Firstly, the stress on Al pad and low K layer is studied with our standard capillary design and bond pad at different stage. Then the capillary inner chamfer angle is varied from 50° to 120 ° to see the impact. Lastly, 4 bond pad structures are presented for comparison.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132088845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507143
J. N. Tey, E. Kok, Haijing Lu, Jun Wei
Three carbon nanotubes post treatment methods were evaluated for their impacts on film conductivity. Acid treatment was found to be the most impactful treatment for conductivity improvement, with >3 times reduction in sheet resistance for long hour soaking in 9M sulfuric acid. Carbon nanotube sorting with agarose gel method for metallic single walled carbon nanotube enrichment also showed great improvement with ∼2.5 to 3 times reduction in sheet resistance by simply enhancing the % M-SWNT from 33% to 60%.
{"title":"Carbon nanotubes post processing methods for improved film conductivity","authors":"J. N. Tey, E. Kok, Haijing Lu, Jun Wei","doi":"10.1109/EPTC.2012.6507143","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507143","url":null,"abstract":"Three carbon nanotubes post treatment methods were evaluated for their impacts on film conductivity. Acid treatment was found to be the most impactful treatment for conductivity improvement, with >3 times reduction in sheet resistance for long hour soaking in 9M sulfuric acid. Carbon nanotube sorting with agarose gel method for metallic single walled carbon nanotube enrichment also showed great improvement with ∼2.5 to 3 times reduction in sheet resistance by simply enhancing the % M-SWNT from 33% to 60%.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"51 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134491038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507101
F. Starzer, A. Fischer, H. Knapp, R. Lachner, M. Wojnowski, L. Maurer, A. Stelzer
A chip-package co-design for a voltage controlled oscillator (VCO) designed in a 200-GHz SiGe:C technology is presented. The VCO is frequency-adjustable using a package defined inductor. An overall bandwidth of 21% supports the frequency bands for three different radar applications with a single silicon device. The VCO is accompanied by a buffer, a down-converter mixer (D-Cm) as well as a prescaler. The VCO is assembled in an embedded wafer level ball grid array (eWLB) package with its inductor in the packages fan-in area. It obtains a center frequency as high as 18GHz and achieves phase noise (PN) values of −92 dBc/Hz at 100 kHz offset frequency and an overall bandwidth of 21.7%.
{"title":"A low phase noise VCO in eWLB package","authors":"F. Starzer, A. Fischer, H. Knapp, R. Lachner, M. Wojnowski, L. Maurer, A. Stelzer","doi":"10.1109/EPTC.2012.6507101","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507101","url":null,"abstract":"A chip-package co-design for a voltage controlled oscillator (VCO) designed in a 200-GHz SiGe:C technology is presented. The VCO is frequency-adjustable using a package defined inductor. An overall bandwidth of 21% supports the frequency bands for three different radar applications with a single silicon device. The VCO is accompanied by a buffer, a down-converter mixer (D-Cm) as well as a prescaler. The VCO is assembled in an embedded wafer level ball grid array (eWLB) package with its inductor in the packages fan-in area. It obtains a center frequency as high as 18GHz and achieves phase noise (PN) values of −92 dBc/Hz at 100 kHz offset frequency and an overall bandwidth of 21.7%.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129587904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507174
Oliver Albrecht, A. Klemm, M. Oppermann, K. Wolter
For electronic products there are distinct and very high reliability requirements, in particular for applications within aeronautics, medicine and automotive sectors. In order to prove the reliability of integrated circuits packages and their solder joints accelerated aging tests are mandatory (e.g. thermal shock cycles, isothermal storage and vibration stress). Additionally electrical characterization methods are needed and are employing so called daisy chain circuits for the electrical failure detection on solder joints during the experiments while using serial circuits with a permanent monitoring of the impressed current for the to be examined electrical connections of the package. Thus, the described methods for the electrical investigation of the reliability are commonly using dummy packages which include additional internal circuits assembled under laboratory conditions. These methods do not allow the investigation of real integrated circuits. This paper will discuss a new method for electrical characterization of real and soldered high pin count integrated circuits due to the utilization of the included ESD-protective circuit like it is common on wafer level or using advanced boundary scan techniques [1]. This method allows the test of the whole interconnect chain (e.g. PCB connections, bonding connections, interposer connections, soldered connections).
{"title":"Electrical test method and realized system for high pin count components during reliability tests","authors":"Oliver Albrecht, A. Klemm, M. Oppermann, K. Wolter","doi":"10.1109/EPTC.2012.6507174","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507174","url":null,"abstract":"For electronic products there are distinct and very high reliability requirements, in particular for applications within aeronautics, medicine and automotive sectors. In order to prove the reliability of integrated circuits packages and their solder joints accelerated aging tests are mandatory (e.g. thermal shock cycles, isothermal storage and vibration stress). Additionally electrical characterization methods are needed and are employing so called daisy chain circuits for the electrical failure detection on solder joints during the experiments while using serial circuits with a permanent monitoring of the impressed current for the to be examined electrical connections of the package. Thus, the described methods for the electrical investigation of the reliability are commonly using dummy packages which include additional internal circuits assembled under laboratory conditions. These methods do not allow the investigation of real integrated circuits. This paper will discuss a new method for electrical characterization of real and soldered high pin count integrated circuits due to the utilization of the included ESD-protective circuit like it is common on wafer level or using advanced boundary scan techniques [1]. This method allows the test of the whole interconnect chain (e.g. PCB connections, bonding connections, interposer connections, soldered connections).","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"122 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129470464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507158
S. Kannan, Bruce C. Kim, Anurag Gupta, Seok-Ho Noh
This paper presents the development of integrated model of CNT-based TSVs for RF applications by taking into consideration contact pad resistance, substrate effects and kinetic inductance contribution of different parasitics, in addition to quantum mechanical transport effects in these 1D mesoscopic systems. Previously, we developed models for CNT-based TSV for low frequencies that SW-CNT bundles by considering ideal contact pads because CNTs offer tremendous performance based benefits such as excellent current carrying capability (> 1010 A/cm2, three orders of magnitude higher than Cu), negligible electro-migration and good thermal stability. However, in order to realize a 3D IC with CNT based TSVs it is essential to form an interconnection network between the TSVs and 2D interconnects on the die. We have used both Molybdenum (Mo) and gold (Au) contact pads to connect CNT-TSVs with copper trace lines on the die. Modeling was performed on two dies interconnected with CNT-TSVs of height 20 μm, diameter of 5 μm and a pitch of 80 μm. BCB (benzocyclobutane) is used as the insulation layer which provides excellent isolation at high frequencies and also fills the gaps in CNT bundles making the structure thermo-mechanically robust. SW-CNTs of diameter 1nm were used in bundles of 15000 CNTs/bundle. S-parameter simulation of CNT-based TSVs with Mo and Au contact pads was performed and the return loss and transmission was measured at frequencies up to 13 GHz.
{"title":"Modeling, analysis and simulation of CNT based TSVs for RF applications","authors":"S. Kannan, Bruce C. Kim, Anurag Gupta, Seok-Ho Noh","doi":"10.1109/EPTC.2012.6507158","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507158","url":null,"abstract":"This paper presents the development of integrated model of CNT-based TSVs for RF applications by taking into consideration contact pad resistance, substrate effects and kinetic inductance contribution of different parasitics, in addition to quantum mechanical transport effects in these 1D mesoscopic systems. Previously, we developed models for CNT-based TSV for low frequencies that SW-CNT bundles by considering ideal contact pads because CNTs offer tremendous performance based benefits such as excellent current carrying capability (> 1010 A/cm2, three orders of magnitude higher than Cu), negligible electro-migration and good thermal stability. However, in order to realize a 3D IC with CNT based TSVs it is essential to form an interconnection network between the TSVs and 2D interconnects on the die. We have used both Molybdenum (Mo) and gold (Au) contact pads to connect CNT-TSVs with copper trace lines on the die. Modeling was performed on two dies interconnected with CNT-TSVs of height 20 μm, diameter of 5 μm and a pitch of 80 μm. BCB (benzocyclobutane) is used as the insulation layer which provides excellent isolation at high frequencies and also fills the gaps in CNT bundles making the structure thermo-mechanically robust. SW-CNTs of diameter 1nm were used in bundles of 15000 CNTs/bundle. S-parameter simulation of CNT-based TSVs with Mo and Au contact pads was performed and the return loss and transmission was measured at frequencies up to 13 GHz.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129120694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507166
E. R. Crandall, G. Flowers, P. Lall, M. Bozack
Studies of tin (Sn) whisker growth from Sn solder alloys shows that SAC deposits can be whisker prone. In fact, even SnPb solders may produce whisker growth. The Sn alloy specimens consisted of 2400 A SAC305 (∼3.0%Ag, 0.5%Cu and rest Sn), along with 750 and 1200 Å Sn-37Pb films, each sputtered under compressive stress conditions on electrochemically polished brass and incubated in ambient room temperature/humidity (RT/RH). After a month of incubation whisker growth is already observed on the SAC and 750 Å SnPb films. The thicker, 1200 Å, SnPb film did not whisker till after over a year of incubation with only 524 whiskers/cm2. At this time (∼400 days) the 750 Å Sn-37Pb film has modest whisker numbers, while SAC has produced > 147,000 whiskers/cm2 after 590 days of incubation at RT/RH, making it apparent that whisker growth can occur on high Sn content alloy deposits. Comparing the 750 Å SnPb specimen to 750 A of pure Sn on brass after similar incubation periods, the Sn film produced ∼ 1.75X the whisker density of the Sn-37Pb film, with > 5 X the average whisker length, highlighting the ability of incorporated Pb to suppress whiskers. This is in agreement with electroplated films studies, where the addition of Pb in Sn is observed to reduce film stress, mitigating whisker growth [e.g., E. Chason et. al., App. Phys. Letters, 92 (2008) 171901].
对锡焊料合金中锡(Sn)晶须生长的研究表明，SAC沉积容易产生晶须。事实上，即使是SnPb焊料也可能产生晶须生长。锡合金试样由2400个A SAC305 (~ 3.0%Ag, 0.5%Cu和剩余Sn)，以及750和1200个Å Sn- 37pb薄膜组成，每个薄膜在压应力条件下溅射在电化学抛光的黄铜上，并在室温/湿度(RT/RH)中孵育。经过一个月的孵育，在SAC和750 Å SnPb薄膜上已经观察到晶须生长。较厚的(1200 Å) SnPb薄膜在经过一年多的孵育后才长出须，只有524须/cm2。此时(~ 400天)，750 Å Sn- 37pb薄膜的晶须数量不大，而SAC在RT/RH下孵育590天后，晶须数量超过147,000 /cm2，这表明在高锡含量的合金沉积上可以出现晶须生长。将750 Å SnPb样品与750 A的纯锡在黄铜上经过相似的孵育时间后进行比较，Sn薄膜的晶须密度是Sn- 37pb薄膜的1.75倍，平均晶须长度大于5倍，突出了掺入Pb抑制晶须的能力。这与电镀薄膜的研究一致，在锡中添加Pb可以减少薄膜应力，减缓晶须生长[例如，E. Chason等人，App. Phys。文学，92(2008)171901]。
{"title":"Whisker growth from Sn solder alloys","authors":"E. R. Crandall, G. Flowers, P. Lall, M. Bozack","doi":"10.1109/EPTC.2012.6507166","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507166","url":null,"abstract":"Studies of tin (Sn) whisker growth from Sn solder alloys shows that SAC deposits can be whisker prone. In fact, even SnPb solders may produce whisker growth. The Sn alloy specimens consisted of 2400 A SAC305 (∼3.0%Ag, 0.5%Cu and rest Sn), along with 750 and 1200 Å Sn-37Pb films, each sputtered under compressive stress conditions on electrochemically polished brass and incubated in ambient room temperature/humidity (RT/RH). After a month of incubation whisker growth is already observed on the SAC and 750 Å SnPb films. The thicker, 1200 Å, SnPb film did not whisker till after over a year of incubation with only 524 whiskers/cm2. At this time (∼400 days) the 750 Å Sn-37Pb film has modest whisker numbers, while SAC has produced > 147,000 whiskers/cm2 after 590 days of incubation at RT/RH, making it apparent that whisker growth can occur on high Sn content alloy deposits. Comparing the 750 Å SnPb specimen to 750 A of pure Sn on brass after similar incubation periods, the Sn film produced ∼ 1.75X the whisker density of the Sn-37Pb film, with > 5 X the average whisker length, highlighting the ability of incorporated Pb to suppress whiskers. This is in agreement with electroplated films studies, where the addition of Pb in Sn is observed to reduce film stress, mitigating whisker growth [e.g., E. Chason et. al., App. Phys. Letters, 92 (2008) 171901].","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128276683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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