Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507147
Nouhad Bachnak
After being established as a leading technology for the manufacturing of 3D antennas for mobile phones the 3D-MD technology (three dimensional molded interconnect devices) is gaining a strong foothold in other applications like MEMS packaging, sensors, LEDs, switches and connectors and it seems to become a game changing technology thanks to its capabilities: Miniaturization, rationalization and functional integration. 3D-MID allows miniaturization by the integration of mechanical and electronic functions in one part and so much more compact construction and much greater function density can be achieved.
{"title":"3D-MID technology MEMS connectivity at system level","authors":"Nouhad Bachnak","doi":"10.1109/EPTC.2012.6507147","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507147","url":null,"abstract":"After being established as a leading technology for the manufacturing of 3D antennas for mobile phones the 3D-MD technology (three dimensional molded interconnect devices) is gaining a strong foothold in other applications like MEMS packaging, sensors, LEDs, switches and connectors and it seems to become a game changing technology thanks to its capabilities: Miniaturization, rationalization and functional integration. 3D-MID allows miniaturization by the integration of mechanical and electronic functions in one part and so much more compact construction and much greater function density can be achieved.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122558081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507070
B. Barabadi, Y. Joshi, Satish Kumar
This paper studies the rapid transient thermal analysis of a packaged high power microprocessor, forced convection cooled using a heat sink. A spatially resolved power map for Intel Core 2 Duo Penryn processor was considered. Two different transient power profiles were investigated: an impulsively applied power map, and an oscillatory variation power map. We extended and demonstrated the capability of a recently developed hybrid approach in modeling several decades of length scale from package to chip at a considerably lower computational cost, while maintaining satisfactory accuracy. The proper orthogonal decomposition (POD) technique was used for the rapid prediction of the transient thermal response for impulsive vs. oscillatory power applied to the chip. The results were compared with a detailed finite element (FE) model developed in COMSOL®. The close agreement between the two models confirms the capability of the multi-scale model in rapidly predicting accurate temperature profiles, without performing detailed FE simulations, which can significantly decrease the computational cost in parametric modeling.
本文研究了采用散热器强制对流冷却的封装型大功率微处理器的快速瞬态热分析。考虑了Intel酷睿2 Duo Penryn处理器的空间分辨功率图。研究了两种不同的暂态功率分布图:脉冲功率分布图和振荡变化功率分布图。我们扩展并展示了最近开发的混合方法的能力，以相当低的计算成本对从封装到芯片的数十年长度进行建模，同时保持令人满意的精度。采用适当的正交分解(POD)技术快速预测了脉冲和振荡功率对芯片瞬态热响应的影响。结果与COMSOL®开发的详细有限元(FE)模型进行了比较。两种模型之间的密切一致性证实了多尺度模型能够快速准确地预测温度分布，而无需进行详细的有限元模拟，这可以显着降低参数化建模的计算成本。
{"title":"Rapid multi-scale transient thermal modeling of packaged microprocessors using hybrid approach","authors":"B. Barabadi, Y. Joshi, Satish Kumar","doi":"10.1109/EPTC.2012.6507070","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507070","url":null,"abstract":"This paper studies the rapid transient thermal analysis of a packaged high power microprocessor, forced convection cooled using a heat sink. A spatially resolved power map for Intel Core 2 Duo Penryn processor was considered. Two different transient power profiles were investigated: an impulsively applied power map, and an oscillatory variation power map. We extended and demonstrated the capability of a recently developed hybrid approach in modeling several decades of length scale from package to chip at a considerably lower computational cost, while maintaining satisfactory accuracy. The proper orthogonal decomposition (POD) technique was used for the rapid prediction of the transient thermal response for impulsive vs. oscillatory power applied to the chip. The results were compared with a detailed finite element (FE) model developed in COMSOL®. The close agreement between the two models confirms the capability of the multi-scale model in rapidly predicting accurate temperature profiles, without performing detailed FE simulations, which can significantly decrease the computational cost in parametric modeling.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122759603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507171
L. Lim, J. Cheong, Jie Li Aw Jerry, Cairan He
This paper reports an implantable blood flow sensor system integrated on flexible circuit that consists of pressure sensor and inductively powered wireless sensor interface Application Specific Integrated Circuit (ASIC) for early graft failure detection application. The proposed system was embedded within the vascular graft to have continuously monitoring the differential blood pressure change as an indication of stenosis build- up in the graft. The fabricated pressure sensor is showed the step of 0.5psi of pressure changes is clearly visible with the resistance change. The resolution of pressure change 8mmHg was achieved. [1] The whole system was successfully integrated on designed flexible circuit by optimizing method of flip-chip bonding with gold stud bump and underfill encapsulant at lower temperature. The assembled system was successfully demonstrated wirelessly.
{"title":"Implantable blood flow sensor integrated on flexible circuit for vascular graft application","authors":"L. Lim, J. Cheong, Jie Li Aw Jerry, Cairan He","doi":"10.1109/EPTC.2012.6507171","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507171","url":null,"abstract":"This paper reports an implantable blood flow sensor system integrated on flexible circuit that consists of pressure sensor and inductively powered wireless sensor interface Application Specific Integrated Circuit (ASIC) for early graft failure detection application. The proposed system was embedded within the vascular graft to have continuously monitoring the differential blood pressure change as an indication of stenosis build- up in the graft. The fabricated pressure sensor is showed the step of 0.5psi of pressure changes is clearly visible with the resistance change. The resolution of pressure change 8mmHg was achieved. [1] The whole system was successfully integrated on designed flexible circuit by optimizing method of flip-chip bonding with gold stud bump and underfill encapsulant at lower temperature. The assembled system was successfully demonstrated wirelessly.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123187617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507177
Ho-Eun Bae, Kwang-Seong Choi, Hyun-Cheol Bae, Y. Eom, D. Bae
Low-volume, low-cost and lead-free Solder-on-Pad (SoP) process using solder bump maker (SBM) is proposed for the fine-pitch flip-chip bonding process. The SBM is composed of a lead-free solder powder and a resin. The resin in the SBM consists of a polymer matrix, a deoxidizing agent and additives. The deoxidizing agent and additives remove the oxide layer on the surface of the solder powder. The bumping process features no-mask process so that a fine pitch bump array can be easily achievable. It mainly consists of two thermal steps; one is for the aggregation of the solder powder on the metal pads on a substrate and the other for the reflow process to make the round solder bump array. The thermo-rheological behavior of the SBM was characterized using a differential scanning calorimetry (DSC) and a dynamic mechanical analyzer (DMA). With this material and process, the solder bump array was successfully formed with pitch of 130μm.
{"title":"Fine-pitch, low-volume SoP(Solder-on-Pad) process","authors":"Ho-Eun Bae, Kwang-Seong Choi, Hyun-Cheol Bae, Y. Eom, D. Bae","doi":"10.1109/EPTC.2012.6507177","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507177","url":null,"abstract":"Low-volume, low-cost and lead-free Solder-on-Pad (SoP) process using solder bump maker (SBM) is proposed for the fine-pitch flip-chip bonding process. The SBM is composed of a lead-free solder powder and a resin. The resin in the SBM consists of a polymer matrix, a deoxidizing agent and additives. The deoxidizing agent and additives remove the oxide layer on the surface of the solder powder. The bumping process features no-mask process so that a fine pitch bump array can be easily achievable. It mainly consists of two thermal steps; one is for the aggregation of the solder powder on the metal pads on a substrate and the other for the reflow process to make the round solder bump array. The thermo-rheological behavior of the SBM was characterized using a differential scanning calorimetry (DSC) and a dynamic mechanical analyzer (DMA). With this material and process, the solder bump array was successfully formed with pitch of 130μm.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115969587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507129
J. Auersperg, R. Dudek, B. Bramer, R. Pufall, B. Seiler, B. Michel
Simple adhesion tests like the pull-out test or the button shear tests have been used in industry for decades. They offer a great potential for comparison of different molding compounds, encapsulants, or adhesives on different types of substrates with or without surface treatment. However, for theoretical prediction purposes, interface fracture mechanics parameters are needed. Quantitative evaluations of the test applied to molding compound (MC)-button on Cu-leadframe by different fracture- and damage mechanical approaches are the subjects of the paper. Defect tolerant methodologies like the "virtual crack closure technique" (VCCT) and the J-inter-action integral approach, which consider the interface initially delaminated, are compared to the damage methodology “cohesive zone modelling (CZM)”, which needs no initial crack and can track the delamination progress. Calculated fracture parameters, in particular the energy release rates and mode mixity are compared. Effects on these parameters are discussed for different button shapes. In-situ tracking of dela-mination progress for a cubic button is shown using the optical correlation technique microDAC.
{"title":"Capturing interface toughness parameters from shear testing using different fracture mechanics approaches","authors":"J. Auersperg, R. Dudek, B. Bramer, R. Pufall, B. Seiler, B. Michel","doi":"10.1109/EPTC.2012.6507129","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507129","url":null,"abstract":"Simple adhesion tests like the pull-out test or the button shear tests have been used in industry for decades. They offer a great potential for comparison of different molding compounds, encapsulants, or adhesives on different types of substrates with or without surface treatment. However, for theoretical prediction purposes, interface fracture mechanics parameters are needed. Quantitative evaluations of the test applied to molding compound (MC)-button on Cu-leadframe by different fracture- and damage mechanical approaches are the subjects of the paper. Defect tolerant methodologies like the \"virtual crack closure technique\" (VCCT) and the J-inter-action integral approach, which consider the interface initially delaminated, are compared to the damage methodology “cohesive zone modelling (CZM)”, which needs no initial crack and can track the delamination progress. Calculated fracture parameters, in particular the energy release rates and mode mixity are compared. Effects on these parameters are discussed for different button shapes. In-situ tracking of dela-mination progress for a cubic button is shown using the optical correlation technique microDAC.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126847109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507093
M. Chew, M. Ding, E. Wai, S. Chong, V. S. Rao, Min Woo Daniel Rhee
In this paper, characterization of 3 types of underfill for high performance applications has been presented. Characterizations of underfill materials such as adhesion testing, contact angle measurement on different surfaces, filler size distribution were conducted to understand the underfill materials. The adhesion test results revealed that failure is mainly mixed mode, which is the failure between bulk underfill failure and interfacial failure. The thermal conductive underfill has a wider range of filler sizes and has the most hydrophilic behavior. From the glass chip flow test, the flow behavior of the underfill could be observed, with the most thermal conductive underfill having the slowest flow. Process optimization for thermal chip and daisy chain chip for void free underfill was also carried out based on dispensing temperature and patterns.
{"title":"Characterization of thermally conductive underfill materials for high performance flip-chip applications","authors":"M. Chew, M. Ding, E. Wai, S. Chong, V. S. Rao, Min Woo Daniel Rhee","doi":"10.1109/EPTC.2012.6507093","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507093","url":null,"abstract":"In this paper, characterization of 3 types of underfill for high performance applications has been presented. Characterizations of underfill materials such as adhesion testing, contact angle measurement on different surfaces, filler size distribution were conducted to understand the underfill materials. The adhesion test results revealed that failure is mainly mixed mode, which is the failure between bulk underfill failure and interfacial failure. The thermal conductive underfill has a wider range of filler sizes and has the most hydrophilic behavior. From the glass chip flow test, the flow behavior of the underfill could be observed, with the most thermal conductive underfill having the slowest flow. Process optimization for thermal chip and daisy chain chip for void free underfill was also carried out based on dispensing temperature and patterns.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126654333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507176
Sung-Hyuk Kim, Jong-jin Park, Jae-Myeong Kim, S. Yoo, Young-Bae Park
The effects of surface finishes on the in situ interfacial reaction characteristics on both ball grid array (BGA) typed Sn-3.5Ag and Sn-0.7Cu lead-free solder bumps were investigated under annealing and electromigration (EM) test conditions of 135 °C to 170°C with 5.0 × 103 A/cm2. The failure mechanisms were explored in detail via in-situ EM tests. For the shear test, the shear force of both Sn-3.5Ag and Sn-0.7Cu solder joints increased and the shear energy decreased with increasing shear speed for the high speed of 1000 mm/s.
{"title":"Comparisons of the electrical and mechanical reliabilities between Sn-3.5Ag and Sn-0.7Cu Pb-free solder bumps","authors":"Sung-Hyuk Kim, Jong-jin Park, Jae-Myeong Kim, S. Yoo, Young-Bae Park","doi":"10.1109/EPTC.2012.6507176","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507176","url":null,"abstract":"The effects of surface finishes on the in situ interfacial reaction characteristics on both ball grid array (BGA) typed Sn-3.5Ag and Sn-0.7Cu lead-free solder bumps were investigated under annealing and electromigration (EM) test conditions of 135 °C to 170°C with 5.0 × 103 A/cm2. The failure mechanisms were explored in detail via in-situ EM tests. For the shear test, the shear force of both Sn-3.5Ag and Sn-0.7Cu solder joints increased and the shear energy decreased with increasing shear speed for the high speed of 1000 mm/s.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128136218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507075
J. M. Park, J. Kim, J. W. Kim, Y. Kim, S. Kim, Y. Park
In this study, effect interfacial bonding strength on pattern density was evaluated. The Silicon oxide(SiO2) on parallel patterned Cu lines wafer can be removed by using a solution of buffered oxide etch and sulfuric acid (BOE/H2SO4) to improve the bonding quality of Cu-Cu pattern direct bonds. Two 8-inch Cu wafers were bonded at 400°C via the thermocompression method. The interfacial adhesion energy of Cu-Cu pattern direct bonding was quantitatively measured by the four-point bending method. After BOE for 2 min/H2SO4 for 1 min wet pretreatment, the interfacial adhesion energies with pattern density of 0.06, and 0.23 were 7.9, and 4.1 J/m2, respectively. Therefore, the CMP planarization is critical to have reliable bonding quality of Cu pattern direct bonds.
{"title":"Pattern density effect on interfacial bonding characteristics of Cu-Cu direct bonds for 3D IC packages","authors":"J. M. Park, J. Kim, J. W. Kim, Y. Kim, S. Kim, Y. Park","doi":"10.1109/EPTC.2012.6507075","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507075","url":null,"abstract":"In this study, effect interfacial bonding strength on pattern density was evaluated. The Silicon oxide(SiO2) on parallel patterned Cu lines wafer can be removed by using a solution of buffered oxide etch and sulfuric acid (BOE/H2SO4) to improve the bonding quality of Cu-Cu pattern direct bonds. Two 8-inch Cu wafers were bonded at 400°C via the thermocompression method. The interfacial adhesion energy of Cu-Cu pattern direct bonding was quantitatively measured by the four-point bending method. After BOE for 2 min/H2SO4 for 1 min wet pretreatment, the interfacial adhesion energies with pattern density of 0.06, and 0.23 were 7.9, and 4.1 J/m2, respectively. Therefore, the CMP planarization is critical to have reliable bonding quality of Cu pattern direct bonds.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121798604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507092
L. Bogaerts, J. de Vos, C. Gerets, G. Jamieson, K. Vandersmissen, A. L. Manna
There are several motivations for moving to 3D IC technology. One of the key factors is performance enhancement which can be achieved by further miniaturization of the IC. As more and more functionality is required on a smaller footprint, 3D stacking is a very valuable solution. The increased use of multi-chip integration schemes that use microbumps, Cu pillars and TSVs introduces however severe requirements in term of bump uniformity, height, profile and pitch making 3D stacking exponentially challenging. In this paper we introduce some of the challenges to enable microbumps with pitch of 50μm and below. We also propose process optimizations to enable 3D face to face stacking of a test vehicle. An improvement of the bump plating has been demonstrated by adding a plasma treatment prior to plating. The optimized bumping process has been validated by shear test and electrical characterization of 3D stacks.
{"title":"Process related challenges for 3D face to face stacking test vehicles using a 40/50μm pitch CuSn microbump configuration","authors":"L. Bogaerts, J. de Vos, C. Gerets, G. Jamieson, K. Vandersmissen, A. L. Manna","doi":"10.1109/EPTC.2012.6507092","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507092","url":null,"abstract":"There are several motivations for moving to 3D IC technology. One of the key factors is performance enhancement which can be achieved by further miniaturization of the IC. As more and more functionality is required on a smaller footprint, 3D stacking is a very valuable solution. The increased use of multi-chip integration schemes that use microbumps, Cu pillars and TSVs introduces however severe requirements in term of bump uniformity, height, profile and pitch making 3D stacking exponentially challenging. In this paper we introduce some of the challenges to enable microbumps with pitch of 50μm and below. We also propose process optimizations to enable 3D face to face stacking of a test vehicle. An improvement of the bump plating has been demonstrated by adding a plasma treatment prior to plating. The optimized bumping process has been validated by shear test and electrical characterization of 3D stacks.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117017682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507095
H. Oppermann, M. Rothermund, N. Jurgensen, Uno Yen, K. Essig
In advanced packaging processes the chips are molded after placement and the chip bonding pads need to be opened by laser drilling. In order to avoid post bond measurements and any correction of individual drilling location it is important to establish a process of high precision die bonding. We investigated the die bonding of 50 μm thin silicon chips on Cu leadframe using thin layers of Au/Sn solder and studied the assembly with respect to solder joint formation, metallurgy, mechanical strength and finally the post bond accuracy achieved.
{"title":"Die bonding in embedded substrates","authors":"H. Oppermann, M. Rothermund, N. Jurgensen, Uno Yen, K. Essig","doi":"10.1109/EPTC.2012.6507095","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507095","url":null,"abstract":"In advanced packaging processes the chips are molded after placement and the chip bonding pads need to be opened by laser drilling. In order to avoid post bond measurements and any correction of individual drilling location it is important to establish a process of high precision die bonding. We investigated the die bonding of 50 μm thin silicon chips on Cu leadframe using thin layers of Au/Sn solder and studied the assembly with respect to solder joint formation, metallurgy, mechanical strength and finally the post bond accuracy achieved.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115048392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：