Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507112
Chin Hui Chong, Y. K. Tan
During the last few years, wafer technology has been shrinking aggressively from the 50nm node down to a much smaller technology node. This creates a disparity between die and packaging in which the die is miniaturizing, yet the packaging's physical footprint remains unchanged. Among the various packaging types, the one that is most impacted is board-on-chip (BOC) packaging, which is the current mainstream packaging for DDR2/DDR3 devices. The construction of the BOC package is a one-layer interposer with a window cut-out along the center; the die's active circuit faces down with respect to the package footprint. The interconnect between the die and package is wire, via the window cut-out. As the die shrinks, and the package footprint remains unchanged, one of the design bottlenecks is the trace fan-out issue from the bond finger to the innermost column of the ball, as well as the tighter bond finger pitch due to the die-pad pitch reduction. This paper will describe the design features that need be addressed for small-die packages — for example, the drive toward fine line trace, wire bond top pad width, and narrower bond slots. A test vehicle is tooled up as a simulation of possible manufacturing/process issues for the small-die package solution. The design and analysis of the experiment are described in full in this paper.
{"title":"Packaging challenges for small die","authors":"Chin Hui Chong, Y. K. Tan","doi":"10.1109/EPTC.2012.6507112","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507112","url":null,"abstract":"During the last few years, wafer technology has been shrinking aggressively from the 50nm node down to a much smaller technology node. This creates a disparity between die and packaging in which the die is miniaturizing, yet the packaging's physical footprint remains unchanged. Among the various packaging types, the one that is most impacted is board-on-chip (BOC) packaging, which is the current mainstream packaging for DDR2/DDR3 devices. The construction of the BOC package is a one-layer interposer with a window cut-out along the center; the die's active circuit faces down with respect to the package footprint. The interconnect between the die and package is wire, via the window cut-out. As the die shrinks, and the package footprint remains unchanged, one of the design bottlenecks is the trace fan-out issue from the bond finger to the innermost column of the ball, as well as the tighter bond finger pitch due to the die-pad pitch reduction. This paper will describe the design features that need be addressed for small-die packages — for example, the drive toward fine line trace, wire bond top pad width, and narrower bond slots. A test vehicle is tooled up as a simulation of possible manufacturing/process issues for the small-die package solution. The design and analysis of the experiment are described in full in this paper.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131173496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507109
T. Tran, V. Mathew, W. S. Koh, K. Yow, Y. K. Au
New automotive mission profiles include more than 3500 total hours at 150ºC. To satisfy new automotive requirements, plastic packages must meet AEC Grade 0 or higher. One key limitation of the conventional plastic package is the use of gold bond wire on aluminum bond pad. Au-Al intermetallic degradation due to intermetallic transformation in high temperature storage condition remains the main reliability concern. Pad re-metallization using nickel/palladium, nickel/gold or nickel/palladium/gold over aluminum bond pad or copper bond pad offers a noble and reliable metal interconnect. This study focused on the development of dicing process for low-K-copper wafers having aluminum pad re-metallized with electroless nickel / electroless palladium / immersion gold Over Pad Metallization (OPM). Development wafers were pizza mask wafers on which multiple die designs and scribe grid production control (SGPC) modules were designed. SGPC modules are designed with aluminum probe pads that are used to monitor wafer-level process control. All aluminum features on the wafer were plated with nickel/palladium/gold OPM. With nickel about four times as hard as aluminum, OPM plated SGPC's were much more difficult to dice than conventional SGPC's with aluminum pads. Cracking on silicon sidewall with crack propagating towards the die was found to cause back-end-of-line (BEOL) delamination and device failure. Surface roughness and hardness measurements were taken on OPM variations. Extensive mechanical dicing studies were conducted to modulate the failures and resolve the dicing challenge. Laser grooving followed by mechanical dicing of OPM wafers was also performed. Packages underwent extensive reliability stress conditions. The associated process improvements described in this paper supported a successful integration of a 55nm die technology in Low Profile Quad Flat Package with Exposed Pad (LQFP-EP) meeting and exceeding AEC grade 0 requirements.
新的汽车任务配置文件包括在150ºC下的总时间超过3500小时。为了满足新的汽车要求，塑料包装必须满足AEC 0级或更高的要求。传统塑料封装的一个关键限制是在铝键垫上使用金键线。高温贮存条件下金属间转化导致的金-铝金属间降解仍然是主要的可靠性问题。在铝键垫或铜键垫上使用镍/钯、镍/金或镍/钯/金的焊垫再金属化，提供高贵可靠的金属互连。研究了用化学镀镍/化学镀钯/浸金对铝衬垫进行再金属化的低钾铜晶片的切割工艺。开发晶圆是披萨掩模晶圆，在其上设计了多个模具设计和划线网格生产控制(SGPC)模块。SGPC模块采用铝制探头垫设计，用于监控晶圆级工艺控制。晶圆片上的所有铝特征都镀有镍/钯/金OPM。由于镍的硬度是铝的四倍，镀OPM的SGPC比镀铝的常规SGPC更难切割。硅侧壁开裂，裂纹向模具方向扩展，导致后端线(BEOL)分层和器件失效。对OPM变化进行了表面粗糙度和硬度测量。进行了广泛的机械切割研究，以调节故障并解决切割挑战。对OPM晶圆进行了激光刻槽和机械切割。封装经历了广泛的可靠性应力条件。本文中描述的相关工艺改进支持了55nm芯片技术在Low Profile Quad Flat Package with Exposed Pad (LQFP-EP)中的成功集成，达到并超过了AEC 0级要求。
{"title":"Overcoming dicing challenges for low-K copper wafers using nickel-palladium-gold bond pads for automotive application","authors":"T. Tran, V. Mathew, W. S. Koh, K. Yow, Y. K. Au","doi":"10.1109/EPTC.2012.6507109","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507109","url":null,"abstract":"New automotive mission profiles include more than 3500 total hours at 150ºC. To satisfy new automotive requirements, plastic packages must meet AEC Grade 0 or higher. One key limitation of the conventional plastic package is the use of gold bond wire on aluminum bond pad. Au-Al intermetallic degradation due to intermetallic transformation in high temperature storage condition remains the main reliability concern. Pad re-metallization using nickel/palladium, nickel/gold or nickel/palladium/gold over aluminum bond pad or copper bond pad offers a noble and reliable metal interconnect. This study focused on the development of dicing process for low-K-copper wafers having aluminum pad re-metallized with electroless nickel / electroless palladium / immersion gold Over Pad Metallization (OPM). Development wafers were pizza mask wafers on which multiple die designs and scribe grid production control (SGPC) modules were designed. SGPC modules are designed with aluminum probe pads that are used to monitor wafer-level process control. All aluminum features on the wafer were plated with nickel/palladium/gold OPM. With nickel about four times as hard as aluminum, OPM plated SGPC's were much more difficult to dice than conventional SGPC's with aluminum pads. Cracking on silicon sidewall with crack propagating towards the die was found to cause back-end-of-line (BEOL) delamination and device failure. Surface roughness and hardness measurements were taken on OPM variations. Extensive mechanical dicing studies were conducted to modulate the failures and resolve the dicing challenge. Laser grooving followed by mechanical dicing of OPM wafers was also performed. Packages underwent extensive reliability stress conditions. The associated process improvements described in this paper supported a successful integration of a 55nm die technology in Low Profile Quad Flat Package with Exposed Pad (LQFP-EP) meeting and exceeding AEC grade 0 requirements.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134283461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507089
Lim Fui Yee, Calvin Lo Wai Yew
Copper wire bond remains a challenge especially on bond pads with sensitive pad metallization. Extensive work and analysis are needed at the onset of the packaging development phase to meet the right level of manufacturability and reliability requirement. Wire bond related issue is not uncommon even after qualification and after years in high volume manufacturing. The process development gets even tougher for finer wire diameter, bond pads with less than 1μm aluminum thickness and of higher via density structure. A workable wire bond process window is needed upfront. Key is to have a window defined to balance between pad cratering and lifted ball bond due to the harder property of the copper wire. Wire bond process optimization commonly focus around bond time, bond force and bond power (USG). Other factors generally evaluated for copper wire bonding include incoming bond pad cleanliness, bonding pad surface oxidation, wire oxidation during EFO and forming gas flow rate. A lesser known variable, die attach, is often overlooked in packaging or gold to copper wire conversion. Die attach material out gassing at cure is a common hypothesis whenever there is bond pad surface contamination issue. But with the advancement in technology and new material development, out gassing risk is low if the material is cured per the supplier recommendation. Therefore, investigation on weak bond is generally focused more on the wire bond process and incoming bonding pad condition rather than the die attach material. In this paper, investigation on non stick and copper wire bond was carried out. A well defined copper wire bond process on sensitive bonding pads is developed using statistical approach in the form of design of experiment (DOE) and response surface methodology (RSM). Surface analysis methodology using SEM, EDS and AES were also utilized to check for bond pad contamination. To understand deeper into the issue and mechanics of the failure, process mapping and brainstorming sessions have also been carried out. Variables involving wafer saw, pre-wire bond plasma, different batches of wafers, die attach bond line thickness and tilt variation have all been studied thoroughly. Eventually, the root cause of copper wire bond issue been identified to be die attach material related. A strong correlation has been found between lifted wire and the die attach material modulus. There is no more lifted ball concern after changing of the die attach material to a material of a suitable modulus. There is no significant difference in the die attach bond line thickness, coverage and voids among others, comparing with the original die attach material. All the wire bond responses including pad cratering, Al-Cu intermetallic (IMC), wire pull and ball shear have been validated to have no issue at a larger sample size. Reliability assessment in the form of preconditioning, temperature cycling and bias HAST have also passed with no sign of interfacial mechanical failure or test fai
{"title":"Die attach materials impacts to copper wire bonding: New challenges","authors":"Lim Fui Yee, Calvin Lo Wai Yew","doi":"10.1109/EPTC.2012.6507089","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507089","url":null,"abstract":"Copper wire bond remains a challenge especially on bond pads with sensitive pad metallization. Extensive work and analysis are needed at the onset of the packaging development phase to meet the right level of manufacturability and reliability requirement. Wire bond related issue is not uncommon even after qualification and after years in high volume manufacturing. The process development gets even tougher for finer wire diameter, bond pads with less than 1μm aluminum thickness and of higher via density structure. A workable wire bond process window is needed upfront. Key is to have a window defined to balance between pad cratering and lifted ball bond due to the harder property of the copper wire. Wire bond process optimization commonly focus around bond time, bond force and bond power (USG). Other factors generally evaluated for copper wire bonding include incoming bond pad cleanliness, bonding pad surface oxidation, wire oxidation during EFO and forming gas flow rate. A lesser known variable, die attach, is often overlooked in packaging or gold to copper wire conversion. Die attach material out gassing at cure is a common hypothesis whenever there is bond pad surface contamination issue. But with the advancement in technology and new material development, out gassing risk is low if the material is cured per the supplier recommendation. Therefore, investigation on weak bond is generally focused more on the wire bond process and incoming bonding pad condition rather than the die attach material. In this paper, investigation on non stick and copper wire bond was carried out. A well defined copper wire bond process on sensitive bonding pads is developed using statistical approach in the form of design of experiment (DOE) and response surface methodology (RSM). Surface analysis methodology using SEM, EDS and AES were also utilized to check for bond pad contamination. To understand deeper into the issue and mechanics of the failure, process mapping and brainstorming sessions have also been carried out. Variables involving wafer saw, pre-wire bond plasma, different batches of wafers, die attach bond line thickness and tilt variation have all been studied thoroughly. Eventually, the root cause of copper wire bond issue been identified to be die attach material related. A strong correlation has been found between lifted wire and the die attach material modulus. There is no more lifted ball concern after changing of the die attach material to a material of a suitable modulus. There is no significant difference in the die attach bond line thickness, coverage and voids among others, comparing with the original die attach material. All the wire bond responses including pad cratering, Al-Cu intermetallic (IMC), wire pull and ball shear have been validated to have no issue at a larger sample size. Reliability assessment in the form of preconditioning, temperature cycling and bias HAST have also passed with no sign of interfacial mechanical failure or test fai","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131255250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507051
M. Hamidullah, A. T. Lin, B. Han, Y. Yoon
This paper presents the integration of miniaturized MEMS tri-axial tactile sensor with surgical needle for robotic assisted minimally invasive surgery (MIS). In MIS, surgeons rely highly on the tactile feedback from the tip of the needle. Sensorized surgical needle will be able to provide quantitative tactile feedback to increase accuracy and reduce risk of overcutting. The sensorized surgical needle could also be integrated with actuator system for robotic assisted minimally invasive surgery.
{"title":"A sensorized surgical needle with miniaturized MEMS tri-axial force sensor for robotic assisted minimally invasive surgery","authors":"M. Hamidullah, A. T. Lin, B. Han, Y. Yoon","doi":"10.1109/EPTC.2012.6507051","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507051","url":null,"abstract":"This paper presents the integration of miniaturized MEMS tri-axial tactile sensor with surgical needle for robotic assisted minimally invasive surgery (MIS). In MIS, surgeons rely highly on the tactile feedback from the tip of the needle. Sensorized surgical needle will be able to provide quantitative tactile feedback to increase accuracy and reduce risk of overcutting. The sensorized surgical needle could also be integrated with actuator system for robotic assisted minimally invasive surgery.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124437354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507150
S. Somasundaram, A. Tay
An optimal spray cooling system would deliver just the right amount of coolant to remove the required heat flux and simultaneously avoid both, a dry out scenario and a thick film (of coolant) deposition on the surface. In most systems, the heat flux varies temporally and the object to be cooled needs to be maintained within a particular temperature range. Promoting phase change helps in reducing coolant requirement. One of the ways to meet all the three requirements is by intermittent spray cooling (ISC), in which the spray mechanism is activated only when the temperature starts rising above a set limit. A commercially available, low flow rate, nozzle was used along with a micro-solenoid valve to implement intermittent spray cooling. A thermal test chip (with integrated heaters to simulate heat source and diodes which act as temperature sensors) was used as target surface to be cooled. De-ionized water was used as coolant and flow rate was within the range of 0.25–0.5 ml/sec. Both steady state (continuous sprays) and intermittent spray cooling experiments were conducted. The main objective of this work is to study the effect of different parameters (heat flux, flow rate, and set-point temperature) on the fluctuation (amplitude) of surface temperature, heat transfer coefficient, valve frequency and on-off periods. Transient temperature fluctuations, transient heat transfer coefficients and frequency of the process were recorded for nozzle pressures of 2, 4 and 6 bar for heat fluxes of 11, 22, and 33 Watts/cm2 at 5, 10 and 15 °C above the steady state temperature. This paper attempts to understand the various physical factors which affect and dominate the intermittent spray cooling process. An important conclusion is that the temperature fluctuations are minimized when the surface temperature is at sufficient superheat, due to the cushioning effect provided by the evaporation/boiling of the liquid film present on the surface during spray off period.
{"title":"Intermittent spray cooling — Solution to optimize spray cooling","authors":"S. Somasundaram, A. Tay","doi":"10.1109/EPTC.2012.6507150","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507150","url":null,"abstract":"An optimal spray cooling system would deliver just the right amount of coolant to remove the required heat flux and simultaneously avoid both, a dry out scenario and a thick film (of coolant) deposition on the surface. In most systems, the heat flux varies temporally and the object to be cooled needs to be maintained within a particular temperature range. Promoting phase change helps in reducing coolant requirement. One of the ways to meet all the three requirements is by intermittent spray cooling (ISC), in which the spray mechanism is activated only when the temperature starts rising above a set limit. A commercially available, low flow rate, nozzle was used along with a micro-solenoid valve to implement intermittent spray cooling. A thermal test chip (with integrated heaters to simulate heat source and diodes which act as temperature sensors) was used as target surface to be cooled. De-ionized water was used as coolant and flow rate was within the range of 0.25–0.5 ml/sec. Both steady state (continuous sprays) and intermittent spray cooling experiments were conducted. The main objective of this work is to study the effect of different parameters (heat flux, flow rate, and set-point temperature) on the fluctuation (amplitude) of surface temperature, heat transfer coefficient, valve frequency and on-off periods. Transient temperature fluctuations, transient heat transfer coefficients and frequency of the process were recorded for nozzle pressures of 2, 4 and 6 bar for heat fluxes of 11, 22, and 33 Watts/cm2 at 5, 10 and 15 °C above the steady state temperature. This paper attempts to understand the various physical factors which affect and dominate the intermittent spray cooling process. An important conclusion is that the temperature fluctuations are minimized when the surface temperature is at sufficient superheat, due to the cushioning effect provided by the evaporation/boiling of the liquid film present on the surface during spray off period.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123468369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507059
E. Seler, M. Wojnowski, G. Sommer, R. Weigel
Embedded Wafer Level Ball Grid Array (eWLB) is one of the most advantageous packaging technologies with respect to higher I/O density, process easiness, integration flexibilities and electrical performance. When it comes to high-frequency (HF), the latter has to be considered particularly. The Quad Flat no Leads Package (VQFN) has often been the choice due to good HF-performance. We present the comparison of the two package technologies eWLB and VQFN. In this paper we present an optimized 24 GHz chip-package-board transition. We compare the performance of an eWLB package to a VQFN package. We focus on a single-ended transition. We obtain a simulated insertion loss better than −0.5 dB in eWLB compared to −1.5 dB in VQFN. In this contribution we show the outstanding potential of the eWLB package for mm-wave applications.
{"title":"Comparative analysis of high-frequency transitions in Embedded Wafer Level BGA (eWLB) and Quad Flat no Leads (VQFN) Packages","authors":"E. Seler, M. Wojnowski, G. Sommer, R. Weigel","doi":"10.1109/EPTC.2012.6507059","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507059","url":null,"abstract":"Embedded Wafer Level Ball Grid Array (eWLB) is one of the most advantageous packaging technologies with respect to higher I/O density, process easiness, integration flexibilities and electrical performance. When it comes to high-frequency (HF), the latter has to be considered particularly. The Quad Flat no Leads Package (VQFN) has often been the choice due to good HF-performance. We present the comparison of the two package technologies eWLB and VQFN. In this paper we present an optimized 24 GHz chip-package-board transition. We compare the performance of an eWLB package to a VQFN package. We focus on a single-ended transition. We obtain a simulated insertion loss better than −0.5 dB in eWLB compared to −1.5 dB in VQFN. In this contribution we show the outstanding potential of the eWLB package for mm-wave applications.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121054051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507086
Xiaowu Zhang, C. Selvanayagam, W. Y. Yong, T. Chai, A. Trigg
In wirebonding, high stresses applied onto the pad during the ultrasonic bonding can result in pad damage, silicon cratering and aluminium splash — all of which ultimately result in poor joint quality. Cracking in the Cu/low-k and Cu/ultra low-k layers beneath the pad (also a result of high applied stresses) is a common issue with wirebonding. As a result of these failures in the substrate and the poor quality of joints made, there is much interest to measure and map the stress distribution (σxx, σyy, σzz, σxy) beneath the bond pad. This information coupled with failure analysis would provide engineers with the information required to form more robust wirebonds. Current methods to measure this stress involve mechanical simulation for extrapolation of stress from the measured regions to the unmeasured regions. This paper presents the novel micro-sensor designs by using the various piezoresistive stress sensors to measure the four components of stress below the bond pad so that the stresses can be correlated with failure mechanism of the wirebond. This would provide a complete picture of what causes the failure of wirebonds. The advantage of this method is that the four components of stress at a very localized region can be determined.
{"title":"Design and development of micro-sensors for measuring localised stresses during copper wirebonding","authors":"Xiaowu Zhang, C. Selvanayagam, W. Y. Yong, T. Chai, A. Trigg","doi":"10.1109/EPTC.2012.6507086","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507086","url":null,"abstract":"In wirebonding, high stresses applied onto the pad during the ultrasonic bonding can result in pad damage, silicon cratering and aluminium splash — all of which ultimately result in poor joint quality. Cracking in the Cu/low-k and Cu/ultra low-k layers beneath the pad (also a result of high applied stresses) is a common issue with wirebonding. As a result of these failures in the substrate and the poor quality of joints made, there is much interest to measure and map the stress distribution (σxx, σyy, σzz, σxy) beneath the bond pad. This information coupled with failure analysis would provide engineers with the information required to form more robust wirebonds. Current methods to measure this stress involve mechanical simulation for extrapolation of stress from the measured regions to the unmeasured regions. This paper presents the novel micro-sensor designs by using the various piezoresistive stress sensors to measure the four components of stress below the bond pad so that the stresses can be correlated with failure mechanism of the wirebond. This would provide a complete picture of what causes the failure of wirebonds. The advantage of this method is that the four components of stress at a very localized region can be determined.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128753005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507041
K. Zoschke, H. Oppermann, C. Manier, I. Ndip, R. Puschmann, O. Ehrmann, J. Wolf, K. Lang
This paper presents a detailed description of the fabrication steps for wafer level processing of silicon interposers with copper filled TSVs as well as their subsequent assembly treatment. The electrical performance and characterization of the TSVs is also discussed. The interposers are created at 200 mm or 300 mm silicon wafers. The fabrication processes include deep reactive ion etching, TSV side wall isolation, PVD seed layer deposition, TSV filling by copper electroplating, wafer front side redistribution, temporary wafer bonding, wafer thinning by mechanical grinding, CMP, silicon dry etching, PECVD, silicon oxide dry etching and wafer backside redistribution. Depending on the final device application, after backside processing a component assembly is done directly at the interposer backside. In other cases, the interposer wafers are either released from the carrier wafers or transfer bonded so that their front side can be accessed again and the component assembly can be done. Finally, the assembled interposers can be release from their carrier wafers and singulated or run into further processes like molding or hermetic sealing by wafer to wafer bonding using suitable capwafers. In the following sections, important technological aspects of interposer fabrication and assembly as well as results from electrical characterizations will be presented. Detailed discussion of produced evaluation devices will explain and outline the versatility of the silicon interposer approach to be a flexible base technology for different application scenarios.
{"title":"Wafer level 3D system integration based on silicon interposers with through silicon vias","authors":"K. Zoschke, H. Oppermann, C. Manier, I. Ndip, R. Puschmann, O. Ehrmann, J. Wolf, K. Lang","doi":"10.1109/EPTC.2012.6507041","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507041","url":null,"abstract":"This paper presents a detailed description of the fabrication steps for wafer level processing of silicon interposers with copper filled TSVs as well as their subsequent assembly treatment. The electrical performance and characterization of the TSVs is also discussed. The interposers are created at 200 mm or 300 mm silicon wafers. The fabrication processes include deep reactive ion etching, TSV side wall isolation, PVD seed layer deposition, TSV filling by copper electroplating, wafer front side redistribution, temporary wafer bonding, wafer thinning by mechanical grinding, CMP, silicon dry etching, PECVD, silicon oxide dry etching and wafer backside redistribution. Depending on the final device application, after backside processing a component assembly is done directly at the interposer backside. In other cases, the interposer wafers are either released from the carrier wafers or transfer bonded so that their front side can be accessed again and the component assembly can be done. Finally, the assembled interposers can be release from their carrier wafers and singulated or run into further processes like molding or hermetic sealing by wafer to wafer bonding using suitable capwafers. In the following sections, important technological aspects of interposer fabrication and assembly as well as results from electrical characterizations will be presented. Detailed discussion of produced evaluation devices will explain and outline the versatility of the silicon interposer approach to be a flexible base technology for different application scenarios.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125784965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507139
X. Jing, Daquan Yu, L. Wan
Detecting through silicon via (TSV) associated defects non-destructively immediately after the fabrication process, or in failure analysis is of great interest and is a challenge. This paper reports on the inspections of 5 to 30 μm diameter TSVs by the state-of-the-art, commercially available X-ray systems, exemplifying a generally preferred method for non-invasively identifying metallization defects in vias as well as in joining structures. The principle of X-ray imaging for TSV measurement is discussed and illustrated, and three dimensional TSV structures are reconstructed by computed tomography (CT). Methods to achieve high-resolution TSV X-ray imaging are discussed.
{"title":"Non-destructive testing of through silicon vias by high-resolution X-ray/CT techniques","authors":"X. Jing, Daquan Yu, L. Wan","doi":"10.1109/EPTC.2012.6507139","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507139","url":null,"abstract":"Detecting through silicon via (TSV) associated defects non-destructively immediately after the fabrication process, or in failure analysis is of great interest and is a challenge. This paper reports on the inspections of 5 to 30 μm diameter TSVs by the state-of-the-art, commercially available X-ray systems, exemplifying a generally preferred method for non-invasively identifying metallization defects in vias as well as in joining structures. The principle of X-ray imaging for TSV measurement is discussed and illustrated, and three dimensional TSV structures are reconstructed by computed tomography (CT). Methods to achieve high-resolution TSV X-ray imaging are discussed.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126091184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507172
N. Wan
This paper presents the results of a two-part study to investigate the package and board-level thermo-mechanical reliability of a 2-COB/4-COB high-density multichip package for highperformance server applications. The first part of this paper presents package-level simulation performed on 2-COB/4-COB packages showed that the packages experienced very high localized stress at the active surface edge of the bottom die. This was due to a localized stiffness and thermal coefficient of expansion mismatch between the silicon die, epoxy, and mold compound. In particular, the mismatch occurred in the resin-rich region and the area of incomplete epoxy coverage. Simulation demonstrated that the model with silicon spacer die stacking technology significantly reduced stress, and was adopted as a solution to improve the package reliability performance. The second part of this paper presents results for board-level simulation conducted to understand the effect of die stacking methods (silicon spacer, epoxy, and film-over-wire) on solder joint reliability. Results indicate that conversion to the silicon spacer stack method solves package-level reliability issues at the expense of board-level solder joint reliability (SJR). This can jeopardize the ability of the product to meet customer with more stringent requirements. Therefore, a fine balance between packaging and board-level reliability must be achieved. As a follow-up to this study, a work was initiated to improve boardlevel SJR for multiple large die stack packages in order to improve the performance margin.
{"title":"High-density DRAM package simulation","authors":"N. Wan","doi":"10.1109/EPTC.2012.6507172","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507172","url":null,"abstract":"This paper presents the results of a two-part study to investigate the package and board-level thermo-mechanical reliability of a 2-COB/4-COB high-density multichip package for highperformance server applications. The first part of this paper presents package-level simulation performed on 2-COB/4-COB packages showed that the packages experienced very high localized stress at the active surface edge of the bottom die. This was due to a localized stiffness and thermal coefficient of expansion mismatch between the silicon die, epoxy, and mold compound. In particular, the mismatch occurred in the resin-rich region and the area of incomplete epoxy coverage. Simulation demonstrated that the model with silicon spacer die stacking technology significantly reduced stress, and was adopted as a solution to improve the package reliability performance. The second part of this paper presents results for board-level simulation conducted to understand the effect of die stacking methods (silicon spacer, epoxy, and film-over-wire) on solder joint reliability. Results indicate that conversion to the silicon spacer stack method solves package-level reliability issues at the expense of board-level solder joint reliability (SJR). This can jeopardize the ability of the product to meet customer with more stringent requirements. Therefore, a fine balance between packaging and board-level reliability must be achieved. As a follow-up to this study, a work was initiated to improve boardlevel SJR for multiple large die stack packages in order to improve the performance margin.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125182401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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