Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507130
C. Bailey, X. Zhu, H. Lu, C. Yin
In recent years, high density packaging (HDP) in electronics manufacturing has been increasingly adopted to meet the needs of miniaturization and increasing functionality in electronic products. One of the failure mechanisms that is causing considerable concern is Electro-migration (EM). EM is due to metal transportation at the atomic level caused by high current density which is an inevitable consequence of miniaturization. EM is known to cause voids and hill-locks in metal conductors and in the worst cases, this leads to open or short circuits. Moreover, higher current density and complexity of interconnect structures also generates high temperature and stress gradients which result in void formation due to thermo-migration and stress-migration respectively in conductors. As a result, the true causes of metal migration involve a multi-physical cross coupling relationship and are hard understood and characterize. For example, in flip-chip interconnects the ever decreasing size of solder joints can lead to current densities reaching 10 A/cm, these will promote electro-migration but also result in high temperature and stress gradients which need to be understood, particularly when aiming to develop qualification tests for this phenomena.
{"title":"Modelling metal migration for high reliability components when subjected to thermo-mechanical loading","authors":"C. Bailey, X. Zhu, H. Lu, C. Yin","doi":"10.1109/EPTC.2012.6507130","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507130","url":null,"abstract":"In recent years, high density packaging (HDP) in electronics manufacturing has been increasingly adopted to meet the needs of miniaturization and increasing functionality in electronic products. One of the failure mechanisms that is causing considerable concern is Electro-migration (EM). EM is due to metal transportation at the atomic level caused by high current density which is an inevitable consequence of miniaturization. EM is known to cause voids and hill-locks in metal conductors and in the worst cases, this leads to open or short circuits. Moreover, higher current density and complexity of interconnect structures also generates high temperature and stress gradients which result in void formation due to thermo-migration and stress-migration respectively in conductors. As a result, the true causes of metal migration involve a multi-physical cross coupling relationship and are hard understood and characterize. For example, in flip-chip interconnects the ever decreasing size of solder joints can lead to current densities reaching 10 A/cm, these will promote electro-migration but also result in high temperature and stress gradients which need to be understood, particularly when aiming to develop qualification tests for this phenomena.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124843069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507188
C. Hunat, Carolyn Tubulo, Chuen Khiang Wang, R. Liang, N. Suthiwongsunthorn
In this paper we presented methods of optimizing a 17×17mm LFBGA package having improve its electrical performance using an electromagnetic-field software through simulation, particularly on controlled signals (single-end & differential pairs) and high-speed I/O signal traces.
{"title":"Design optimization for electrical performance of a LFBGA package using EM-field simulation","authors":"C. Hunat, Carolyn Tubulo, Chuen Khiang Wang, R. Liang, N. Suthiwongsunthorn","doi":"10.1109/EPTC.2012.6507188","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507188","url":null,"abstract":"In this paper we presented methods of optimizing a 17×17mm LFBGA package having improve its electrical performance using an electromagnetic-field software through simulation, particularly on controlled signals (single-end & differential pairs) and high-speed I/O signal traces.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123401968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507145
Jaewung Lee, Wei-Shan Wang, J. Sharma, Yu-Ching Lin, M. Esashi, Chen Bangtao, Navab Singh
This paper presents the application of the Nano Porous Gold (NPG) for encapsulating the MicroElectroMechanical System (MEMS) devices. The NPG was realized by selective etching of the Sn from electroplated AuSn alloy on ap articular seed layer. However, it is very difficult to form through pores during selective etching process as seed layer does not contain Sn. This seed layer acts as barrier for the application of Thin Film Encapsulation (TFE) which need through etch holes in cap layer to remove the sacrificial layer underneath. So in this paper, different seed mater ials were studied to find comptability of the material with AuSn alloy as well as their suitability in easy etching to form the through etch holes after NPG formation. Cu and Ni were found the suitable seed layer for forming the AuSn alloy. During the above study, it was found that current density for electroplating of AuSn alloy is also very important parameter to fabricate the uniform AuSn alloy. It was found that 1.25 mA/cm2 is the optimum current density to achieve the AuSn alloy for TFE application. These parameters were used for demonstration of TFE.
{"title":"Development and evaluation of the porous Au structure for the thin film encapsulation","authors":"Jaewung Lee, Wei-Shan Wang, J. Sharma, Yu-Ching Lin, M. Esashi, Chen Bangtao, Navab Singh","doi":"10.1109/EPTC.2012.6507145","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507145","url":null,"abstract":"This paper presents the application of the Nano Porous Gold (NPG) for encapsulating the MicroElectroMechanical System (MEMS) devices. The NPG was realized by selective etching of the Sn from electroplated AuSn alloy on ap articular seed layer. However, it is very difficult to form through pores during selective etching process as seed layer does not contain Sn. This seed layer acts as barrier for the application of Thin Film Encapsulation (TFE) which need through etch holes in cap layer to remove the sacrificial layer underneath. So in this paper, different seed mater ials were studied to find comptability of the material with AuSn alloy as well as their suitability in easy etching to form the through etch holes after NPG formation. Cu and Ni were found the suitable seed layer for forming the AuSn alloy. During the above study, it was found that current density for electroplating of AuSn alloy is also very important parameter to fabricate the uniform AuSn alloy. It was found that 1.25 mA/cm2 is the optimum current density to achieve the AuSn alloy for TFE application. These parameters were used for demonstration of TFE.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129631846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507069
L. Zhang, H. Li, G. Lo, C. Tan
Through-silicon-via (TSV) as a key enabler for three-dimensional (3D) integration provides electrical connections between stacked functional dies. This work examines the thermal characteristics of the TSV arrays and experimentally demonstrates that TSV arrays embedded in silicon substrate can be utilized as an effective heat removal element that helps in both heat dissipation and management of 3D integration. It is found that the use of appropriate TSV arrays which surround and are placed beneath a temperature sensor has an effective cooling capability as much as ∼40°C.
{"title":"Thermal characterization of TSV array as heat removal element in 3D IC stacking","authors":"L. Zhang, H. Li, G. Lo, C. Tan","doi":"10.1109/EPTC.2012.6507069","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507069","url":null,"abstract":"Through-silicon-via (TSV) as a key enabler for three-dimensional (3D) integration provides electrical connections between stacked functional dies. This work examines the thermal characteristics of the TSV arrays and experimentally demonstrates that TSV arrays embedded in silicon substrate can be utilized as an effective heat removal element that helps in both heat dissipation and management of 3D integration. It is found that the use of appropriate TSV arrays which surround and are placed beneath a temperature sensor has an effective cooling capability as much as ∼40°C.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129810458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507066
Q. Qi, D. Monthei
Die attach is a crucial ingredient of the overall solution to ensure that a PA device can function with acceptable junction temperature during peak power operation over the target service life, while mitigating thermo-mechanical stresses incurred by the mismatch of coefficients of thermal expansion between GaN device and substrate materials during temperature excursion. Traditionally, thermal and stress analyses must be performed separately and with different numerical analysis tools. This process can be lengthy and time consuming and more often than not an optimized thermal solution will not coincide with an optimized mechanical solution. Such a dilemma provides the impetus for what is reported here: development of an analytical tool for concurrent thermal and stress analyses and quick turn die attach optimization. Thermal solutions are based on the approach reported by Muzychka et al. that accounts for general device level thermal spreading resistance; the infinite series summation solution was adapted to GaN device configurations that allows device design and die attach optimizations at the same time by, unlike numerical solutions, showing the individual contributing factors to the overall thermal resistances. If the input power level and user environment are known for a particular device, junction temperature may be calculated and used to calibrate the model accuracy with, say, high resolution IR thermal imaging measurement or independent FEA analysis. Once calibration is confirmed, trend prediction can then be performed to assess the impacts of different design parameters as well as die attach materials on the device thermal performance. Thermo-mechanical stress solutions are based on the bimetallic beam theories originally attributed to Timoshenko and later improved by Suhir and others. This 2D approach utilizes close-form analytical solutions and captures the dominant behavior of the stress distributions inside the die attach layer. For a given die attach material and bond-line-thickness (BLT), von Mises stress can be readily calculated and results for die attach materials can then be assessed side by side with the thermal analysis results. An iterative loop may be initiated based on the independent but yet integrated analysis methodologies presented here: thermal analysis to optimize the device design with selection of die attaches material and stress analysis to verify the selected die attach does not induce excessive stress under thermal loading. Iteration stops when the selected die attach achieves a balance among factors such as acceptable junction to case thermal resistance and lower die attach von Mises stress, in addition to cost, shelf life, processing condition, etc. considerations. A case study will be demonstrated to show how the developed tool can be applied to help shorten the die attach selection cycle with optimization and trend predictions.
在整个解决方案中，贴片是一个至关重要的组成部分，它可以确保PA器件在目标使用寿命内的峰值功率工作期间能够以可接受的结温运行，同时减轻温度偏移期间GaN器件和衬底材料之间热膨胀系数不匹配所产生的热机械应力。传统上，热分析和应力分析必须分开进行，并使用不同的数值分析工具。这个过程可能是漫长而耗时的，而且通常优化的热解决方案不会与优化的机械解决方案一致。这样的困境提供了什么是在这里报道的动力:一个分析工具的发展，并发热应力分析和快速翻模附件优化。热解决方案基于Muzychka等人报告的方法，该方法考虑了一般器件级的热扩散阻力;无限级数求和解决方案适用于GaN器件配置，允许器件设计和芯片连接优化同时进行，与数值解决方案不同，它显示了影响整体热阻的各个因素。如果特定设备的输入功率水平和用户环境已知，则可以计算结温，并使用高分辨率红外热成像测量或独立有限元分析来校准模型精度。一旦校准得到确认，就可以进行趋势预测，以评估不同设计参数以及模具贴附材料对器件热性能的影响。热机械应力解基于双金属梁理论，最初归因于Timoshenko，后来由Suhir和其他人改进。这种二维方法利用闭合形式的解析解，并捕获了模具附着层内应力分布的主要行为。对于给定的模具附着材料和粘结线厚度(BLT)， von Mises应力可以很容易地计算出来，然后可以将模具附着材料的结果与热分析结果并排评估。一个迭代循环可以基于独立但集成的分析方法在这里提出:热分析，以优化器件设计，选择模具附件材料和应力分析，以验证所选择的模具附件在热载荷下不会引起过大的应力。除了成本、保质期、加工条件等方面的考虑外，当所选贴片在可接受的结壳热阻和较低的贴片von Mises应力等因素之间达到平衡时，迭代停止。一个案例研究将展示如何开发的工具可以应用于帮助缩短模具附件选择周期与优化和趋势预测。
{"title":"An analytical thermal and stress analysis tool for die attach optimization in GaN power amplifier (PA) applications","authors":"Q. Qi, D. Monthei","doi":"10.1109/EPTC.2012.6507066","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507066","url":null,"abstract":"Die attach is a crucial ingredient of the overall solution to ensure that a PA device can function with acceptable junction temperature during peak power operation over the target service life, while mitigating thermo-mechanical stresses incurred by the mismatch of coefficients of thermal expansion between GaN device and substrate materials during temperature excursion. Traditionally, thermal and stress analyses must be performed separately and with different numerical analysis tools. This process can be lengthy and time consuming and more often than not an optimized thermal solution will not coincide with an optimized mechanical solution. Such a dilemma provides the impetus for what is reported here: development of an analytical tool for concurrent thermal and stress analyses and quick turn die attach optimization. Thermal solutions are based on the approach reported by Muzychka et al. that accounts for general device level thermal spreading resistance; the infinite series summation solution was adapted to GaN device configurations that allows device design and die attach optimizations at the same time by, unlike numerical solutions, showing the individual contributing factors to the overall thermal resistances. If the input power level and user environment are known for a particular device, junction temperature may be calculated and used to calibrate the model accuracy with, say, high resolution IR thermal imaging measurement or independent FEA analysis. Once calibration is confirmed, trend prediction can then be performed to assess the impacts of different design parameters as well as die attach materials on the device thermal performance. Thermo-mechanical stress solutions are based on the bimetallic beam theories originally attributed to Timoshenko and later improved by Suhir and others. This 2D approach utilizes close-form analytical solutions and captures the dominant behavior of the stress distributions inside the die attach layer. For a given die attach material and bond-line-thickness (BLT), von Mises stress can be readily calculated and results for die attach materials can then be assessed side by side with the thermal analysis results. An iterative loop may be initiated based on the independent but yet integrated analysis methodologies presented here: thermal analysis to optimize the device design with selection of die attaches material and stress analysis to verify the selected die attach does not induce excessive stress under thermal loading. Iteration stops when the selected die attach achieves a balance among factors such as acceptable junction to case thermal resistance and lower die attach von Mises stress, in addition to cost, shelf life, processing condition, etc. considerations. A case study will be demonstrated to show how the developed tool can be applied to help shorten the die attach selection cycle with optimization and trend predictions.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125532904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507040
K. Muniandy, S. Hian, Teng Seng Kiong
Center Gate Molding or also known as Pin Gate Molding is a molding method that is gaining a lot of interest in the market in recent times. This is due to its improvement in wire sweep performance for ultra fine pitch wire bonding and ability to capitalize desirable mold compound mechanical properties. The main reason for this is the mold flow of the compound is radial with the wire which will minimize flow stress on bonded wire rather than opposing the wire in the typical side gate molding. This paper discusses the key challenges and the improvements that have been implemented for the center gate molding for the cavity down TBGA (Tape Ball Grid Array) package in the High Volume Manufacturing (HVM). Substrate type which includes the different stack up of the polyimide tape was one of the major concerns for implementing molding on the cavity down TBGA package. The various substrate stack up of the polyimide tape were evaluated and Design of Experiments (DOE) were applied to determine the optimum molding process conditions in order to achieve a material set for overall process robustness.
{"title":"Center Gate Molding challenges and improvements for cavity down TBGA packages","authors":"K. Muniandy, S. Hian, Teng Seng Kiong","doi":"10.1109/EPTC.2012.6507040","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507040","url":null,"abstract":"Center Gate Molding or also known as Pin Gate Molding is a molding method that is gaining a lot of interest in the market in recent times. This is due to its improvement in wire sweep performance for ultra fine pitch wire bonding and ability to capitalize desirable mold compound mechanical properties. The main reason for this is the mold flow of the compound is radial with the wire which will minimize flow stress on bonded wire rather than opposing the wire in the typical side gate molding. This paper discusses the key challenges and the improvements that have been implemented for the center gate molding for the cavity down TBGA (Tape Ball Grid Array) package in the High Volume Manufacturing (HVM). Substrate type which includes the different stack up of the polyimide tape was one of the major concerns for implementing molding on the cavity down TBGA package. The various substrate stack up of the polyimide tape were evaluated and Design of Experiments (DOE) were applied to determine the optimum molding process conditions in order to achieve a material set for overall process robustness.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121207757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507110
L. Wai, D. Zhi, V. S. Rao, Min Woo Daniel Rhee
In this paper, die attach process characterization on two type of highly conductive silver paste die attach materials was discussed. The first silver paste die attach materials (DA1) was used as a reference which is silver-loaded epoxy adhesive with high thermal conductivity of 60W/mK and electrical conductivity of 16Ms/m. Second silver paste die attach material (DA2) can be sintered with low pressure or pressure-less at temperature of 220°C to 280°C. DA2 material acquires high thermal conductivity range of 100–170W/mK and electrical conductivity range of 12–15Ms/m. Process specifications were set at die tilt < 1%, average bond line thickness between 25μm to 50μm and full die attach materials coverage without overflow of materials on top of die's surface. Process was optimized with 70μm thin silicon daisy chain chip with die size of 5mm×5mm on Ag plated QFN lead frame for both silver paste materials and achieved the required process specifications. Process optimized on DA1 achieved average bond line thickness ranged from 24.5μm to 30.5μm with die tilt less than 0.24% and DA2 had average bond line thickness ranged from 32.6μm to 44.2 μm with die tilt less than 0.15%. There was further evaluation on die attach process with silver sintered paste for different die thickness (which 50μm, 70μm and 175μm were used) on a fixed die size of 5mm×5mm. Porosity after die attach cure is always a curial factor which affects the modulus and conductivity of the device. Investigation on porosity of cured die attached materials was carrying out on different die size range from 0.5mm × 0.5mm to 5mm × 5mm. This helped to understand the effect of die size on sintering process. Optimization of dispensing pattern and die attach process challenges of thin die attachment were discussed in details in this paper.
{"title":"Process characterization of highly conductive silver paste die attach materials for thin die on QFN","authors":"L. Wai, D. Zhi, V. S. Rao, Min Woo Daniel Rhee","doi":"10.1109/EPTC.2012.6507110","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507110","url":null,"abstract":"In this paper, die attach process characterization on two type of highly conductive silver paste die attach materials was discussed. The first silver paste die attach materials (DA1) was used as a reference which is silver-loaded epoxy adhesive with high thermal conductivity of 60W/mK and electrical conductivity of 16Ms/m. Second silver paste die attach material (DA2) can be sintered with low pressure or pressure-less at temperature of 220°C to 280°C. DA2 material acquires high thermal conductivity range of 100–170W/mK and electrical conductivity range of 12–15Ms/m. Process specifications were set at die tilt < 1%, average bond line thickness between 25μm to 50μm and full die attach materials coverage without overflow of materials on top of die's surface. Process was optimized with 70μm thin silicon daisy chain chip with die size of 5mm×5mm on Ag plated QFN lead frame for both silver paste materials and achieved the required process specifications. Process optimized on DA1 achieved average bond line thickness ranged from 24.5μm to 30.5μm with die tilt less than 0.24% and DA2 had average bond line thickness ranged from 32.6μm to 44.2 μm with die tilt less than 0.15%. There was further evaluation on die attach process with silver sintered paste for different die thickness (which 50μm, 70μm and 175μm were used) on a fixed die size of 5mm×5mm. Porosity after die attach cure is always a curial factor which affects the modulus and conductivity of the device. Investigation on porosity of cured die attached materials was carrying out on different die size range from 0.5mm × 0.5mm to 5mm × 5mm. This helped to understand the effect of die size on sintering process. Optimization of dispensing pattern and die attach process challenges of thin die attachment were discussed in details in this paper.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125940050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507126
S. Yoon
Currently various wafer level packaging (WLP) technologies are now cruising at a very high altitude, especially in mobile and portable applications. This is significant trend in packaging business: over 25 billion WLP units are expected to be mounted in smart-phones, tablet PCs or portable devices in 2012. Cost reduction together with miniaturization remains the main driver for adoption of WLP technology. Compared to conventional wire bonding and flipchip packaging, wafer level packaging needs higher capex investment because it has fab-like tools for redistribution process with thin film metals and dielectric polymers. Further cost reduction is a critical factor for penetration into market beyond current market boundaries. And WLP size is increasing with higher IO density and integration of functionality, so board level reliability would be key challenge for moving into broader application areas. In this paper, there will be discussion of technical challenges and market needs of advanced wafer level packaging technology, including fan-in, fan-out (FO), bumping and TSV (Silicon Through Via) etc. And potential solutions and industry approach for those challenges will be presented. Some deeper insights on business opportunities and cost reduction approaches in wafer level packaging in materials and processes will be presented. Lastly new trend of wafer level packaging technology will be discussed including large panel or scalability for high volume production.
目前，各种晶圆级封装(WLP)技术正在非常高的高度巡航，特别是在移动和便携式应用中。这是包装行业的一个重要趋势:2012年，预计将有超过250亿WLP设备被安装在智能手机、平板电脑或便携式设备上。降低成本和小型化仍然是WLP技术采用的主要动力。与传统的线键合和倒装芯片封装相比，晶圆级封装需要更高的资本支出，因为它需要类似于晶圆厂的工具来重新分配薄膜金属和介电聚合物。进一步降低成本是突破当前市场边界进入市场的关键因素。随着IO密度的提高和功能的集成，WLP尺寸也在不断增加，因此板级可靠性将是进入更广泛应用领域的关键挑战。本文将讨论先进晶圆级封装技术的技术挑战和市场需求，包括扇入，扇出(FO)，碰撞和TSV (Silicon Through Via)等。并将介绍应对这些挑战的潜在解决方案和行业方法。我们将介绍晶圆级封装材料和工艺的商业机会和降低成本的方法。最后，将讨论晶圆级封装技术的新趋势，包括大面板或大批量生产的可扩展性。
{"title":"Challenges of advanced wafer level packaging technology: Cost-effectiveness, integration and scalability","authors":"S. Yoon","doi":"10.1109/EPTC.2012.6507126","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507126","url":null,"abstract":"Currently various wafer level packaging (WLP) technologies are now cruising at a very high altitude, especially in mobile and portable applications. This is significant trend in packaging business: over 25 billion WLP units are expected to be mounted in smart-phones, tablet PCs or portable devices in 2012. Cost reduction together with miniaturization remains the main driver for adoption of WLP technology. Compared to conventional wire bonding and flipchip packaging, wafer level packaging needs higher capex investment because it has fab-like tools for redistribution process with thin film metals and dielectric polymers. Further cost reduction is a critical factor for penetration into market beyond current market boundaries. And WLP size is increasing with higher IO density and integration of functionality, so board level reliability would be key challenge for moving into broader application areas. In this paper, there will be discussion of technical challenges and market needs of advanced wafer level packaging technology, including fan-in, fan-out (FO), bumping and TSV (Silicon Through Via) etc. And potential solutions and industry approach for those challenges will be presented. Some deeper insights on business opportunities and cost reduction approaches in wafer level packaging in materials and processes will be presented. Lastly new trend of wafer level packaging technology will be discussed including large panel or scalability for high volume production.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128221352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507061
A. Singulani, H. Ceric, S. Selberherr
A specific open Through Silicon Via (TSV) technology is analyzed by means of thermo-mechanical Finite Element Method (FEM) simulations in order to assess stress behavior and to identify critical stress points in the structure. An analytical expression is introduced for the stress field around one TSV and its application in the description of the stress in a particular arrangement of vias is discussed. The analysis provides a consistent justification for the robustness of the technology, while it also points out the potential failure points.
{"title":"Thermo-mechanical simulations of an open tungsten TSV","authors":"A. Singulani, H. Ceric, S. Selberherr","doi":"10.1109/EPTC.2012.6507061","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507061","url":null,"abstract":"A specific open Through Silicon Via (TSV) technology is analyzed by means of thermo-mechanical Finite Element Method (FEM) simulations in order to assess stress behavior and to identify critical stress points in the structure. An analytical expression is introduced for the stress field around one TSV and its application in the description of the stress in a particular arrangement of vias is discussed. The analysis provides a consistent justification for the robustness of the technology, while it also points out the potential failure points.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127216366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507113
H. Ng, Wui-Weng Wong
This paper describes an effective characterization method developed for frequency-dependent electrical characteristics of multiple-terminal chip capacitors used widely in power delivery networks in today's high-speed digital applications. This technique achieves excellent accuracy across a wide frequency range in the chip capacitor application on a digital ASIC substrate compared to conventional ESR and ESL extraction methods. To ensure the developed circuit models cover the wide frequency range, multiple branches of RLC elements are proposed to capture the higher-order frequency response of the chip capacitor impedance. The characterization procedure consists of carefully designed test fixtures, two-port VNA measurements, a de-embedding process, and circuit modeling and simulation. Simulation results demonstrated using this method is further correlated with a frequency limited de-embedded s-parameters from measurements.
{"title":"A wide frequency band characterization technique for multiple-terminal discrete decoupling capacitors","authors":"H. Ng, Wui-Weng Wong","doi":"10.1109/EPTC.2012.6507113","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507113","url":null,"abstract":"This paper describes an effective characterization method developed for frequency-dependent electrical characteristics of multiple-terminal chip capacitors used widely in power delivery networks in today's high-speed digital applications. This technique achieves excellent accuracy across a wide frequency range in the chip capacitor application on a digital ASIC substrate compared to conventional ESR and ESL extraction methods. To ensure the developed circuit models cover the wide frequency range, multiple branches of RLC elements are proposed to capture the higher-order frequency response of the chip capacitor impedance. The characterization procedure consists of carefully designed test fixtures, two-port VNA measurements, a de-embedding process, and circuit modeling and simulation. Simulation results demonstrated using this method is further correlated with a frequency limited de-embedded s-parameters from measurements.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132130920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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