Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507056
Rui Li, Cheng Jin, K. Sampath, Min Tang, S. W. Ho, Siong Chiew Ong
This paper presents the design and implementation of a second-order 135GHz bandpass filter (BPF) constructed on a thin suspended membrane structure. The BPF is built by cascading two U-shape slotline resonators formed on the ground plane. The input and output coupling are achieved by the microstrip line to slotline transition on the other side of the substrate. The unloaded quality (Q) factors of both I-shape and U-shape resonator due to the radiation, material and conductor loss are studied. The BPF is fabricated and measured, and it demonstrates a good agreement between the simulation and measurement results.
{"title":"A 135GHz slotline bandpass filter using silicon/membrane technology","authors":"Rui Li, Cheng Jin, K. Sampath, Min Tang, S. W. Ho, Siong Chiew Ong","doi":"10.1109/EPTC.2012.6507056","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507056","url":null,"abstract":"This paper presents the design and implementation of a second-order 135GHz bandpass filter (BPF) constructed on a thin suspended membrane structure. The BPF is built by cascading two U-shape slotline resonators formed on the ground plane. The input and output coupling are achieved by the microstrip line to slotline transition on the other side of the substrate. The unloaded quality (Q) factors of both I-shape and U-shape resonator due to the radiation, material and conductor loss are studied. The BPF is fabricated and measured, and it demonstrates a good agreement between the simulation and measurement results.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"292 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122303844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507062
Y. S. Chan, Hong Yu Li, Xiaowu Zhang
TSV interposer is expected to be the driving vehicle for 2.5-D IC integration. Although a number of studies have been reported on the thermo-mechanical reliability of TSVs, it remains difficult for one to justify whether a TSV design or an interposer design is manufacturable or not because we are still lack of experimental reliability data. This investigation has provided this important experimental data, and also a series of correlation studies by finite element simulations. A 2-D analytical solution was also examined to help understanding the physics of the problem. Regarding the experimental results, wafer cracking was observed for TSV arrays with large diameters and small pitch-to-diameter ratios after annealing at 300 °C. The critical strength to wafer cracking was determined to be 388 MPa from some finite element analyses. Through analytical considerations, the influence of TSV diameter on wafer cracking was found to rely on the contributions from the dielectric layer thickness and also the barrier layer thickness. An empirical model for the design of copper-filled TSV interposers was ultimately generated based on the modification of the 2-D solution.
{"title":"The effect of TSV design parameters on the manufacturability of TSV interposers","authors":"Y. S. Chan, Hong Yu Li, Xiaowu Zhang","doi":"10.1109/EPTC.2012.6507062","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507062","url":null,"abstract":"TSV interposer is expected to be the driving vehicle for 2.5-D IC integration. Although a number of studies have been reported on the thermo-mechanical reliability of TSVs, it remains difficult for one to justify whether a TSV design or an interposer design is manufacturable or not because we are still lack of experimental reliability data. This investigation has provided this important experimental data, and also a series of correlation studies by finite element simulations. A 2-D analytical solution was also examined to help understanding the physics of the problem. Regarding the experimental results, wafer cracking was observed for TSV arrays with large diameters and small pitch-to-diameter ratios after annealing at 300 °C. The critical strength to wafer cracking was determined to be 388 MPa from some finite element analyses. Through analytical considerations, the influence of TSV diameter on wafer cracking was found to rely on the contributions from the dielectric layer thickness and also the barrier layer thickness. An empirical model for the design of copper-filled TSV interposers was ultimately generated based on the modification of the 2-D solution.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116495685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507091
Megan Chang, F. Yu
This paper presents TI development of low cost fillers die attach materials for powerpad and non powerpad packages with PPF LDF. While silver fillers drive conductive die attach applications in semiconductor history, eagerness for a promising alternative filler die attach has been arising to get rid of silver filler die attach price impacted by silver price on the market. Besides the short term cost benefit, how to maintain the long term cost advantage across the rivals is another priority for development. Silver plated copper (SPC) filler die attach materials have attracted a lot of attentions due to the relative higher thermal conductivity and lower cost of metal copper comparing with other metals. Although there has been available silver plated copper die attach materials in semiconductor industry, however the low thermal conductivity constrains the application in powerpad packages especially for the weak adhesion performance of PPF Au/Pd/Ni LDF. In addition to silver plated copper fillers, many opportunities are being engaged and evaluated for promising long term cost advantages die attach materials for electronic packaging. Among of them, copper filler is the most interesting target for the super low cost die attach materials. Quality and reliability of low cost metals die attach materials have been validating via extensive evaluation plan on powerpad and non powerpad packages in recent and confirmed as noteworthy solutions for further development.
{"title":"Low cost fillers die attach materials development for powerpad and non powerpad packages with PPF LDF","authors":"Megan Chang, F. Yu","doi":"10.1109/EPTC.2012.6507091","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507091","url":null,"abstract":"This paper presents TI development of low cost fillers die attach materials for powerpad and non powerpad packages with PPF LDF. While silver fillers drive conductive die attach applications in semiconductor history, eagerness for a promising alternative filler die attach has been arising to get rid of silver filler die attach price impacted by silver price on the market. Besides the short term cost benefit, how to maintain the long term cost advantage across the rivals is another priority for development. Silver plated copper (SPC) filler die attach materials have attracted a lot of attentions due to the relative higher thermal conductivity and lower cost of metal copper comparing with other metals. Although there has been available silver plated copper die attach materials in semiconductor industry, however the low thermal conductivity constrains the application in powerpad packages especially for the weak adhesion performance of PPF Au/Pd/Ni LDF. In addition to silver plated copper fillers, many opportunities are being engaged and evaluated for promising long term cost advantages die attach materials for electronic packaging. Among of them, copper filler is the most interesting target for the super low cost die attach materials. Quality and reliability of low cost metals die attach materials have been validating via extensive evaluation plan on powerpad and non powerpad packages in recent and confirmed as noteworthy solutions for further development.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128864345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507140
Z. Syahirah, R. Gopmath, M. Tay
As package integration has reached a saturation point in device miniaturization, fault isolation of flip-chip packaging defects using real-time X-ray, even when using high-magnification viewing, is facing more challenges due to the increase in package complexity and shrinking package dimensions. Computed tomography (CT) X-ray is a solution to overcome this problem. This paper compares defect detection between 2D and 3D X-ray images using the CT X-ray platform. We present specific case study discussions of various defects that were challenging for 2D X-ray but effectively isolated by 3D X-ray.
{"title":"Advanced non-destructive fault isolation using computed tomography in flip-chip devices","authors":"Z. Syahirah, R. Gopmath, M. Tay","doi":"10.1109/EPTC.2012.6507140","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507140","url":null,"abstract":"As package integration has reached a saturation point in device miniaturization, fault isolation of flip-chip packaging defects using real-time X-ray, even when using high-magnification viewing, is facing more challenges due to the increase in package complexity and shrinking package dimensions. Computed tomography (CT) X-ray is a solution to overcome this problem. This paper compares defect detection between 2D and 3D X-ray images using the CT X-ray platform. We present specific case study discussions of various defects that were challenging for 2D X-ray but effectively isolated by 3D X-ray.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129532408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507080
Ravi Subramaniyan Sathanantham, F. Foo, Z. Oh
Advancement in deep-sub-micron technology has given the microelectronic industry the opportunity to squeeze more transistors on a smaller die. As a result, thermal management solutions for these high-density circuits that dissipate a large amount of heat become ever-more essential. Compounding the thermal management challenge is the high demand for razor-thin products that are driving lidless packaging solutions. These lidless packages expose the die back-side to harsh environments, making it prone to scratches and chippage during assembly, testing, transportation, and handling. Hence, there is an urgent need to evaluate the strength of silicon die in lidless flip-chip packages and understand the effect of die back-side flaws at a fundamental level to ensure that the mechanical reliability of the flip-chip die is uncompromised. This work investigates the influence of microscopic flaws on the fracture strength of silicon die. This paper uses standard techniques to evaluate the strength of flip-chip die as a function of flaw size using a standard flexure test to determine fracture strength and the minimum flaw size required for fracture to occur in a silicon die. Efforts have been made to understand the origin and propagation of cracking in silicon by implementing fracture analysis techniques that can be adopted as one important step in physical failure analysis of die cracks.
{"title":"Fundamental study of fracture strength of silicon dies in flip-chip lidless packages","authors":"Ravi Subramaniyan Sathanantham, F. Foo, Z. Oh","doi":"10.1109/EPTC.2012.6507080","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507080","url":null,"abstract":"Advancement in deep-sub-micron technology has given the microelectronic industry the opportunity to squeeze more transistors on a smaller die. As a result, thermal management solutions for these high-density circuits that dissipate a large amount of heat become ever-more essential. Compounding the thermal management challenge is the high demand for razor-thin products that are driving lidless packaging solutions. These lidless packages expose the die back-side to harsh environments, making it prone to scratches and chippage during assembly, testing, transportation, and handling. Hence, there is an urgent need to evaluate the strength of silicon die in lidless flip-chip packages and understand the effect of die back-side flaws at a fundamental level to ensure that the mechanical reliability of the flip-chip die is uncompromised. This work investigates the influence of microscopic flaws on the fracture strength of silicon die. This paper uses standard techniques to evaluate the strength of flip-chip die as a function of flaw size using a standard flexure test to determine fracture strength and the minimum flaw size required for fracture to occur in a silicon die. Efforts have been made to understand the origin and propagation of cracking in silicon by implementing fracture analysis techniques that can be adopted as one important step in physical failure analysis of die cracks.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114629532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507153
Masaru Monta, K. Okiyama, T. Sakai, N. Imaizumi
In this paper, we report a reflow process that uses formic acid to rem ove the native oxide of a so lder on a Cu pillar instead of using flux. To study the effect of the solder on the Cu pillar, we compare the shape and the crystal structure of a wetted solder on a Cup illar afterareflo w process using formic acid and flux. To conduct the experiment, we also had to confirm the effect of the in termetallic compound layer between a solder and a Cu pillar. Therefore, we prepared the sample with a Ni layer between a so lder and a C u pillar to prevent the formation of an intermetallic compound layer. Both samples with/without Ni layer were investigated simultaneously. The results showed that the solder which was fabricated by a reflow process using formic acid crystalized even at a peak temperature of 228 °C, which is ciò se to the solder melting temperature. There was no difference in the reduction abilities between formic acid an d flux in the wettability test o f the solder. However, it was found that the amount of formic acid are proportional to the reflow temperature. Atmosphere of formic acid is main factor of raising peak temperature of reflow.
{"title":"Formation of solder cap on Cu pillar bump using formic acid reduction","authors":"Masaru Monta, K. Okiyama, T. Sakai, N. Imaizumi","doi":"10.1109/EPTC.2012.6507153","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507153","url":null,"abstract":"In this paper, we report a reflow process that uses formic acid to rem ove the native oxide of a so lder on a Cu pillar instead of using flux. To study the effect of the solder on the Cu pillar, we compare the shape and the crystal structure of a wetted solder on a Cup illar afterareflo w process using formic acid and flux. To conduct the experiment, we also had to confirm the effect of the in termetallic compound layer between a solder and a Cu pillar. Therefore, we prepared the sample with a Ni layer between a so lder and a C u pillar to prevent the formation of an intermetallic compound layer. Both samples with/without Ni layer were investigated simultaneously. The results showed that the solder which was fabricated by a reflow process using formic acid crystalized even at a peak temperature of 228 °C, which is ciò se to the solder melting temperature. There was no difference in the reduction abilities between formic acid an d flux in the wettability test o f the solder. However, it was found that the amount of formic acid are proportional to the reflow temperature. Atmosphere of formic acid is main factor of raising peak temperature of reflow.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130299600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507133
Jie Wu, T. Rockey, O. Yauw, Liming Shen, B. Chylak
Lower cost materials, such as copper (Cu) and palladium coated copper (PdCu) are the commonly chosen alternatives of gold (Au) wire in the package industry. However, the high hardness of Cu and PdCu wires brings concerns over the bonding quality and the long-term reliability of the packages. Silver (Ag) has drawn more attention in the package industry since it has similar properties like hardness, elongation and breaking load as Au, while having a comparable price to PdCu. Bondability of Ag-alloy wire, including performance of free air balls (FAB) and bonding capability on aluminum (Al) die pads, was first investigated. Inspection of intermetallic compound (IMC) and unmolded baking of the bonded packages with the Ag-alloy wire were also carried out for further understanding the reliability performance of the wire. Investigations of bonding capability comparison between pure Ag, Ag-alloy, and PdCu wires in processes with stand-off-stitch-bond (SSB) and peel sensitive dies were included in the study as well. Generally, Ag-alloy wire delivers good and stable bonding capability using N2 as the cover gas. For applications with SSB and peel/lift sensitive bond pads which are normally difficult using PdCu wire, Ag-alloy wire also possesses good performance.
{"title":"Study of Ag-alloy wire in thermosonic wire bonding","authors":"Jie Wu, T. Rockey, O. Yauw, Liming Shen, B. Chylak","doi":"10.1109/EPTC.2012.6507133","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507133","url":null,"abstract":"Lower cost materials, such as copper (Cu) and palladium coated copper (PdCu) are the commonly chosen alternatives of gold (Au) wire in the package industry. However, the high hardness of Cu and PdCu wires brings concerns over the bonding quality and the long-term reliability of the packages. Silver (Ag) has drawn more attention in the package industry since it has similar properties like hardness, elongation and breaking load as Au, while having a comparable price to PdCu. Bondability of Ag-alloy wire, including performance of free air balls (FAB) and bonding capability on aluminum (Al) die pads, was first investigated. Inspection of intermetallic compound (IMC) and unmolded baking of the bonded packages with the Ag-alloy wire were also carried out for further understanding the reliability performance of the wire. Investigations of bonding capability comparison between pure Ag, Ag-alloy, and PdCu wires in processes with stand-off-stitch-bond (SSB) and peel sensitive dies were included in the study as well. Generally, Ag-alloy wire delivers good and stable bonding capability using N2 as the cover gas. For applications with SSB and peel/lift sensitive bond pads which are normally difficult using PdCu wire, Ag-alloy wire also possesses good performance.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130658434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507096
J. Hunt, Kidd Lee, P. Shih, J. Lin
As die sizes shrink with technology node advances, the area of WLCSP dice is becoming too small to accommodate all of the solder balls required for the dice I/O. One solution to this problem has been Fan Out Wafer Level Packages (FOWLP), which have been in volume production for over three years. However, these are Wafer processes, performed with either 200mm or 300mm reconstituted molded wafers, and are often not cost competitive with other traditional packages. A lower cost solution is needed to use for fanning out the I/O of small die that approximates the structure of the FOWLP. We have developed a panel process that uses a similar simple single Redistribution Layer (RDL) for the fan out function that complements the FOWLP solution.
{"title":"A hybrid panel embedding process for fanout","authors":"J. Hunt, Kidd Lee, P. Shih, J. Lin","doi":"10.1109/EPTC.2012.6507096","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507096","url":null,"abstract":"As die sizes shrink with technology node advances, the area of WLCSP dice is becoming too small to accommodate all of the solder balls required for the dice I/O. One solution to this problem has been Fan Out Wafer Level Packages (FOWLP), which have been in volume production for over three years. However, these are Wafer processes, performed with either 200mm or 300mm reconstituted molded wafers, and are often not cost competitive with other traditional packages. A lower cost solution is needed to use for fanning out the I/O of small die that approximates the structure of the FOWLP. We have developed a panel process that uses a similar simple single Redistribution Layer (RDL) for the fan out function that complements the FOWLP solution.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"253 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134347176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6522604
Hongbin Shi, Cuihua Tian, M. Pecht, T. Ueda
Full capillary flow underfill (FCFU) has been proven to be effective in improving the board-level mechanical reliability of lead-free (LF) area array packages (AAPs). However, the FCFU may have negative effects on the thermal cycling reliability of AAPs depending on the material properties of underfills, including coefficients of thermal expansion, glass transition temperature, modulus, and adhesion strength. In addition, the increased cost, time-consuming processes, and poor reworkability caused by the application of FCFU have also hindered the widespread use of the board-level underfills. In order to address these challenges, a partial capillary flow underfill (PCFU) or corner-only underfill approach was developed. However, data are scarce for board-level solder joint reliability of LF AAPs with PCFU, especially for portable electronics applications. In this paper, the overall reliability of LF chip scale packages (CSPs) with FCFU and PCFU was comparatively studied using the AAP-to-board interconnection shear test, monotonic 3-point bending test, vertical free drop test, and thermal cycling test. One set of non-underfilled CSP assemblies was tested as the control. The test results indicated that the mechanical performance of underfilled CSPs was significantly enhanced compared to the CSPs without underfill, especially for drop reliability. However, the characteristic life values of CSPs with FCFU and PCFU during the thermal cycling test were reduced by 15% and 8%, respectively. The improvement in overall boardlevel solder joint reliability of LF CSPs provided by the PCFU was comparable to that of the FCFU. Hence, partial underfill can be used as a good alternative to full underfill. Failure analysis demonstrated that the dominant failure mode was PCB pad cratering in shear and bending test, and the brittle fracture at the CSP intermetallic compound/solder interface was dominant for all the test groups under drop loading conditions. In contrast, the failure mechanisms of the underfilled and control boards were different during the thermal cycling test: PCB pad cratering and bulk solder fatigue crack were found in the CSPs with and without underfill, respectively.
{"title":"Board-level shear, bend, drop and thermal cycling reliability of lead-free chip scale packages with partial underfill: a low-cost alternative to full underfill","authors":"Hongbin Shi, Cuihua Tian, M. Pecht, T. Ueda","doi":"10.1109/EPTC.2012.6522604","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6522604","url":null,"abstract":"Full capillary flow underfill (FCFU) has been proven to be effective in improving the board-level mechanical reliability of lead-free (LF) area array packages (AAPs). However, the FCFU may have negative effects on the thermal cycling reliability of AAPs depending on the material properties of underfills, including coefficients of thermal expansion, glass transition temperature, modulus, and adhesion strength. In addition, the increased cost, time-consuming processes, and poor reworkability caused by the application of FCFU have also hindered the widespread use of the board-level underfills. In order to address these challenges, a partial capillary flow underfill (PCFU) or corner-only underfill approach was developed. However, data are scarce for board-level solder joint reliability of LF AAPs with PCFU, especially for portable electronics applications. In this paper, the overall reliability of LF chip scale packages (CSPs) with FCFU and PCFU was comparatively studied using the AAP-to-board interconnection shear test, monotonic 3-point bending test, vertical free drop test, and thermal cycling test. One set of non-underfilled CSP assemblies was tested as the control. The test results indicated that the mechanical performance of underfilled CSPs was significantly enhanced compared to the CSPs without underfill, especially for drop reliability. However, the characteristic life values of CSPs with FCFU and PCFU during the thermal cycling test were reduced by 15% and 8%, respectively. The improvement in overall boardlevel solder joint reliability of LF CSPs provided by the PCFU was comparable to that of the FCFU. Hence, partial underfill can be used as a good alternative to full underfill. Failure analysis demonstrated that the dominant failure mode was PCB pad cratering in shear and bending test, and the brittle fracture at the CSP intermetallic compound/solder interface was dominant for all the test groups under drop loading conditions. In contrast, the failure mechanisms of the underfilled and control boards were different during the thermal cycling test: PCB pad cratering and bulk solder fatigue crack were found in the CSPs with and without underfill, respectively.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"407 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132206897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507065
Emad A. Poshtan, S. Rzepka, B. Wunderle, C. Silber, T. von Bargen, B. Michel
In this paper we examine the influence of different characteristics of TQFP (thin quad flat package) components on package behavior by simulation and experiment. The varied parameters are the package dimensions, rate-dependent material properties such as viscoelasticity and cure shrinkage and external boundary conditions.
{"title":"The effects of rate-dependent material properties and geometrical characteristics on thermo-mechanical behavior of TQFP package","authors":"Emad A. Poshtan, S. Rzepka, B. Wunderle, C. Silber, T. von Bargen, B. Michel","doi":"10.1109/EPTC.2012.6507065","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507065","url":null,"abstract":"In this paper we examine the influence of different characteristics of TQFP (thin quad flat package) components on package behavior by simulation and experiment. The varied parameters are the package dimensions, rate-dependent material properties such as viscoelasticity and cure shrinkage and external boundary conditions.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130244831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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