Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507111
L. Ji, L. Wai, Min Woo Daniel Rhee
This paper presents a new numerical model to characterize the die attach process in the advance packaging. With its successful application on a 5 mm by 5 mm with 70um thickness die attached to the substrate, final fillet shape of the die attach material is predicted for various process conditions. Focuses have been given on the die attach material over flow on the die top surface. The contamination on the die top surface may cause failures in the subsequent processes. The simulation results were compared with the experiment. Good match was obtained. Moreover, process window for a given amount die attach material was established through the simulation and the corresponding bonding force that will not cause die attach material over flow was predicted. Key advantage of this numerical study is to give the insights into process parameters and provide initial process window to prevent die attach over flow.
{"title":"Flow modeling of die attach process and the optimization of process parameters in advance packaging","authors":"L. Ji, L. Wai, Min Woo Daniel Rhee","doi":"10.1109/EPTC.2012.6507111","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507111","url":null,"abstract":"This paper presents a new numerical model to characterize the die attach process in the advance packaging. With its successful application on a 5 mm by 5 mm with 70um thickness die attached to the substrate, final fillet shape of the die attach material is predicted for various process conditions. Focuses have been given on the die attach material over flow on the die top surface. The contamination on the die top surface may cause failures in the subsequent processes. The simulation results were compared with the experiment. Good match was obtained. Moreover, process window for a given amount die attach material was established through the simulation and the corresponding bonding force that will not cause die attach material over flow was predicted. Key advantage of this numerical study is to give the insights into process parameters and provide initial process window to prevent die attach over flow.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128593376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507073
L. Frisk, S. Lahokallio, M. Mostofizadeh, J. Kiilunen, K. Saarinen
Electrically conductive adhesives (ECA) are considered to be one of the future technologies due to their potential for low cost, high reliability, and simple processing. Additionally, an important advantage with ECA materials is the possibility for low bonding temperature. Therefore, they are especially well suited for low cost applications. ECA materials are prepared by mixing polymer matrix with electrically conductive particles. In isotropic conductive adhesives (ICA) concentration of the conductive particles is high and they conduct in all directions. Several materials can be used to manufacture ICAs. The most widely used ICAs in the electronics industry are silver-filled epoxies, which also provide a high level of thermal conductivity. However, other polymers can also be used. All polymer materials used in ICAs absorb moisture, which affects their mechanical behavior. Additionally, the electrical properties of the ICA may change. Therefore it is important to study how different ICA materials behave under humid conditions. Especially, if the humidity levels are high, these changes may occur very rapidly. In this work 14 different commercial ICA materials were studied under condensing humidity conditions. To study the behavior of the ICAs they were used to attach zero ohm resistors onto FR-4 test boards. To study the effect of glob top on the behavior of the ICAs, two additional test series were assembled with two epoxy ICAs using a glop top material to protect the components and the interconnections. Marked changes were seen in the resistance values of the test samples during the test. Additionally, considerable variation was seen between the ICAs. Some ICAs showed increased resistance values very quickly after the testing was started. The two ICAs not shown did not show failures during testing.
{"title":"Reliability of isotropic electrically conductive adhesives under condensing humidity testing","authors":"L. Frisk, S. Lahokallio, M. Mostofizadeh, J. Kiilunen, K. Saarinen","doi":"10.1109/EPTC.2012.6507073","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507073","url":null,"abstract":"Electrically conductive adhesives (ECA) are considered to be one of the future technologies due to their potential for low cost, high reliability, and simple processing. Additionally, an important advantage with ECA materials is the possibility for low bonding temperature. Therefore, they are especially well suited for low cost applications. ECA materials are prepared by mixing polymer matrix with electrically conductive particles. In isotropic conductive adhesives (ICA) concentration of the conductive particles is high and they conduct in all directions. Several materials can be used to manufacture ICAs. The most widely used ICAs in the electronics industry are silver-filled epoxies, which also provide a high level of thermal conductivity. However, other polymers can also be used. All polymer materials used in ICAs absorb moisture, which affects their mechanical behavior. Additionally, the electrical properties of the ICA may change. Therefore it is important to study how different ICA materials behave under humid conditions. Especially, if the humidity levels are high, these changes may occur very rapidly. In this work 14 different commercial ICA materials were studied under condensing humidity conditions. To study the behavior of the ICAs they were used to attach zero ohm resistors onto FR-4 test boards. To study the effect of glob top on the behavior of the ICAs, two additional test series were assembled with two epoxy ICAs using a glop top material to protect the components and the interconnections. Marked changes were seen in the resistance values of the test samples during the test. Additionally, considerable variation was seen between the ICAs. Some ICAs showed increased resistance values very quickly after the testing was started. The two ICAs not shown did not show failures during testing.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128750557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507162
Amarjit Dhadda, Robert M. Montgomery, P. Jones, Jason Heirene, Rachel Kuthakis, F. Bieck
Providing thinner and thinner Silicon is one of the key challenges in today's semiconductor manufacturing. The thinner the wafer and thus the die, the thinner the package can be designed. Getting thinner devices is also a necessary precondition for Trough Silicon Via (TSV) technology, in which a thin wafer is needed in order to create through-contacts in the die. While for standard wafer applications the driver for thinner Silicon wafers may be considered as “geometrical”, this is not the case for power chip application. Here, the main driver for using thinner Silicon in powerchip applications is directly linked to device performance. As the Rds(on) is primarily a function of the device thickness and thus the wafer thickness, producing thinner Silicon provides not only geometrical advantages in the packaging process, but especially better performing devices. In order to fullill the demand for thinner and thus improved devices, International Rectifier (IR) has recently installed a 200 mm line for ultrathin wafers. In this paper, we will describe and discuss the thinning process that is implemented at IR.
{"title":"Processing of ultrathin wafers for power chip applications","authors":"Amarjit Dhadda, Robert M. Montgomery, P. Jones, Jason Heirene, Rachel Kuthakis, F. Bieck","doi":"10.1109/EPTC.2012.6507162","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507162","url":null,"abstract":"Providing thinner and thinner Silicon is one of the key challenges in today's semiconductor manufacturing. The thinner the wafer and thus the die, the thinner the package can be designed. Getting thinner devices is also a necessary precondition for Trough Silicon Via (TSV) technology, in which a thin wafer is needed in order to create through-contacts in the die. While for standard wafer applications the driver for thinner Silicon wafers may be considered as “geometrical”, this is not the case for power chip application. Here, the main driver for using thinner Silicon in powerchip applications is directly linked to device performance. As the Rds(on) is primarily a function of the device thickness and thus the wafer thickness, producing thinner Silicon provides not only geometrical advantages in the packaging process, but especially better performing devices. In order to fullill the demand for thinner and thus improved devices, International Rectifier (IR) has recently installed a 200 mm line for ultrathin wafers. In this paper, we will describe and discuss the thinning process that is implemented at IR.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127639617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507083
V. N. Sekhar, J. Toh, Jin Cheng, J. Sharma, S. Fernando, Chen Bangtao
This paper presents the design, fabrication and characterization of MEMS wafer level packaging (WLP) with TSV based silicon interposer as cap wafer. High resistivity Si wafers have been used for TSV interposer fabrication mainly to minimize the intrinsic loss of RF MEMS device due to packaging. During development of this RF MEMS WLP, many key challenging processes have been developed such as, high aspect ratio TSV fabrication, double side RDL fabrication, thin wafer handling of TSV interposer and optimization of Au-Sn based TLP bonding. There are several fabrication steps involved in the actual process flow as, a) TSV fabrication and front side RDL patterning and passivation, b) Wafer thinning and backside RDL patterning and passivation c) UBM/ seal ring solder deposition and cavity formation, and d) TLP based wafer bonding of cap TSV interposer wafer with MEMS CPW wafer. Different CPW designs with three passivation schemes have been fabricated mainly to study the effect of passivation on insertion loss and ultimately quantify the packaging insertion loss. In pre-bonding testing, effect of passivation on insertion loss is thoroughly studied. After successful fabrication of the WLP, loss of RF device characteristics due to packaging has been studied. Before and after packaging, S-parameter measurements performed on coplanar waveguides (CPW). Amongst different passivation schemes, CPW structures with poly-silicon passivation have shown better performance.
{"title":"Wafer level packaging of RF MEMS devices using TSV interposer technology","authors":"V. N. Sekhar, J. Toh, Jin Cheng, J. Sharma, S. Fernando, Chen Bangtao","doi":"10.1109/EPTC.2012.6507083","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507083","url":null,"abstract":"This paper presents the design, fabrication and characterization of MEMS wafer level packaging (WLP) with TSV based silicon interposer as cap wafer. High resistivity Si wafers have been used for TSV interposer fabrication mainly to minimize the intrinsic loss of RF MEMS device due to packaging. During development of this RF MEMS WLP, many key challenging processes have been developed such as, high aspect ratio TSV fabrication, double side RDL fabrication, thin wafer handling of TSV interposer and optimization of Au-Sn based TLP bonding. There are several fabrication steps involved in the actual process flow as, a) TSV fabrication and front side RDL patterning and passivation, b) Wafer thinning and backside RDL patterning and passivation c) UBM/ seal ring solder deposition and cavity formation, and d) TLP based wafer bonding of cap TSV interposer wafer with MEMS CPW wafer. Different CPW designs with three passivation schemes have been fabricated mainly to study the effect of passivation on insertion loss and ultimately quantify the packaging insertion loss. In pre-bonding testing, effect of passivation on insertion loss is thoroughly studied. After successful fabrication of the WLP, loss of RF device characteristics due to packaging has been studied. Before and after packaging, S-parameter measurements performed on coplanar waveguides (CPW). Amongst different passivation schemes, CPW structures with poly-silicon passivation have shown better performance.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129534625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507039
Tama Fouzder, Y. Chan, Daniel K. Chan
Different surface finished lead-free electroplated Cu substrates were prepared using an electrolytic process jointly developed for special applications. The surface morphology and plated layer thicknesses were investigated using atomic force microscope (AFM) and seanning electron microscope (SEM). From SEM micrographs, it was confirmed that the plated layers i.e., Au/Ni and Ag/Ni were well deposited on Cu substrates uniformly. In addition, the plated layer thicknesses were increased with an increasing processing temperature. The average Au/Ni p lated layers thicknesses atplated temperatures of30°C, 40°C and 5 0°C were about 0.67μm, 0.71μm and 0.77 μm, respectively. On the other hand, the average Ag/Ni plated layers thicknesses at plated temperatures of 10°C, 20°C and 30°C were about 6.5μm, 7.7μm and 8.4μm, respectively. From AFM observations, it was confirmed that the plated layer appeared to have a very smooth surface without any defects such as cra cks, delamination etc., confirming the successful application of the specially developed electrolytic process.
{"title":"Microstructure and plating thickness analysis of different surface finished plated printed circuit boards","authors":"Tama Fouzder, Y. Chan, Daniel K. Chan","doi":"10.1109/EPTC.2012.6507039","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507039","url":null,"abstract":"Different surface finished lead-free electroplated Cu substrates were prepared using an electrolytic process jointly developed for special applications. The surface morphology and plated layer thicknesses were investigated using atomic force microscope (AFM) and seanning electron microscope (SEM). From SEM micrographs, it was confirmed that the plated layers i.e., Au/Ni and Ag/Ni were well deposited on Cu substrates uniformly. In addition, the plated layer thicknesses were increased with an increasing processing temperature. The average Au/Ni p lated layers thicknesses atplated temperatures of30°C, 40°C and 5 0°C were about 0.67μm, 0.71μm and 0.77 μm, respectively. On the other hand, the average Ag/Ni plated layers thicknesses at plated temperatures of 10°C, 20°C and 30°C were about 6.5μm, 7.7μm and 8.4μm, respectively. From AFM observations, it was confirmed that the plated layer appeared to have a very smooth surface without any defects such as cra cks, delamination etc., confirming the successful application of the specially developed electrolytic process.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129216839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507124
M. Briindel, U. Scholz, F. Haag, E. Graf, T. Braun, K. Becker
In this paper, we present the application of a substrateless packaging technology consisting of sub sequential molding of ASIC and MEMS dice und forming redistribution layers (RDL) on the molding compound. Acceleration sensors and pressure sensors were packaged, each sensor type presenting its own challenges. For pressure sensors it is crucial to ensure the access of the surrounding media to the pressure sensitive membrane. This was achieved by structuring the redistribution layer without changing the process, making the application of standard equipment and materials relatively easy. The acceleration sensors needed to be modified by trough silicon vias to fit the packaging process. For the redistribution layer, a novel approach was evaluated in parallel to the standard thin-film technology for the acceleration sensor package. All sensor packages fabricated by the process have been found to be within the specifications of standard packages using the same MEMS dice.
{"title":"Substrateless sensor packaging using wafer level fan-out technology","authors":"M. Briindel, U. Scholz, F. Haag, E. Graf, T. Braun, K. Becker","doi":"10.1109/EPTC.2012.6507124","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507124","url":null,"abstract":"In this paper, we present the application of a substrateless packaging technology consisting of sub sequential molding of ASIC and MEMS dice und forming redistribution layers (RDL) on the molding compound. Acceleration sensors and pressure sensors were packaged, each sensor type presenting its own challenges. For pressure sensors it is crucial to ensure the access of the surrounding media to the pressure sensitive membrane. This was achieved by structuring the redistribution layer without changing the process, making the application of standard equipment and materials relatively easy. The acceleration sensors needed to be modified by trough silicon vias to fit the packaging process. For the redistribution layer, a novel approach was evaluated in parallel to the standard thin-film technology for the acceleration sensor package. All sensor packages fabricated by the process have been found to be within the specifications of standard packages using the same MEMS dice.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128755790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507104
B. Soon, Navab Singh, J. Tsai, Chengkuo Lee
In this paper, we demonstrate wafer level encapsulation of MEMS using physical vapor deposition of aluminum (Al). A cavity area, which simulates the area of a MEMS device, is fully encapsulated by dual layer of amorphous silicon and Al. The encapsulation process takes place in the PVD chamber, thus the vacuum level in the sealed cavity is assumed to be high. The proposed processes are entirely CMOS compatible and readily deployed into any standard CMOS foundry and semiconductor wafer fabrication.
{"title":"Vacuum based wafer level encapsulation (WLE) of MEMS using physical vapor deposition (PVD)","authors":"B. Soon, Navab Singh, J. Tsai, Chengkuo Lee","doi":"10.1109/EPTC.2012.6507104","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507104","url":null,"abstract":"In this paper, we demonstrate wafer level encapsulation of MEMS using physical vapor deposition of aluminum (Al). A cavity area, which simulates the area of a MEMS device, is fully encapsulated by dual layer of amorphous silicon and Al. The encapsulation process takes place in the PVD chamber, thus the vacuum level in the sealed cavity is assumed to be high. The proposed processes are entirely CMOS compatible and readily deployed into any standard CMOS foundry and semiconductor wafer fabrication.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116901307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507187
S. Sushanth Kumar, Satishchandra C Warn, Roland Lee
In automobiles, an ECM (Electronic Control Module) is used for controlling internal ambient temperature of vehicles to enhance comfort level of passengers. It typically contains a display module to show various operational modes such as cooling air temperature, ON/OFF for blower, AC, de-fogger etc. The display module uses LEDs as source of illumination. Adequate illumination requires packaging of several LEDs m a compact/constrained space. Also LEDs must operate at very high ambient temperature of 85°C that leads to significant thermal management challenges. This paper describes parametric studies using various thermal management techniques such as heat spreader, increased PCB copper layer thickness, increased copper pad size for LED, high conductive plastic back cover along with pedestals, thermal via for LEDs and vent holes for the enclosure; to bring down LED temperatures within its safe operating limit. LEDs are modeled in detail (using contact resistance between the die and lead frame) in order to improve the accuracy of junction temperature prediction. A combination of thermal management solutions/techniques are used to mitigate heat from LEDs with significant bearing on cost competitiveness.
在汽车中，ECM (Electronic Control Module)用于控制车辆内部环境温度，以提高乘客的舒适度。它通常包含一个显示模块，以显示各种操作模式，如冷却空气温度，开/关鼓风机，交流，除雾器等。显示模块使用led作为照明光源。充足的照明需要在一个紧凑/受限的空间内封装几个led。此外，led必须在85°C的高环境温度下工作，这导致了重大的热管理挑战。本文描述了使用各种热管理技术的参数化研究，例如散热器，增加PCB铜层厚度，增加LED铜垫尺寸，高导电性塑料后盖以及基座，LED的热通孔和外壳的通风口;将LED温度降低到安全工作范围内。为了提高结温预测的准确性，对led进行了详细的建模(使用芯片和引线框架之间的接触电阻)。热管理解决方案/技术的组合用于减少led的热量，这对成本竞争力有重要影响。
{"title":"LED thermal management of an automotive electronic control module with display","authors":"S. Sushanth Kumar, Satishchandra C Warn, Roland Lee","doi":"10.1109/EPTC.2012.6507187","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507187","url":null,"abstract":"In automobiles, an ECM (Electronic Control Module) is used for controlling internal ambient temperature of vehicles to enhance comfort level of passengers. It typically contains a display module to show various operational modes such as cooling air temperature, ON/OFF for blower, AC, de-fogger etc. The display module uses LEDs as source of illumination. Adequate illumination requires packaging of several LEDs m a compact/constrained space. Also LEDs must operate at very high ambient temperature of 85°C that leads to significant thermal management challenges. This paper describes parametric studies using various thermal management techniques such as heat spreader, increased PCB copper layer thickness, increased copper pad size for LED, high conductive plastic back cover along with pedestals, thermal via for LEDs and vent holes for the enclosure; to bring down LED temperatures within its safe operating limit. LEDs are modeled in detail (using contact resistance between the die and lead frame) in order to improve the accuracy of junction temperature prediction. A combination of thermal management solutions/techniques are used to mitigate heat from LEDs with significant bearing on cost competitiveness.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123194311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507052
V. Chidambaram, Ho Beng Yeung, C. Sing, Daniel Rhee Min Woo
The accomplishment of fully functional high-pressure high-temperature (HPHT) well is possible only, when the packaging and interconnections in the well logging equipments can survive at higher temperatures. Currently, there are numerous choices for substrate materials and interconnection materials. However, there are hardly any encapsulation materials that can endure at 300°C. Thus, the limiting factor for the evaluation and monitoring of HPHT wells is; the availability of high-temperature endurable encapsulation material. In this paper, the endurability of three prospective candidates for high-temperature encapsulation have been characterized and reported. The three prospective candidates are benzocyclobutene (BCB), ceramic filled cyanate ester and quartz filled cyanate ester. The high-temperature endurability has been evaluated in this work by high-temperature storage at 300°C up to 500 hours. Adhesion strength of these prospective candidates with the alumina ceramic substrate and the Si die was verified by room shear testing and hot shear testing. It has been determined that the quartz filled cyanate ester could comply with the minimum indispensable requirement for this application, when sandwiched between alumina ceramic substrates, despite the loss of strength during long-term thermal aging at 300°C. The material degradation has been studied in this work, using thermo-gravimetric analysis.
{"title":"High-temperature endurable encapsulation material","authors":"V. Chidambaram, Ho Beng Yeung, C. Sing, Daniel Rhee Min Woo","doi":"10.1109/EPTC.2012.6507052","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507052","url":null,"abstract":"The accomplishment of fully functional high-pressure high-temperature (HPHT) well is possible only, when the packaging and interconnections in the well logging equipments can survive at higher temperatures. Currently, there are numerous choices for substrate materials and interconnection materials. However, there are hardly any encapsulation materials that can endure at 300°C. Thus, the limiting factor for the evaluation and monitoring of HPHT wells is; the availability of high-temperature endurable encapsulation material. In this paper, the endurability of three prospective candidates for high-temperature encapsulation have been characterized and reported. The three prospective candidates are benzocyclobutene (BCB), ceramic filled cyanate ester and quartz filled cyanate ester. The high-temperature endurability has been evaluated in this work by high-temperature storage at 300°C up to 500 hours. Adhesion strength of these prospective candidates with the alumina ceramic substrate and the Si die was verified by room shear testing and hot shear testing. It has been determined that the quartz filled cyanate ester could comply with the minimum indispensable requirement for this application, when sandwiched between alumina ceramic substrates, despite the loss of strength during long-term thermal aging at 300°C. The material degradation has been studied in this work, using thermo-gravimetric analysis.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131273785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507134
Chan Wai Kok, Tham Veng Leong, W. Yong
Bare copper (Cu) wire is one of the promising materials used in assembly packaging to replace gold wire. As copper is harder compared to gold, the formation of the looping during wire bonding is a concern and challenge especially to ball neck surface condition. Thus, the objective of this paper is to identify the key parameters that are having significant impact on the ball neck surface condition at wire bond and molding process. Evaluations are performed and the result do identified key factors that are having impact to the ball neck surface condition.
{"title":"Wire bond and molding factors influencing bare Cu wire surface conditions","authors":"Chan Wai Kok, Tham Veng Leong, W. Yong","doi":"10.1109/EPTC.2012.6507134","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507134","url":null,"abstract":"Bare copper (Cu) wire is one of the promising materials used in assembly packaging to replace gold wire. As copper is harder compared to gold, the formation of the looping during wire bonding is a concern and challenge especially to ball neck surface condition. Thus, the objective of this paper is to identify the key parameters that are having significant impact on the ball neck surface condition at wire bond and molding process. Evaluations are performed and the result do identified key factors that are having impact to the ball neck surface condition.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126401731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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