Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507103
D. V. Sorono, Ji Lin, C. T. Chong, S. Chong, S. Vempati
The rapidly increasing demand of embedded wafer level package (EMWLP) due to its advantages, smaller form factor and flexibility in system level integration leads to the development of reconstructed wafer level encapsulation. The reconstructed wafers are encapsulated with epoxy molding compound using compression molding. Due to EMWLP advanced applications, there is a need to use multi chips with different layout in a single package. The overall reconstructed wafer design then became complex that eventually leads to asymmetrical chips layout within the wafer. One major challenge in molding of reconstructed wafer with multi-chip layout was the incomplete filling due to imbalance mold compound flow during compression molding. This study was conducted to determine the actual mold compound flow during compression molding of EMWLP with multi chips layout. Mold flow studies has been carried out on different multi-chip layouts using ANSYS Poly flow/Fluent software and results revealed that asymmetrical chips layout had imbalance mold flow response. The result of the mold flow simulation was then compared to the actual mold compound flow during compression molding by performing intentional short shots at different mold filling stages. It was confirmed that actual molding with asymmetrical chips layout also resulted to unbalance mold filling. The flow of the molding compound in areas with wider gaps was faster compared to areas with narrow gaps. This suggests that the chips layout determines the actual mold compound flow during compression molding. Balanced mold compound flow was achieved by re-arranging the chips into a symmetrical layout. In addition, this paper also shows that by changing the dispensing pattern to oval shape, the actual mold compound flow on asymmetrical chips layout became balanced. The mold flow simulation results with different chips layout were validated with experimental mold compound flow tests. The simulation and experimental results revealed that the chips layout and mold compound materials dispensing pattern are critical to achieve excellent molding quality results.
{"title":"Study on mold flow during compression molding for embedded wafer level package (EMWLP) with multiple chips","authors":"D. V. Sorono, Ji Lin, C. T. Chong, S. Chong, S. Vempati","doi":"10.1109/EPTC.2012.6507103","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507103","url":null,"abstract":"The rapidly increasing demand of embedded wafer level package (EMWLP) due to its advantages, smaller form factor and flexibility in system level integration leads to the development of reconstructed wafer level encapsulation. The reconstructed wafers are encapsulated with epoxy molding compound using compression molding. Due to EMWLP advanced applications, there is a need to use multi chips with different layout in a single package. The overall reconstructed wafer design then became complex that eventually leads to asymmetrical chips layout within the wafer. One major challenge in molding of reconstructed wafer with multi-chip layout was the incomplete filling due to imbalance mold compound flow during compression molding. This study was conducted to determine the actual mold compound flow during compression molding of EMWLP with multi chips layout. Mold flow studies has been carried out on different multi-chip layouts using ANSYS Poly flow/Fluent software and results revealed that asymmetrical chips layout had imbalance mold flow response. The result of the mold flow simulation was then compared to the actual mold compound flow during compression molding by performing intentional short shots at different mold filling stages. It was confirmed that actual molding with asymmetrical chips layout also resulted to unbalance mold filling. The flow of the molding compound in areas with wider gaps was faster compared to areas with narrow gaps. This suggests that the chips layout determines the actual mold compound flow during compression molding. Balanced mold compound flow was achieved by re-arranging the chips into a symmetrical layout. In addition, this paper also shows that by changing the dispensing pattern to oval shape, the actual mold compound flow on asymmetrical chips layout became balanced. The mold flow simulation results with different chips layout were validated with experimental mold compound flow tests. The simulation and experimental results revealed that the chips layout and mold compound materials dispensing pattern are critical to achieve excellent molding quality results.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131092702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507179
S. Praveen, Muhammad Rawi Mohamed Zain, Zhang Xin, David J. Johnson
This paper discusses the importance of having a tapered via in TSV integration processes and the various ways currently used to achieve it. In addition, a novel way of creating this tapered via with single step Deep Reactive Ion Etching (DRIE) process to achieve it is also presented.
{"title":"Development of a single step via tapering etch process using deep reactive ion etching with low sidewall roughness for through-silicon via applications","authors":"S. Praveen, Muhammad Rawi Mohamed Zain, Zhang Xin, David J. Johnson","doi":"10.1109/EPTC.2012.6507179","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507179","url":null,"abstract":"This paper discusses the importance of having a tapered via in TSV integration processes and the various ways currently used to achieve it. In addition, a novel way of creating this tapered via with single step Deep Reactive Ion Etching (DRIE) process to achieve it is also presented.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122047371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507185
L. Siow, W. Deng, Qing Xin Zhang, T. Chai, C. G. Koh, D. Witarsa, Xianfeng Wang, Hongqi Sun, T. Ando, T. Y. Tee, J. Wong
This paper will revise the traditional wafer fabrication process flow to accommodate the new material used to achieve 40 um fine pitch Cu pillar with minimize seed layer undercut. New photo-resist material is introduced to attain a single coating of 40um thickness and it has demonstrated the capability of attaining an aspect ratio of 2. The wafer fabrication process ended using a combination of seed layer (Ti/Cu) wet and dry etching. It has shown the potential of achieving almost zero undercut which is very critical for a 20um via. Cross-sectional SEM will be carried out to verify the side wall profile and the footing of the photo-resist. FIB cross-section is done to identify Ti and Cu undercut. Bump shear test will be performed after the seed layer etching to quantify the failure mode of a bump with and without seed layer undercuts.
{"title":"Fine pitch Cu pillar wafer process development and seed layer etching characterization","authors":"L. Siow, W. Deng, Qing Xin Zhang, T. Chai, C. G. Koh, D. Witarsa, Xianfeng Wang, Hongqi Sun, T. Ando, T. Y. Tee, J. Wong","doi":"10.1109/EPTC.2012.6507185","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507185","url":null,"abstract":"This paper will revise the traditional wafer fabrication process flow to accommodate the new material used to achieve 40 um fine pitch Cu pillar with minimize seed layer undercut. New photo-resist material is introduced to attain a single coating of 40um thickness and it has demonstrated the capability of attaining an aspect ratio of 2. The wafer fabrication process ended using a combination of seed layer (Ti/Cu) wet and dry etching. It has shown the potential of achieving almost zero undercut which is very critical for a 20um via. Cross-sectional SEM will be carried out to verify the side wall profile and the footing of the photo-resist. FIB cross-section is done to identify Ti and Cu undercut. Bump shear test will be performed after the seed layer etching to quantify the failure mode of a bump with and without seed layer undercuts.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":" 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120834756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507181
Song Li, Peng Liu, Qisui Wang, Xia Chen
The silver conductive films are formed by depositing the Ag nanoparticles (NPs) inks dispersion onto the plastic substrate and drying the solvent at room temperature. This paper aims to investigate the effects of the different capping agent poly(vinylpyrrolidone) (PVP), polyaniline (PAN), L-cysteine (L-cys), and oleic acid (OA)) on the electrical resistivity. The high conductivity was achieved by the self-aggregation of Ag/PVP NPs after drying the solvent. We compared the conductivity ability of four Ag NPs, and thought the coordination ability and adhesive force onto substrates of capping agent resulted in the different conductivity. This method is expected to have many potential applications for low-cost printable electronics.
{"title":"Preparation of stable aqueous based Ag nanoparticle ink with different capping agent for printing on a plastic substrate","authors":"Song Li, Peng Liu, Qisui Wang, Xia Chen","doi":"10.1109/EPTC.2012.6507181","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507181","url":null,"abstract":"The silver conductive films are formed by depositing the Ag nanoparticles (NPs) inks dispersion onto the plastic substrate and drying the solvent at room temperature. This paper aims to investigate the effects of the different capping agent poly(vinylpyrrolidone) (PVP), polyaniline (PAN), L-cysteine (L-cys), and oleic acid (OA)) on the electrical resistivity. The high conductivity was achieved by the self-aggregation of Ag/PVP NPs after drying the solvent. We compared the conductivity ability of four Ag NPs, and thought the coordination ability and adhesive force onto substrates of capping agent resulted in the different conductivity. This method is expected to have many potential applications for low-cost printable electronics.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"11 1-3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129713590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507178
Youkai Chen, F. Zhu, H. Liao, Wei Zhang, Sheng Liu
Mechanical behaviors of single-walled carbon nanotube (SWCNT) and Ni-coated single-walled carbon nanotube (SWCNT-Ni) were investigated by using molecular dynamics (MD) simulation method. From these results of molecular dynamics simulation for two models of SWCNT and SWCNT-Ni, it was found that the Young's Modulus of SWCNT was higher than that of SWCNT-Ni, and failure stress and failure strain of SWCNT were also lower than that of SWCNT-Ni at same temperature point of 300K, 500K, and 700K. In order to understand compressing behaviors of different temperature, two different molecular models of SWCNT and SWCNT-Ni were analyzed at 300K, 500K and 700K respectively, and it was revealed that temperature fluctuation could also change the Young's Modulus, critical stress, and critical strain. In this work, it was very clear that nickel atoms on surface of SWCNT-Ni could retard local buckling at the processing of compressing. Coating nickel atoms on surface of SWCNT could improve some mechanical properties of SWCNT.
{"title":"Compressing deformation investigation of single-walled carbon nanotube coated with Ni","authors":"Youkai Chen, F. Zhu, H. Liao, Wei Zhang, Sheng Liu","doi":"10.1109/EPTC.2012.6507178","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507178","url":null,"abstract":"Mechanical behaviors of single-walled carbon nanotube (SWCNT) and Ni-coated single-walled carbon nanotube (SWCNT-Ni) were investigated by using molecular dynamics (MD) simulation method. From these results of molecular dynamics simulation for two models of SWCNT and SWCNT-Ni, it was found that the Young's Modulus of SWCNT was higher than that of SWCNT-Ni, and failure stress and failure strain of SWCNT were also lower than that of SWCNT-Ni at same temperature point of 300K, 500K, and 700K. In order to understand compressing behaviors of different temperature, two different molecular models of SWCNT and SWCNT-Ni were analyzed at 300K, 500K and 700K respectively, and it was revealed that temperature fluctuation could also change the Young's Modulus, critical stress, and critical strain. In this work, it was very clear that nickel atoms on surface of SWCNT-Ni could retard local buckling at the processing of compressing. Coating nickel atoms on surface of SWCNT could improve some mechanical properties of SWCNT.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129082841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507100
Alvin Lee, Jay Su, J. McCutcheon, B. Wang, L. Tsai, A. Shorey
Interest has intensified in temporary wafer bonding technology for thin wafer handling to realize 3D system integration. Several challenges such as thermal stability, process compatibility, and chemical resistance for temporary adhesives have been addressed in numerous publications. However, the correlation of thickness variation among carrier, temporary adhesive, temporary bonding, and final thinning thickness is rarely discussed because of limitations in metrology. The work described here utilized a WaferBOND® advanced bonding material and ZoneBOND® [1] technology from Brewer Science, Inc., as well as the Tropel® FlatMaster® MSP-300 and semiconductor glass wafers from Corning Incorporated to evaluate the influence of each layer and suitable metrology to enhance overall performance.
{"title":"Optimization of temporary bonding through high-resolution metrologies to realize ultrathin wafer handling","authors":"Alvin Lee, Jay Su, J. McCutcheon, B. Wang, L. Tsai, A. Shorey","doi":"10.1109/EPTC.2012.6507100","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507100","url":null,"abstract":"Interest has intensified in temporary wafer bonding technology for thin wafer handling to realize 3D system integration. Several challenges such as thermal stability, process compatibility, and chemical resistance for temporary adhesives have been addressed in numerous publications. However, the correlation of thickness variation among carrier, temporary adhesive, temporary bonding, and final thinning thickness is rarely discussed because of limitations in metrology. The work described here utilized a WaferBOND® advanced bonding material and ZoneBOND® [1] technology from Brewer Science, Inc., as well as the Tropel® FlatMaster® MSP-300 and semiconductor glass wafers from Corning Incorporated to evaluate the influence of each layer and suitable metrology to enhance overall performance.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126542302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507136
J. Ling, A. Tay, K. F. Choo, W. Chen, D. Kendig
Thermal characterization of high power microwave devices is important for determining their reliability. Exceeding the optimal temperature will have a detrimental effect on the performance and reliability of these devices. In this paper, the temperature a power amplifier (PA) Monolithic Microwave Integrated Circuit (MMIC) was measured using the traditional Infrared (IR) thermography technique and an emerging technique called Thermoreflectance (TR) thermography. The measured results were compared to those calculated using finite element analysis (FEA). It was found that temperatures measured using TR thermography agreed very well with FEA results, whereas temperatures measured using IR thermography did not. This could be attributed to the presence of reflective and low emissivity surfaces on the PA MMIC and the inadequate spatial resolution of the IR camera.
{"title":"Measurement of MMIC gate temperature using infrared and Thermoreflectance thermography","authors":"J. Ling, A. Tay, K. F. Choo, W. Chen, D. Kendig","doi":"10.1109/EPTC.2012.6507136","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507136","url":null,"abstract":"Thermal characterization of high power microwave devices is important for determining their reliability. Exceeding the optimal temperature will have a detrimental effect on the performance and reliability of these devices. In this paper, the temperature a power amplifier (PA) Monolithic Microwave Integrated Circuit (MMIC) was measured using the traditional Infrared (IR) thermography technique and an emerging technique called Thermoreflectance (TR) thermography. The measured results were compared to those calculated using finite element analysis (FEA). It was found that temperatures measured using TR thermography agreed very well with FEA results, whereas temperatures measured using IR thermography did not. This could be attributed to the presence of reflective and low emissivity surfaces on the PA MMIC and the inadequate spatial resolution of the IR camera.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121108775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507175
Winston Sun, T. Sun, K.C.S. Lim, Mianzhi Ding, R. Lim, B. Johari, U. Dinish, M. Olivo
We report a simple yet effective approach to interconnect pairs of orthogonally aligned out-of-plane bond-pads that are separated at wide gaps of about 100 μm. The developed method can effectively bridge interconnections between a MEMS micromirror device chip (width × height × thickness: 1.9 × 2.2 × 0.5 mm³) on a mini PCB bench (width × length × thickness: 1.6 × 12 × 0.4 mm³) with just a few standard procedural steps. The measured average interconnection resistance is about 0.6 Ω. The packaged system is currently target for optical coherence tomography (OCT) applications and the concept can be applied to many other miniaturized medical device packaging situations that require orthogonally aligned out-of-plane interconnections.
{"title":"Effective 90° interconnections using laser solder jetting technologies for optical coherence tomography applications","authors":"Winston Sun, T. Sun, K.C.S. Lim, Mianzhi Ding, R. Lim, B. Johari, U. Dinish, M. Olivo","doi":"10.1109/EPTC.2012.6507175","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507175","url":null,"abstract":"We report a simple yet effective approach to interconnect pairs of orthogonally aligned out-of-plane bond-pads that are separated at wide gaps of about 100 μm. The developed method can effectively bridge interconnections between a MEMS micromirror device chip (width × height × thickness: 1.9 × 2.2 × 0.5 mm³) on a mini PCB bench (width × length × thickness: 1.6 × 12 × 0.4 mm³) with just a few standard procedural steps. The measured average interconnection resistance is about 0.6 Ω. The packaged system is currently target for optical coherence tomography (OCT) applications and the concept can be applied to many other miniaturized medical device packaging situations that require orthogonally aligned out-of-plane interconnections.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"223 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124877296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507072
A. Trigg, C. T. Chong, Sheryl Yong Puay Fen, Jasmond Lee Thiam Kwee, Calvin Chua Hung Ming, Sharon Chan Sok Mung, Chen Ping, V. Ganesh, By Low, T. Chu, E. P. Leng
The use of copper wire for wire bonding integrated circuits (ICs) has increased significantly in recent years, driven mainly by the dramatic increase in the cost of gold. The technical advantages and limitations, particularly with respect to reliability, of copper for wire bonding, compared with gold, have been widely reported. This paper describes reliability studies comparing on copper, palladium coated copper and gold wires using a dedicated test vehicle comprising a modular test chip with multiple daisy chains and corrosion sensors in a BGA package. The reliability tests were High Temperature Storage (HTS), 1000 hours at 150 ºC, Thermal cycling (TC) from 1000 cycles from −40 ºC to + 125 ºC, Temperature Humidity Bias (THB), 1000 hours at 85ºC/85% RH, 20 V applied, and unbiased HAST. It was found that performance was strongly dependent on the wire type and mold compound. Copper wires with one mold compound having a higher chlorine level (12mmm), showed high leakage currents and rates of failure during THB. Both copper and palladium coated copper wires with a different mold compound showed high rates of failure during thermal cycling.
{"title":"Copper wire bond reliability evaluation using a modular test chip","authors":"A. Trigg, C. T. Chong, Sheryl Yong Puay Fen, Jasmond Lee Thiam Kwee, Calvin Chua Hung Ming, Sharon Chan Sok Mung, Chen Ping, V. Ganesh, By Low, T. Chu, E. P. Leng","doi":"10.1109/EPTC.2012.6507072","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507072","url":null,"abstract":"The use of copper wire for wire bonding integrated circuits (ICs) has increased significantly in recent years, driven mainly by the dramatic increase in the cost of gold. The technical advantages and limitations, particularly with respect to reliability, of copper for wire bonding, compared with gold, have been widely reported. This paper describes reliability studies comparing on copper, palladium coated copper and gold wires using a dedicated test vehicle comprising a modular test chip with multiple daisy chains and corrosion sensors in a BGA package. The reliability tests were High Temperature Storage (HTS), 1000 hours at 150 ºC, Thermal cycling (TC) from 1000 cycles from −40 ºC to + 125 ºC, Temperature Humidity Bias (THB), 1000 hours at 85ºC/85% RH, 20 V applied, and unbiased HAST. It was found that performance was strongly dependent on the wire type and mold compound. Copper wires with one mold compound having a higher chlorine level (12mmm), showed high leakage currents and rates of failure during THB. Both copper and palladium coated copper wires with a different mold compound showed high rates of failure during thermal cycling.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127560707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507076
K. Rebibis, C. Gerets, G. Capuz, R. Daily, T. Wang, A. Lamanna, F. Duval, A. Miller, R. Guino, R. Peddi, E. Beyne, B. Swinnen
As the demand for 3D packaging increases, selecting reliable and cost effective materials to be used to build these complex packages has gained a lot of importance. As current IC technology nodes are becoming “Moore-than-Moore” challenging, thus industry and research institutes alike are trying to find ways of addressing this challenge. The integration of new types of underfill materials in 3D stacking is one very important part of the package material set that will determine its reliability and cost effectiveness. With the introduction of 3D technology, bump sizes and pitches have been scaled down significantly which in turn has also shrank underfill gaps between dies which complicates the assembly of 3D stacks. The need of new underfill materials and underfilling concepts becomes inevitable. It is quite difficult to make traditional capillary type underfills and underfilling methods to work due to the very narrow gaps and fine bump pitches that 3D stacks have. Pre-applied underfills (Wafer Applied or No Flow) with or without fillers (submicron or Nano-fillers) may prove to be a suitable solution for this concern. Using a 2 die-stack test vehicle with a bump pitch of 40 μm (with Cu and Cu/Sn bumps) and an underfill gap of 13.5 μm, four (4) different underfill materials (2 NUFs and 2 WAUFs) were screened. This paper will report on the assessment done for both wafer applied and no flow underfill materials, the differences in the application process, the material's filling and stacking process capabilities and finally the reliability of the 3D stacks. The materials were initially screened based on the test vehicle geometry then processed thru the different phases of the screening process. The changes in thermo-compression bonding parameters used in the experiment to improve the electrical yields will also be discussed. It will also be shown how underfill materials with and without fillers differ in the thermo-compression bonding force required to be able to get good bump-to-bump connection.
{"title":"Wafer applied and no flow underfill screening for 3D stacks","authors":"K. Rebibis, C. Gerets, G. Capuz, R. Daily, T. Wang, A. Lamanna, F. Duval, A. Miller, R. Guino, R. Peddi, E. Beyne, B. Swinnen","doi":"10.1109/EPTC.2012.6507076","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507076","url":null,"abstract":"As the demand for 3D packaging increases, selecting reliable and cost effective materials to be used to build these complex packages has gained a lot of importance. As current IC technology nodes are becoming “Moore-than-Moore” challenging, thus industry and research institutes alike are trying to find ways of addressing this challenge. The integration of new types of underfill materials in 3D stacking is one very important part of the package material set that will determine its reliability and cost effectiveness. With the introduction of 3D technology, bump sizes and pitches have been scaled down significantly which in turn has also shrank underfill gaps between dies which complicates the assembly of 3D stacks. The need of new underfill materials and underfilling concepts becomes inevitable. It is quite difficult to make traditional capillary type underfills and underfilling methods to work due to the very narrow gaps and fine bump pitches that 3D stacks have. Pre-applied underfills (Wafer Applied or No Flow) with or without fillers (submicron or Nano-fillers) may prove to be a suitable solution for this concern. Using a 2 die-stack test vehicle with a bump pitch of 40 μm (with Cu and Cu/Sn bumps) and an underfill gap of 13.5 μm, four (4) different underfill materials (2 NUFs and 2 WAUFs) were screened. This paper will report on the assessment done for both wafer applied and no flow underfill materials, the differences in the application process, the material's filling and stacking process capabilities and finally the reliability of the 3D stacks. The materials were initially screened based on the test vehicle geometry then processed thru the different phases of the screening process. The changes in thermo-compression bonding parameters used in the experiment to improve the electrical yields will also be discussed. It will also be shown how underfill materials with and without fillers differ in the thermo-compression bonding force required to be able to get good bump-to-bump connection.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134175452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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