This paper presents an integrated Hall switch sensor based on SMIC 0.18 µm CMOS technology. The system includes a front-end Hall element and a back-end signal processing circuit. By optimizing the structure of the Hall element and using the orthogonal coupling and spinning current technology, the offset voltage can be suppressed effectively. The simulation results showed that the Hall switch can eliminate offset voltage greater than 1 mV at 3.3 V supply voltage. Two modes of the Hall switch circuit, the awake mode and the sleep mode, were realized by using clock logic signals without compromising the performance of the Hall switch, thereby reducing power consumption. The test results showed that the operate point and the release point of the switch were within the range of 3–7 mT at 3.3 V supply voltage. Meanwhile, the current consumption is 7.89 µA.
{"title":"Low-Power CMOS Integrated Hall Switch Sensor","authors":"Rongshan Wei, Shizhong Guo, Shanzhi Yang","doi":"10.1155/2017/5375619","DOIUrl":"https://doi.org/10.1155/2017/5375619","url":null,"abstract":"This paper presents an integrated Hall switch sensor based on SMIC 0.18 µm CMOS technology. The system includes a front-end Hall element and a back-end signal processing circuit. By optimizing the structure of the Hall element and using the orthogonal coupling and spinning current technology, the offset voltage can be suppressed effectively. The simulation results showed that the Hall switch can eliminate offset voltage greater than 1 mV at 3.3 V supply voltage. Two modes of the Hall switch circuit, the awake mode and the sleep mode, were realized by using clock logic signals without compromising the performance of the Hall switch, thereby reducing power consumption. The test results showed that the operate point and the release point of the switch were within the range of 3–7 mT at 3.3 V supply voltage. Meanwhile, the current consumption is 7.89 µA.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2017-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2017/5375619","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42426324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new floating emulator for the flux-controlled memristor is introduced in this paper. The proposed emulator circuit is very simple and consists of only two current feedback operational amplifiers (CFOAs), two analog multipliers, three resistors, and two capacitors. The emulator can be configured as an incremental or decremental type memristor by using an additional switch. The mathematical model of the emulator is derived to characterize its behavior. The hysteresis behavior of the emulator is discussed in detail, showing that the pinched hysteresis loops in - plane depend not only on the amplitude-to-frequency ratio of the exciting signal but also on the time constant of the emulator circuit itself. Experimental tests are provided to validate the emulator’s workability.
{"title":"A Novel Floating Memristor Emulator with Minimal Components","authors":"Zhijun Li, Yicheng Zeng, M. Ma","doi":"10.1155/2017/1609787","DOIUrl":"https://doi.org/10.1155/2017/1609787","url":null,"abstract":"A new floating emulator for the flux-controlled memristor is introduced in this paper. The proposed emulator circuit is very simple and consists of only two current feedback operational amplifiers (CFOAs), two analog multipliers, three resistors, and two capacitors. The emulator can be configured as an incremental or decremental type memristor by using an additional switch. The mathematical model of the emulator is derived to characterize its behavior. The hysteresis behavior of the emulator is discussed in detail, showing that the pinched hysteresis loops in - plane depend not only on the amplitude-to-frequency ratio of the exciting signal but also on the time constant of the emulator circuit itself. Experimental tests are provided to validate the emulator’s workability.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2017-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2017/1609787","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43872556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The total ionizing dose irradiation effects are investigated in Si vertical diffused MOSFETs (VDMOSs) with different gate dielectrics including single SiO2 layer and double Si3N4/SiO2 layer. Radiation-induced holes trapping is greater for single SiO2 layer than for double Si3N4/SiO2 layer. Dielectric oxidation temperature dependent TID effects are also studied. Holes trapping induced negative threshold voltage shift is smaller for SiO2 at lower oxidation temperature. Gate bias during irradiation leads to different shift for different gate dielectrics. Single SiO2 layer shows the worst negative at , while double Si3N4/SiO2 shows negative shift at , positive shift at , and negligible shift at .
{"title":"Total Ionizing Dose Effects of Si Vertical Diffused MOSFET with SiO2 and Si3N4/SiO2 Gate Dielectrics","authors":"Jiongjiong Mo, Xuran Zhao, Min Zhou","doi":"10.1155/2017/9685685","DOIUrl":"https://doi.org/10.1155/2017/9685685","url":null,"abstract":"The total ionizing dose irradiation effects are investigated in Si vertical diffused MOSFETs (VDMOSs) with different gate dielectrics including single SiO2 layer and double Si3N4/SiO2 layer. Radiation-induced holes trapping is greater for single SiO2 layer than for double Si3N4/SiO2 layer. Dielectric oxidation temperature dependent TID effects are also studied. Holes trapping induced negative threshold voltage shift is smaller for SiO2 at lower oxidation temperature. Gate bias during irradiation leads to different shift for different gate dielectrics. Single SiO2 layer shows the worst negative at , while double Si3N4/SiO2 shows negative shift at , positive shift at , and negligible shift at .","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2017/9685685","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43829173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
It is necessary for three-level explosion-proof inverters to have high thermal stability and good output characteristics avoiding problems caused by power devices, such as IGBT, so it becomes a hot and difficult research point using only one control algorithm to guarantee both output characteristics and high thermal stability. Firstly, the simplified SVPWM (Space Vector Pulse Width Modulation) algorithm was illustrated based on the NPC (neutral-point-clamped) three-level inverter, and then the quasi-square wave control was brought in and made into a novel holographic equivalent dual-mode modulation algorithm together with the simplified SVPWM. The holographic equivalent model was established to analyze the relative advantages comparing with the two single algorithms. Finally, the dynamic output and steady power device losses were analyzed, based on which the power loss calculation and system simulation were conducted as well. The experiment proved that the high-power three-level explosion-proof inverter has good output characteristics and thermal stability.
三电平防爆逆变器必须具有高的热稳定性和良好的输出特性，以避免IGBT等功率器件带来的问题，因此仅使用一种控制算法来保证输出特性和高的热稳定成为研究的热点和难点。首先，在NPC（neutral point clamp）三电平逆变器的基础上，给出了空间矢量脉宽调制（SVPWM）的简化算法，然后引入准方波控制，将其与简化的SVPWM一起构成一种新的全息等效双模调制算法。建立了全息等效模型，分析了两种算法的相对优势。最后，对功率器件的动态输出和稳态损耗进行了分析，并在此基础上进行了功率损耗计算和系统仿真。实验证明，该大功率三电平防爆逆变器具有良好的输出特性和热稳定性。
{"title":"Power Device Thermal Fault Tolerant Control of High-Power Three-Level Explosion-Proof Inverter Based on Holographic Equivalent Dual-Mode Modulation","authors":"Shi-Zhou Xu, Chun-jie Wang, Yu-feng Peng","doi":"10.1155/2017/6961832","DOIUrl":"https://doi.org/10.1155/2017/6961832","url":null,"abstract":"It is necessary for three-level explosion-proof inverters to have high thermal stability and good output characteristics avoiding problems caused by power devices, such as IGBT, so it becomes a hot and difficult research point using only one control algorithm to guarantee both output characteristics and high thermal stability. Firstly, the simplified SVPWM (Space Vector Pulse Width Modulation) algorithm was illustrated based on the NPC (neutral-point-clamped) three-level inverter, and then the quasi-square wave control was brought in and made into a novel holographic equivalent dual-mode modulation algorithm together with the simplified SVPWM. The holographic equivalent model was established to analyze the relative advantages comparing with the two single algorithms. Finally, the dynamic output and steady power device losses were analyzed, based on which the power loss calculation and system simulation were conducted as well. The experiment proved that the high-power three-level explosion-proof inverter has good output characteristics and thermal stability.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2017-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2017/6961832","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44498043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The design, implementation, and measurements of a high efficiency and high power wideband GaN HEMT power amplifier are presented. Package parasitic effect is reduced significantly by a novel compensation circuit design to improve the accuracy of impedance matching. An improved structure is proposed based on the traditional Class-F structure with all even harmonics and the third harmonic effectively controlled, respectively. Also the stepped-impedance matching method is applied to the third harmonic control network, which has a positive effect on the expansion bandwidth. CGH40025F power transistor is utilized to build the power amplifier working at 0.8 to 2.7 GHz, with the measured saturated output power 20–50 W, drain efficiency 52%–76%, and gain level above 10 dB. The second and the third harmonic suppression levels are maintained at −16 to −36 dBc and −16 to −33 dBc, respectively. The simulation and the measurement results of the proposed power amplifier show good consistency.
{"title":"Design of 0.8–2.7 GHz High Power Class-F Harmonic-Tuned Power Amplifier with Parasitic Compensation Circuit","authors":"Zhiqun Cheng, Xuefei Xuan, Huajie Ke, Guohua Liu, Zhihua Dong, S. Gao","doi":"10.1155/2017/2543917","DOIUrl":"https://doi.org/10.1155/2017/2543917","url":null,"abstract":"The design, implementation, and measurements of a high efficiency and high power wideband GaN HEMT power amplifier are presented. Package parasitic effect is reduced significantly by a novel compensation circuit design to improve the accuracy of impedance matching. An improved structure is proposed based on the traditional Class-F structure with all even harmonics and the third harmonic effectively controlled, respectively. Also the stepped-impedance matching method is applied to the third harmonic control network, which has a positive effect on the expansion bandwidth. CGH40025F power transistor is utilized to build the power amplifier working at 0.8 to 2.7 GHz, with the measured saturated output power 20–50 W, drain efficiency 52%–76%, and gain level above 10 dB. The second and the third harmonic suppression levels are maintained at −16 to −36 dBc and −16 to −33 dBc, respectively. The simulation and the measurement results of the proposed power amplifier show good consistency.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2017-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2017/2543917","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44338648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A simple half-bridge, galvanic separated power supply which can be short circuit proof is proposed for gate driver local supplies. The supply is made while hacking a common mode type filter as a transformer, as the transformer shows a good insulation, it has a very low parasitic capacitance between primary and secondary coils, and it is cost-effective. Very low standby losses were observed during lab experiments. This makes it compatible with energy efficient drives and solar inverters.
{"title":"Less-Conventional Low-Consumption Galvanic Separated MOSFET-IGBT Gate Drive Supply","authors":"Jean Marie V. Bikorimana, A. V. Bossche","doi":"10.1155/2017/4181549","DOIUrl":"https://doi.org/10.1155/2017/4181549","url":null,"abstract":"A simple half-bridge, galvanic separated power supply which can be short circuit proof is proposed for gate driver local supplies. The supply is made while hacking a common mode type filter as a transformer, as the transformer shows a good insulation, it has a very low parasitic capacitance between primary and secondary coils, and it is cost-effective. Very low standby losses were observed during lab experiments. This makes it compatible with energy efficient drives and solar inverters.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2017-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2017/4181549","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47431146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Satyam Shukla, S. S. Gill, Navneet Kaur, H. S. Jatana, Varun Nehru
Technology scaling below 22 nm has brought several detrimental effects such as increased short channel effects (SCEs) and leakage currents. In deep submicron technology further scaling in gate length and oxide thickness can be achieved by changing the device structure of MOSFET. For 10–30 nm channel length multigate MOSFETs have been considered as most promising devices and FinFETs are the leading multigate MOSFET devices. Process parameters can be varied to obtain the desired performance of the FinFET device. In this paper, evaluation of on-off current ratio ( ), subthreshold swing (SS) and Drain Induced Barrier Lowering (DIBL) for different process parameters, that is, doping concentration (1015/cm3 to 1018/cm3), oxide thickness (0.5 nm and 1 nm), and fin height (10 nm to 40 nm), has been presented for 20 nm triangular FinFET device. Density gradient model used in design simulation incorporates the considerable quantum effects and provides more practical environment for device simulation. Simulation result shows that fin shape has great impact on FinFET performance and triangular fin shape leads to reduction in leakage current and SCEs. Comparative analysis of simulation results has been investigated to observe the impact of process parameters on the performance of designed FinFET.
{"title":"Comparative Simulation Analysis of Process Parameter Variations in 20 nm Triangular FinFET","authors":"Satyam Shukla, S. S. Gill, Navneet Kaur, H. S. Jatana, Varun Nehru","doi":"10.1155/2017/5947819","DOIUrl":"https://doi.org/10.1155/2017/5947819","url":null,"abstract":"Technology scaling below 22 nm has brought several detrimental effects such as increased short channel effects (SCEs) and leakage currents. In deep submicron technology further scaling in gate length and oxide thickness can be achieved by changing the device structure of MOSFET. For 10–30 nm channel length multigate MOSFETs have been considered as most promising devices and FinFETs are the leading multigate MOSFET devices. Process parameters can be varied to obtain the desired performance of the FinFET device. In this paper, evaluation of on-off current ratio ( ), subthreshold swing (SS) and Drain Induced Barrier Lowering (DIBL) for different process parameters, that is, doping concentration (1015/cm3 to 1018/cm3), oxide thickness (0.5 nm and 1 nm), and fin height (10 nm to 40 nm), has been presented for 20 nm triangular FinFET device. Density gradient model used in design simulation incorporates the considerable quantum effects and provides more practical environment for device simulation. Simulation result shows that fin shape has great impact on FinFET performance and triangular fin shape leads to reduction in leakage current and SCEs. Comparative analysis of simulation results has been investigated to observe the impact of process parameters on the performance of designed FinFET.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2017-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2017/5947819","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41287981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the current study, an Au/BN/C microwave back-to-back Schottky device is designed and characterized. The device morphology and roughness were evaluated by means of scanning electron and atomic force microscopy. As verified by the Richardson–Schottky current conduction transport mechanism which is well fitted to the experimental data, the temperature dependence of the current-voltage characteristics of the devices is dominated by the electric field assisted thermionic emission of charge carriers over a barrier height of ~0.87 eV and depletion region width of ~1.1 μm. Both the depletion width and barrier height followed an increasing trend with increasing temperature. On the other hand, the alternating current conductivity analysis which was carried out in the frequency range of 100–1400 MHz revealed the domination of the phonon assisted quantum mechanical tunneling (hopping) of charge carriers through correlated barriers (CBH). In addition, the impedance and power spectral studies carried out in the gigahertz-frequency domain revealed a resonance-antiresonance feature at frequency of ~1.6 GHz. The microwave power spectra of this device revealed an ideal band stop filter of notch frequency of ~1.6 GHz. The ac signal analysis of this device displays promising characteristics for using this device as wave traps.
{"title":"Microwave Impedance Spectroscopy and Temperature Effects on the Electrical Properties of Au/BN/C Interfaces","authors":"H. Khanfar, A. F. Qasrawi, Yasmeen Kh. Ghannam","doi":"10.1155/2017/4791347","DOIUrl":"https://doi.org/10.1155/2017/4791347","url":null,"abstract":"In the current study, an Au/BN/C microwave back-to-back Schottky device is designed and characterized. The device morphology and roughness were evaluated by means of scanning electron and atomic force microscopy. As verified by the Richardson–Schottky current conduction transport mechanism which is well fitted to the experimental data, the temperature dependence of the current-voltage characteristics of the devices is dominated by the electric field assisted thermionic emission of charge carriers over a barrier height of ~0.87 eV and depletion region width of ~1.1 μm. Both the depletion width and barrier height followed an increasing trend with increasing temperature. On the other hand, the alternating current conductivity analysis which was carried out in the frequency range of 100–1400 MHz revealed the domination of the phonon assisted quantum mechanical tunneling (hopping) of charge carriers through correlated barriers (CBH). In addition, the impedance and power spectral studies carried out in the gigahertz-frequency domain revealed a resonance-antiresonance feature at frequency of ~1.6 GHz. The microwave power spectra of this device revealed an ideal band stop filter of notch frequency of ~1.6 GHz. The ac signal analysis of this device displays promising characteristics for using this device as wave traps.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2017-02-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2017/4791347","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45137687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a substrate integrated waveguide (SIW) bandpass filter using defected ground structure (DGS) with complementary split ring resonators (CSRRs) is proposed. By using the unique resonant properties of CSRRs and DGSs, two passbands with a transmission zero in the middle have been achieved. The resonant modes of the two passbands are different and the bandwidth of the second passband is much wider than that of the first one. In order to increase out-of-band rejection, a pair of dumbbell DGSs has been added on each side of the CSRRs. The structure is analyzed using equivalent circuit models and simulated based on EM simulation software. For validation, the proposed filter is fabricated and measured. The measurement results are in good agreement with the simulated ones.
{"title":"Design of a SIW Bandpass Filter Using Defected Ground Structure with CSRRs","authors":"Weiping Li, Z. Tang, Xin Cao","doi":"10.1155/2017/1606341","DOIUrl":"https://doi.org/10.1155/2017/1606341","url":null,"abstract":"In this paper, a substrate integrated waveguide (SIW) bandpass filter using defected ground structure (DGS) with complementary split ring resonators (CSRRs) is proposed. By using the unique resonant properties of CSRRs and DGSs, two passbands with a transmission zero in the middle have been achieved. The resonant modes of the two passbands are different and the bandwidth of the second passband is much wider than that of the first one. In order to increase out-of-band rejection, a pair of dumbbell DGSs has been added on each side of the CSRRs. The structure is analyzed using equivalent circuit models and simulated based on EM simulation software. For validation, the proposed filter is fabricated and measured. The measurement results are in good agreement with the simulated ones.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2017-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2017/1606341","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44874892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose a new design, Physical Unclonable Function (PUF) scheme, for the Internet of Things (IoT), which has been suffering from multiple-level security threats. As more and more objects interconnect on IoT networks, the identity of each thing is very important. To authenticate each object, we design an impedance mismatch PUF, which exploits random physical factors of the transmission line to generate a security unique private key. The characteristic impedance of the transmission line and signal transmission theory of the printed circuit board (PCB) are also analyzed in detail. To improve the reliability, current feedback amplifier (CFA) method is applied on the PUF. Finally, the proposed scheme is implemented and tested. The measure results show that impedance mismatch PUF provides better unpredictability and randomness.
{"title":"Design Impedance Mismatch Physical Unclonable Functions for IoT Security","authors":"Xiaomin Zheng, Yuejun Zhang, Jiaweng Zhang, Huang Wenqi","doi":"10.1155/2017/4070589","DOIUrl":"https://doi.org/10.1155/2017/4070589","url":null,"abstract":"We propose a new design, Physical Unclonable Function (PUF) scheme, for the Internet of Things (IoT), which has been suffering from multiple-level security threats. As more and more objects interconnect on IoT networks, the identity of each thing is very important. To authenticate each object, we design an impedance mismatch PUF, which exploits random physical factors of the transmission line to generate a security unique private key. The characteristic impedance of the transmission line and signal transmission theory of the printed circuit board (PCB) are also analyzed in detail. To improve the reliability, current feedback amplifier (CFA) method is applied on the PUF. Finally, the proposed scheme is implemented and tested. The measure results show that impedance mismatch PUF provides better unpredictability and randomness.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2017-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2017/4070589","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42742532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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