Yu Xiao, Zhengyuan Zhang, Xiyi Liao, F. Jiang, Yan Wang
To quickly destroy electronic devices and ensure information security, a destruction mechanism of transient electronic devices was designed in this paper. By placing the Ni-Cr film resistance and the energetic material between the chip and the package and heating the resistance by an electric current, the energetic material expanded and the chip cracked. The information on the chip was destroyed. The author simulated the temperature distribution and stress of the power-on structure in different sizes by ANSYS software. The simulation results indicate that the chip cracks within 50 ms under the trigger current of 0.5 A when a circular groove with an area of 1 mm2 and depth of 0.1 mm is filled with an expansion material with an expansion coefficient of 10−5°C−1. Then, the author prepared a sample for experimental verification. Experimental results show that the sample chip quickly cracks and fails within 10 ms under the trigger current of 1 A. The simulation and experimental results confirm the feasibility of the structure in quick destruction, which lays the foundation for developing instantaneous-failure integrated circuit products to meet information security applications.
{"title":"Design, Simulation, and Experimental Verification of a Destruction Mechanism of Transient Electronic Devices","authors":"Yu Xiao, Zhengyuan Zhang, Xiyi Liao, F. Jiang, Yan Wang","doi":"10.1155/2020/8898943","DOIUrl":"https://doi.org/10.1155/2020/8898943","url":null,"abstract":"To quickly destroy electronic devices and ensure information security, a destruction mechanism of transient electronic devices was designed in this paper. By placing the Ni-Cr film resistance and the energetic material between the chip and the package and heating the resistance by an electric current, the energetic material expanded and the chip cracked. The information on the chip was destroyed. The author simulated the temperature distribution and stress of the power-on structure in different sizes by ANSYS software. The simulation results indicate that the chip cracks within 50 ms under the trigger current of 0.5 A when a circular groove with an area of 1 mm2 and depth of 0.1 mm is filled with an expansion material with an expansion coefficient of 10−5°C−1. Then, the author prepared a sample for experimental verification. Experimental results show that the sample chip quickly cracks and fails within 10 ms under the trigger current of 1 A. The simulation and experimental results confirm the feasibility of the structure in quick destruction, which lays the foundation for developing instantaneous-failure integrated circuit products to meet information security applications.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":"1 1","pages":""},"PeriodicalIF":0.4,"publicationDate":"2020-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42530712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Thorough investigations of the low-frequency noise (LFN) in a fully depleted silicon-on-insulator technology node have been accomplished, pointing out on the contribution of the buried oxide (BOX) and the Si-BOX interface to the total drain current noise level. A new analytical multilayer gate stack flat-band voltage fluctuation-based model has been established, and 2D numerical simulations have been carried out to identify the main noise sources and related parameters on which the LFN depends. The increase of the noise at strong inversion could be explained by the access resistance contribution to the 1/f noise. Therefore, considering uncorrelated noise sources in the channel and in the source/drain regions, the total low-frequency noise can simply be obtained by adding to the channel noise the contribution of the excess noise originating from the access region (Δr). Moreover, only two fit parameters are used in this work: the trap volumetric density in the BOX, and the 1/f access noise level originating from the access series resistance, which is assumed to be the same for the front and the back interfaces.
{"title":"Semianalytical Modelling and 2D Numerical Simulation of Low-Frequency Noise in Advanced N-Channel FDSOI MOSFETs","authors":"T. Boutchacha, G. Ghibaudo","doi":"10.1155/2020/7989238","DOIUrl":"https://doi.org/10.1155/2020/7989238","url":null,"abstract":"Thorough investigations of the low-frequency noise (LFN) in a fully depleted silicon-on-insulator technology node have been accomplished, pointing out on the contribution of the buried oxide (BOX) and the Si-BOX interface to the total drain current noise level. A new analytical multilayer gate stack flat-band voltage fluctuation-based model has been established, and 2D numerical simulations have been carried out to identify the main noise sources and related parameters on which the LFN depends. The increase of the noise at strong inversion could be explained by the access resistance contribution to the 1/f noise. Therefore, considering uncorrelated noise sources in the channel and in the source/drain regions, the total low-frequency noise can simply be obtained by adding to the channel noise the contribution of the excess noise originating from the access region (Δr). Moreover, only two fit parameters are used in this work: the trap volumetric density in the BOX, and the 1/f access noise level originating from the access series resistance, which is assumed to be the same for the front and the back interfaces.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":" ","pages":""},"PeriodicalIF":0.4,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43483885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kosumo Matsui, K. Komurasaki, Waku Hatakeyama, K. Shimamura, Kohei Fujiwara, Hidehiko Yamaoka
Wireless power transfer (WPT) is one solution to realize long flight times and accommodate various missions of micro-uncrewed aerial vehicles (MAVs). Reducing the constraint of power transmission distance and realizing high beam efficiency are possible because of the high directivity of WPT using millimeter wave (MMW) methods. Nevertheless, no report of the relevant literature describes an investigation of sending power to an MAV using MMW because MMW rectennas have low efficiency. The purpose of our study is to conduct fundamental research of a high-efficiency and high-power rectenna at 94 GHz aimed at MAV application using MMW. As described herein, we developed and evaluated a 100-mW-class single-diode rectifier at 94 GHz with a finline of a waveguide (WG) to a microstrip-line (MSL) transducer. With the optimum load of 150 Ω at input power of 128 mW, the output DC power and rectifying efficiency were obtained respectively as 41.7 mW and 32.5%. By comparison to an earlier study, measurement of 94 GHz rectifiers under high power input becomes more accurate through this study.
{"title":"Development of a 100 mW-Class 94 GHz High-Efficiency Single-Series Rectifier Feed by Finline for Micro-UAV Application","authors":"Kosumo Matsui, K. Komurasaki, Waku Hatakeyama, K. Shimamura, Kohei Fujiwara, Hidehiko Yamaoka","doi":"10.1155/2020/4072325","DOIUrl":"https://doi.org/10.1155/2020/4072325","url":null,"abstract":"Wireless power transfer (WPT) is one solution to realize long flight times and accommodate various missions of micro-uncrewed aerial vehicles (MAVs). Reducing the constraint of power transmission distance and realizing high beam efficiency are possible because of the high directivity of WPT using millimeter wave (MMW) methods. Nevertheless, no report of the relevant literature describes an investigation of sending power to an MAV using MMW because MMW rectennas have low efficiency. The purpose of our study is to conduct fundamental research of a high-efficiency and high-power rectenna at 94 GHz aimed at MAV application using MMW. As described herein, we developed and evaluated a 100-mW-class single-diode rectifier at 94 GHz with a finline of a waveguide (WG) to a microstrip-line (MSL) transducer. With the optimum load of 150 Ω at input power of 128 mW, the output DC power and rectifying efficiency were obtained respectively as 41.7 mW and 32.5%. By comparison to an earlier study, measurement of 94 GHz rectifiers under high power input becomes more accurate through this study.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":"2020 1","pages":"1-8"},"PeriodicalIF":0.4,"publicationDate":"2020-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2020/4072325","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47459571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The calculation and design of an ultralow-power Low Noise Amplifier (LNA) are proposed in this paper. The LNA operates from 5 GHz to 10 GHz, and forward body biasing technique is used to bring down power consumption of the circuit. The design revolves around precise calculations related to input impedance, output impedance, and the gain of the circuit. MATLAB and Advanced Design System (ADS) are utilized to design and simulate the LNA. In addition, TSMC 0.13 μm CMOS process is used in ADS. The LNA is biased with two different voltage supplies in order to reduce power consumption. Noise Figure (NF), input matching (S11), gain (S21), IIP3, and power dissipation are 1.46 dB–2.27 dB, −11.25 dB, 13.82 dB, −8.5, and 963 μW, respectively.
{"title":"The Design of an Ultralow-Power Ultra-wideband (5 GHz–10 GHz) Low Noise Amplifier in 0.13 μm CMOS Technology","authors":"Hemad Heidari Jobaneh","doi":"10.1155/2020/8537405","DOIUrl":"https://doi.org/10.1155/2020/8537405","url":null,"abstract":"The calculation and design of an ultralow-power Low Noise Amplifier (LNA) are proposed in this paper. The LNA operates from 5 GHz to 10 GHz, and forward body biasing technique is used to bring down power consumption of the circuit. The design revolves around precise calculations related to input impedance, output impedance, and the gain of the circuit. MATLAB and Advanced Design System (ADS) are utilized to design and simulate the LNA. In addition, TSMC 0.13 μm CMOS process is used in ADS. The LNA is biased with two different voltage supplies in order to reduce power consumption. Noise Figure (NF), input matching (S11), gain (S21), IIP3, and power dissipation are 1.46 dB–2.27 dB, −11.25 dB, 13.82 dB, −8.5, and 963 μW, respectively.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":"2020 1","pages":"1-12"},"PeriodicalIF":0.4,"publicationDate":"2020-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2020/8537405","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41390879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An ease of four-port dual-mode diplexer with high signal isolation is presented. A compact dual-mode diplexer with high signal isolation between the Rx and Tx modules is achievable by only using one resonator filter topology. Two back-to-back dual-mode diplexers have a 180° phase shift in one branch. The high isolation can be achieved by amplitude and phase cancellation technique. The delayed transmission line can be easily achieved by the phase shifter. The simulated and measured four-port dual-mode diplexers are designed at the centre frequency of Rx/Tx at 1.95 GHz and 2.14 GHz, respectively. The measured results of Rx/Tx dual-mode diplexer devices are presented with 47.1 dB Rx/Tx isolation. This four-port dual-mode diplexer achieves the isolation (S32) of more than 24.1 dB when compared with the conventional three-port dual-mode diplexer structure.
提出了一种易于实现的高信号隔离度四端口双模双工器。通过仅使用一个谐振器滤波器拓扑结构，可以实现Rx和Tx模块之间具有高信号隔离的紧凑型双模双工器。两个背靠背双模双工器在一个支路中具有180°相移。高隔离可以通过幅度和相位消除技术来实现。延迟传输线可以通过移相器容易地实现。模拟和测量的四端口双模双工器是在1.95的Rx/Tx中心频率下设计的 GHz和2.14 GHz。Rx/Tx双模双工器器件的测量结果为47.1 dB Rx/Tx隔离。该四端口双模双工器实现了24.1以上的隔离（S32） dB。
{"title":"Four-Port Dual-Mode Diplexer with High Signal Isolation","authors":"J. Konpang, Natchayathorn Wattikornsirikul","doi":"10.1155/2020/4032673","DOIUrl":"https://doi.org/10.1155/2020/4032673","url":null,"abstract":"An ease of four-port dual-mode diplexer with high signal isolation is presented. A compact dual-mode diplexer with high signal isolation between the Rx and Tx modules is achievable by only using one resonator filter topology. Two back-to-back dual-mode diplexers have a 180° phase shift in one branch. The high isolation can be achieved by amplitude and phase cancellation technique. The delayed transmission line can be easily achieved by the phase shifter. The simulated and measured four-port dual-mode diplexers are designed at the centre frequency of Rx/Tx at 1.95 GHz and 2.14 GHz, respectively. The measured results of Rx/Tx dual-mode diplexer devices are presented with 47.1 dB Rx/Tx isolation. This four-port dual-mode diplexer achieves the isolation (S32) of more than 24.1 dB when compared with the conventional three-port dual-mode diplexer structure.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":"2020 1","pages":"1-5"},"PeriodicalIF":0.4,"publicationDate":"2020-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2020/4032673","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45212299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
LDMOS devices with grounded gate shield structures variations were simulated and tested, aiming to address hot carrier immunity and robustness concurrently. Optimal configuration of grounded gate shield structure was found to reduce local electrical field strength at gate-to-drain overlap for better hot carrier immunity, and to achieve uniform E-field distribution on drain side for robustness as well. Design trade off of hot carrier immunity (HCI) and robustness is analyzed by simulation and silicon data.
{"title":"Design Tradeoff of Hot Carrier Immunity and Robustness in LDMOS with Grounded Gate Shield","authors":"Haifeng Mo, Yaohui Zhang, Helun Song","doi":"10.1155/2019/1928494","DOIUrl":"https://doi.org/10.1155/2019/1928494","url":null,"abstract":"LDMOS devices with grounded gate shield structures variations were simulated and tested, aiming to address hot carrier immunity and robustness concurrently. Optimal configuration of grounded gate shield structure was found to reduce local electrical field strength at gate-to-drain overlap for better hot carrier immunity, and to achieve uniform E-field distribution on drain side for robustness as well. Design trade off of hot carrier immunity (HCI) and robustness is analyzed by simulation and silicon data.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":"2019 1","pages":"1-8"},"PeriodicalIF":0.4,"publicationDate":"2019-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2019/1928494","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46502022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposed a logic synthesis method based on binary decision diagram (BDD) representation. The proposed method is optimized for dual-threshold independent-gate (DTIG) FinFET circuits. The algorithm of the BDD-based topology optimization is stated in detail. Some kinds of feature subgraph structures of a BDD are extracted by the extraction algorithm and then fed to mapping algorithm to get a final optimized circuit based on predefined DTIG FinFET logic gates. Some MCNC benchmark circuits are tested under the proposed synthesis method by comparing with ABC, DC tools. The simulations show that the proposed synthesis method can obtain performance improvement for DTIG FinFET circuits.
{"title":"BDD-Based Topology Optimization for Low-Power DTIG FinFET Circuits","authors":"H. Ni, Jianping Hu, Xuqiang Zhang, Haotian Zhu","doi":"10.1155/2019/8292653","DOIUrl":"https://doi.org/10.1155/2019/8292653","url":null,"abstract":"This paper proposed a logic synthesis method based on binary decision diagram (BDD) representation. The proposed method is optimized for dual-threshold independent-gate (DTIG) FinFET circuits. The algorithm of the BDD-based topology optimization is stated in detail. Some kinds of feature subgraph structures of a BDD are extracted by the extraction algorithm and then fed to mapping algorithm to get a final optimized circuit based on predefined DTIG FinFET logic gates. Some MCNC benchmark circuits are tested under the proposed synthesis method by comparing with ABC, DC tools. The simulations show that the proposed synthesis method can obtain performance improvement for DTIG FinFET circuits.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":" ","pages":""},"PeriodicalIF":0.4,"publicationDate":"2019-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2019/8292653","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48856333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper discusses linearity and robustness together for the first time, disclosing a way to improve them. It reveals that the nonlinear transconductance with device working at quasi-saturation region is significant factor of device linearity. The peak electric field is the root cause of electron velocity saturation. The high electric field at the drift region near the drain will cause more electron-hole pairs generated to trigger the parasitic NPN transistor turn-on, which may cause failure of device. Devices with different drift region doping are simulated with TCAD and measured. With LDD4 doping, the peak electric field in the drift region is reduced; the linear region of the transconductance is broadened. The adjacent channel power ratio is decreased by 2 dBc; 12% more power can be discharged before the NPN transistor turn-on, indicating a better linearity and robustness.
{"title":"Improving Linearity and Robustness of RF LDMOS by Mitigating Quasi-Saturation Effect","authors":"Haifeng Mo, Yaohui Zhang, Helun Song","doi":"10.1155/2019/8425198","DOIUrl":"https://doi.org/10.1155/2019/8425198","url":null,"abstract":"This paper discusses linearity and robustness together for the first time, disclosing a way to improve them. It reveals that the nonlinear transconductance with device working at quasi-saturation region is significant factor of device linearity. The peak electric field is the root cause of electron velocity saturation. The high electric field at the drift region near the drain will cause more electron-hole pairs generated to trigger the parasitic NPN transistor turn-on, which may cause failure of device. Devices with different drift region doping are simulated with TCAD and measured. With LDD4 doping, the peak electric field in the drift region is reduced; the linear region of the transconductance is broadened. The adjacent channel power ratio is decreased by 2 dBc; 12% more power can be discharged before the NPN transistor turn-on, indicating a better linearity and robustness.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":" ","pages":""},"PeriodicalIF":0.4,"publicationDate":"2019-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2019/8425198","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43390309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zhaopeng Wei, G. Jacquemod, Y. Leduc, E. Foucauld, J. Prouvée, B. Blampey
Analog integrated circuits never follow the Moore’s Law. This is particularly right for passive component. Due to the Short Channel Effect, we have to implement longer transistor, especially for analog cell. In this paper, we propose a new topology using some advantages of the FDSOI (Fully Depleted Silicon on Insulator) technology in order to reduce the size of analog cells. First, a current mirror was chosen to illustrate and validate a new design. Measured currents, with 35nm transistor length, have validated our new cross-coupled back-gate topology. Then, a VCRO (Voltage Controlled Ring Oscillator) based on complementary inverter is also used to remove passive components reducing the size of the circuit.
{"title":"Reducing the Short Channel Effect of Transistors and Reducing the Size of Analog Circuits","authors":"Zhaopeng Wei, G. Jacquemod, Y. Leduc, E. Foucauld, J. Prouvée, B. Blampey","doi":"10.1155/2019/4578501","DOIUrl":"https://doi.org/10.1155/2019/4578501","url":null,"abstract":"Analog integrated circuits never follow the Moore’s Law. This is particularly right for passive component. Due to the Short Channel Effect, we have to implement longer transistor, especially for analog cell. In this paper, we propose a new topology using some advantages of the FDSOI (Fully Depleted Silicon on Insulator) technology in order to reduce the size of analog cells. First, a current mirror was chosen to illustrate and validate a new design. Measured currents, with 35nm transistor length, have validated our new cross-coupled back-gate topology. Then, a VCRO (Voltage Controlled Ring Oscillator) based on complementary inverter is also used to remove passive components reducing the size of the circuit.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":" ","pages":""},"PeriodicalIF":0.4,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2019/4578501","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46052153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Retracted: Design of a Narrow Bandwidth Bandpass Filter Using Compact Spiral Resonator with Chirality","authors":"","doi":"10.1155/2019/7262158","DOIUrl":"https://doi.org/10.1155/2019/7262158","url":null,"abstract":"","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":" ","pages":""},"PeriodicalIF":0.4,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2019/7262158","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43623636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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