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Reconfigurable Mixed Mode Universal Filter 可重构混合模式通用滤波器
IF 0.4 Q3 Engineering Pub Date : 2014-10-20 DOI: 10.1155/2014/769198
N. Afzal, Devesh Singh
This paper presents a novel mixed mode universal filter configuration capable of working in voltage and transimpedance mode. The proposed single filter configuration can be reconfigured digitally to realize all the five second order filter functions (types) at single output port. Other salient features of proposed configuration include independently programmable filter parameters, full cascadability, and low sensitivity figure. However, all these features are provided at the cost of quite large number of active elements. It needs three digitally programmable current feedback amplifiers and three digitally programmable current conveyors. Use of six active elements is justified by introducing three additional reduced hardware mixed mode universal filter configurations and its comparison with reported filters.
本文提出了一种新的混合模式通用滤波器结构,能够工作在电压和跨阻模式下。所提出的单滤波器配置可以数字化地重新配置,以实现在单个输出端口上的所有五种二阶滤波器功能(类型)。所提出的配置的其他显著特征包括独立可编程的滤波器参数,全级联性和低灵敏度数字。然而,所有这些功能都是以大量活动元素为代价提供的。它需要三个数字可编程电流反馈放大器和三个数字可编程电流传送带。通过介绍三种额外的简化硬件混合模式通用滤波器配置及其与已有滤波器的比较,证明使用六个有源元件是合理的。
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引用次数: 4
Sinusoidal Generator with π/4-Shifted Four/Eight Voltage Outputs Employing Four Grounded Components and Two/Six Active Elements 具有π/4移位的4 / 8电压输出的正弦发生器,采用四个接地元件和两个/六个有源元件
IF 0.4 Q3 Engineering Pub Date : 2014-08-28 DOI: 10.1155/2014/480590
S. Maheshwari
This paper presents a new circuit proposal for multiphase sine-wave generation, employing two active elements and four grounded passive elements. The proposed oscillator provides four 45° phase-shifted voltage outputs. Incorporation of additional inverters for generation of eight-phase outputs is further shown. Simultaneous current outputs can also be generated with additional output stages. The compact circuit structure is studied for nonideal and parasitic effects and simulation results are given, which are in good agreement with the theory. The utility of the proposal for π/4-QPSK generation is explored as an interesting application example with supporting results.
本文提出了一种采用两个有源元件和四个接地无源元件产生多相正弦波的新电路方案。所提出的振荡器提供4个45°相移电压输出。合并额外的逆变器产生八相输出进一步显示。同时的电流输出也可以产生额外的输出级。研究了紧凑电路结构对非理想效应和寄生效应的影响,并给出了仿真结果,与理论结果吻合较好。作为一个有趣的应用实例,本文探讨了该方法在π/4-QPSK生成中的应用。
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引用次数: 12
Implementation of Power Efficient Flash Analogue-to-Digital Converter 节能型闪存模数转换器的实现
IF 0.4 Q3 Engineering Pub Date : 2014-08-14 DOI: 10.1155/2014/723053
T. Lakshmi, Avireni Srinivasulu, P. C. Shaker
An efficient low power high speed 5-bit 5-GS/s flash analogue-to-digital converter (ADC) is proposed in this paper. The designing of a thermometer code to binary code is one of the exacting issues of low power flash ADC. The embodiment consists of two main blocks, a comparator and a digital encoder. To reduce the metastability and the effect of bubble errors, the thermometer code is converted into the gray code and there after translated to binary code through encoder. The proposed encoder is thus implemented by using differential cascade voltage switch logic (DCVSL) to maintain high speed and low power dissipation. The proposed 5-bit flash ADC is designed using Cadence 180 nm CMOS technology with a supply rail voltage typically ±0.85 V. The simulation results include a total power dissipation of 46.69 mW, integral nonlinearity (INL) value of −0.30 LSB and differential nonlinearity (DNL) value of −0.24 LSB, of the flash ADC.
提出了一种高效的低功耗高速5位5-GS/s闪存模数转换器(ADC)。温度计码转换成二进制码的设计是低功耗闪存ADC的难点之一。实施例包括两个主要块、比较器和数字编码器。为了减少亚稳态和气泡误差的影响,将温度计码转换为灰度码,再通过编码器转换为二进制码。因此,该编码器采用差分级联电压开关逻辑(DCVSL)实现,以保持高速度和低功耗。所提出的5位闪存ADC采用Cadence 180 nm CMOS技术设计,电源轨电压通常为±0.85 V。仿真结果表明,flash ADC的总功耗为46.69 mW,积分非线性(INL)值为−0.30 LSB,微分非线性(DNL)值为−0.24 LSB。
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引用次数: 11
Y-Function Analysis of the Low Temperature Behavior of Ultrathin Film FD SOI MOSFETs 超薄膜FD SOI mosfet低温行为的y函数分析
IF 0.4 Q3 Engineering Pub Date : 2014-06-11 DOI: 10.1155/2014/697369
A. Karsenty, A. Chelly
The respective transfer characteristics of the ultrathin body (UTB) and gate recessed channel (GRC) device, sharing same W/L ratio but having a channel thickness of 46 nm, and 2.2 nm respectively, were measured at 300 K and at 77 K. By decreasing the temperature we found that the electrical behaviors of these devices were radically opposite: if for UTB device, the conductivity was increased, the opposite effect was observed for GRC. The low field electron mobility and series resistance values were extracted using a method based on Y-function for both the temperatures. If low values were found for UTB, very high values (g1) were extracted for GRC. Surprisingly, for the last device, the effective field mobility is found very low (l1) and is decreasing by lowering the temperature. After having discussed the limits of this analysis.This case study illustrates the advantage of the Y-analysis in discriminating a parameter of great relevance for nanoscale devices and gives a coherent interpretation of an anomalous electrical behavior.
在300 K和77 K温度下,测量了具有相同W/L比、通道厚度分别为46 nm和2.2 nm的超薄体(UTB)和栅极凹槽沟道(GRC)器件的传递特性。通过降低温度,我们发现这些器件的电学行为完全相反:如果对于UTB器件,电导率增加,则对于GRC器件观察到相反的效果。利用基于y函数的方法提取了两种温度下的低场电子迁移率和串联电阻值。如果发现UTB值较低,则提取GRC值非常高(g1)。令人惊讶的是,对于最后一个器件,发现有效场迁移率非常低(l1),并且随着温度的降低而降低。在讨论了这种分析的局限性之后。本案例研究说明了y分析在鉴别与纳米级器件非常相关的参数方面的优势,并给出了异常电行为的连贯解释。
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引用次数: 2
A Novel Power Electronic Inverter Circuit for Transformerless Photovoltaic Systems 一种新型无变压器光伏系统电力电子逆变电路
IF 0.4 Q3 Engineering Pub Date : 2014-05-26 DOI: 10.1155/2014/329043
Cao Hai-yan
Capacitive leakage current is one of the most important issues for transformerless photovoltaic systems. In order to deal with the capacitive leakage current, a new power electronic inverter circuit is proposed in this paper. The inverter circuit consists of six switches and operates with constant common mode voltage. Theoretical analysis is conducted to clarify the circuit operation principle and the common mode characteristic. The performance evaluation test is carried out, and test results demonstrate that the capacitive leakage current can be significantly minimized with the proposed power electronic inverter circuit.
电容漏电流是无变压器光伏系统的重要问题之一。为了处理电容漏电流,本文提出了一种新的电力电子逆变电路。逆变电路由六个开关组成,以恒定的共模电压工作。通过理论分析,阐明了电路的工作原理和共模特性。进行了性能评估测试,测试结果表明,所提出的电力电子逆变电路可以显著降低电容漏电流。
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引用次数: 1
Active Comb Filter Using Operational Transconductance Amplifier 使用运算跨导放大器的有源梳状滤波器
IF 0.4 Q3 Engineering Pub Date : 2014-05-22 DOI: 10.1155/2014/587932
R. Ranjan, Surya Prasanna Yalla, Shubham Sorya, S. K. Paul
A new approach for the design of an active comb filter is proposed to remove the selected frequencies of various signals. The proposed filter is based on only OTAs and capacitors, hence suitable for monolithic integrated circuit implementation. The workability of the circuit is tested using PSPICE for test signals of 60, 180, 300, and 420 Hz as in ECG signal. The results are given in the paper and found to agree well with theory.
提出了一种设计有源梳状滤波器的新方法,以去除各种信号的选定频率。所提出的滤波器仅基于ota和电容器,因此适合于单片集成电路实现。采用PSPICE测试了60hz、180hz、300hz和420hz的心电信号,测试了电路的可操作性。文中给出了计算结果,结果与理论吻合较好。
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引用次数: 15
Design of a 2 GHz Linear-in-dB Variable-Gain Amplifier with 80-dB Gain Range 增益范围为80db的2 GHz线性db可变增益放大器的设计
IF 0.4 Q3 Engineering Pub Date : 2014-04-17 DOI: 10.1155/2014/434189
Zhengyu Sun, Yuepeng Yan
A broadband linear-in-dB variable-gain amplifier (VGA) circuit is implemented in 0.18 μm SiGe BiCMOS process. The VGA comprises two cascaded variable-gain core, in which a hybrid current-steering current gain cell is inserted in the Cherry-Hooper amplifier to maintain a broad bandwidth while covering a wide gain range. Postlayout simulation results confirm that the proposed circuit achieves a 2 GHz 3-dB bandwidth with wide linear-in-dB gain tuning range from −19 dB up to 61 dB. The amplifier offers a competitive gain bandwidth product of 2805 GHz at the maximum gain for a 110-GHz ft BiCMOS technology. The amplifier core consumes 31 mW from a 3.3 V supply and occupies active area of 280 μm by 140 μm.
采用0.18 μm SiGe BiCMOS工艺实现了宽带线性- db可变增益放大器(VGA)电路。VGA包括两个级联可变增益核心,其中在Cherry-Hooper放大器中插入混合电流转向电流增益单元,以保持宽带宽,同时覆盖宽增益范围。布局后仿真结果证实,该电路实现了2 GHz的3db带宽,具有从- 19 dB到61 dB的宽线性增益调谐范围。该放大器在110 GHz ft BiCMOS技术的最大增益下提供具有竞争力的2805 GHz增益带宽产品。放大器芯在3.3 V电源下消耗31mw,占用280 μm × 140 μm的有效面积。
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引用次数: 0
Harmonic-Rejection Compact Bandpass Filter Using Defected Ground Structure for GPS Application 基于缺陷接地结构的抗谐波紧凑带通滤波器在GPS中的应用
IF 0.4 Q3 Engineering Pub Date : 2014-04-03 DOI: 10.1155/2014/436964
Haiwen Liu, Baoping Ren, Xiang Xiao, Zhi‐Chong Zhang, Shen Li, Suping Peng
A miniaturized bandpass filter (BPF) using defected ground structure (DGS) resonator with the characteristic of harmonic rejection is developed in this paper. The second and third harmonics of the proposed BPF are rejected by the characteristic of stepped-impedance DGS resonator. Moreover, open stubs are established so that two adjustable transmission zeros can independently be created to extend the stopband and improve the rejection level. Finally, a second-order BPF, centered at 1.62 GHz with a stopband extended up to 5.6 GHz and a rejection level better than 20 dB, is designed and implemented for GPS application. A good agreement between simulation and measurement verifies the validity of this design methodology.
研制了一种采用具有谐波抑制特性的缺陷接地结构(DGS)谐振腔的小型化带通滤波器。利用阶跃阻抗DGS谐振器的特性,抑制了BPF的二次和三次谐波。此外,还建立了开路存根,从而可以独立创建两个可调传输零点,以延长阻带,提高抑制水平。最后,设计并实现了一种以1.62 GHz为中心,阻带扩展至5.6 GHz,抑制电平优于20 dB的二阶BPF,用于GPS应用。仿真结果与实测结果吻合良好,验证了该设计方法的有效性。
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引用次数: 9
New Realizations of Single OTRA-Based Sinusoidal Oscillators 基于单otra的正弦振荡器的新实现
IF 0.4 Q3 Engineering Pub Date : 2014-03-10 DOI: 10.1155/2014/938987
Hung-Chun Chien
This study proposes three new sinusoidal oscillators based on an operational transresistance amplifier (OTRA). Each of the proposed oscillator circuits consists of one OTRA combined with a few passive components. The first circuit is an OTRA-based minimum RC oscillator. The second circuit is capable of providing independent control on the condition of oscillation without affecting the oscillation frequency. The third circuit exhibits independent control of oscillation frequency through a capacitor. This study first introduces the OTRA and the related formulations of the proposed oscillator circuits, and then discusses the nonideal effects, sensitivity analyses, and frequency stability of the presented circuits. The proposed oscillators exhibit low sensitivities and good frequency stability. Because the presented circuits feature low impedance output, they can be connected directly to the next stage without cascading additional voltage buffers. HSPICE simulations and experimental results confirm the feasibility of the new oscillator circuits.
本文提出了三种基于运算跨阻放大器(OTRA)的新型正弦振荡器。所提出的每个振荡器电路由一个OTRA和几个无源元件组成。第一个电路是基于otra的最小RC振荡器。第二电路能够在不影响振荡频率的情况下对振荡条件提供独立控制。第三个电路通过电容显示振荡频率的独立控制。本研究首先介绍了OTRA和所提振荡器电路的相关公式,然后讨论了所提电路的非理想效应、灵敏度分析和频率稳定性。该振荡器具有低灵敏度和良好的频率稳定性。由于所提出的电路具有低阻抗输出,它们可以直接连接到下一级,而无需级联额外的电压缓冲器。HSPICE仿真和实验结果证实了该振荡器电路的可行性。
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引用次数: 21
Signal Integrity Analysis in Carbon Nanotube Based Through-Silicon Via 基于碳纳米管的硅通孔信号完整性分析
IF 0.4 Q3 Engineering Pub Date : 2014-03-02 DOI: 10.1155/2014/524107
M. Majumder, Archana Kumari, B. Kaushik, S. Manhas
Development of a reliable 3D integrated system is largely dependent on the choice of filler materials used in through-silicon vias (TSVs). This research paper presents carbon nanotube (CNT) bundles as prospective filler materials for TSVs and provides an analysis of signal integrity for different single- (SWCNT), double- (DWCNT), and multi-walled CNT (MWCNT) bundle based TSVs. Depending on the physical configuration of a pair of TSVs, an equivalent electrical model is employed to analyze the in-phase and out-phase delays. It is observed that, using an MWCNT bundle (with number of shells = 10), the overall in-phase delays are reduced by 96.86%, 92.33%, 78.35%, and 32.72% compared to the bundled SWCNT, DWCNT, 4-shell MWCNT, and 8-shell MWCNT, respectively; similarly, the overall reduction in out-phase delay is 85.89%, 73.38%, 45.92%, and 12.56%, respectively.
可靠的3D集成系统的开发在很大程度上取决于硅通孔(tsv)中填充材料的选择。本文提出了碳纳米管束作为tsv的潜在填充材料,并分析了不同单壁(SWCNT)、双壁(DWCNT)和多壁碳纳米管束(MWCNT) tsv的信号完整性。根据tsv对的物理结构,采用等效电学模型分析了tsv对的相内和相外延迟。研究发现,与捆绑的SWCNT、DWCNT、4壳MWCNT和8壳MWCNT相比,使用MWCNT束(壳数= 10),总体同相延迟分别减少了96.86%、92.33%、78.35%和32.72%;同样,整体的外相延迟降低率分别为85.89%、73.38%、45.92%和12.56%。
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引用次数: 5
期刊
Active and Passive Electronic Components
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