Pub Date : 2007-12-26DOI: 10.1109/EMICC.2007.4412658
B. Benbakhti, M. Rousseau, A. Soltani, J. Laureyns, J. De Jaeger
For power applications, the dissipated power in GaN based devices becomes very significant and consequently can generate a very important self-heating effect in the component. The self-heating in the device increases considerably the lattice or the operating temperature and the transport properties are then degraded. To explain and to understand the physical phenomena observed in experiment for power components, it requires to introduce heating effects. The goal of this study is to estimate self-heating effects on the static characteristics of TLM (Transmission Line Model) AlGaN/GaN structures. For this objective, a developed physical thermal model is used in order to study the electrical and thermal phenomena in a coupled way. These studies are validated by electrical measurements regarding I-V characteristics and also by optic measurements using micro-Raman spectroscopy.
{"title":"Thermal behaviour of gate-less AlGaN/GaN heterostructures","authors":"B. Benbakhti, M. Rousseau, A. Soltani, J. Laureyns, J. De Jaeger","doi":"10.1109/EMICC.2007.4412658","DOIUrl":"https://doi.org/10.1109/EMICC.2007.4412658","url":null,"abstract":"For power applications, the dissipated power in GaN based devices becomes very significant and consequently can generate a very important self-heating effect in the component. The self-heating in the device increases considerably the lattice or the operating temperature and the transport properties are then degraded. To explain and to understand the physical phenomena observed in experiment for power components, it requires to introduce heating effects. The goal of this study is to estimate self-heating effects on the static characteristics of TLM (Transmission Line Model) AlGaN/GaN structures. For this objective, a developed physical thermal model is used in order to study the electrical and thermal phenomena in a coupled way. These studies are validated by electrical measurements regarding I-V characteristics and also by optic measurements using micro-Raman spectroscopy.","PeriodicalId":436391,"journal":{"name":"2007 European Microwave Integrated Circuit Conference","volume":"215 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131963018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-12-26DOI: 10.1109/EMICC.2007.4412689
G. Vandersteen, L. Bos, P. Dobrovolný
Various design methodologies for common-source low noise amplifiers (LNAs) in Si CMOS technologies were proposed in the past. These start from long-channel assumptions to derive analytic design equations. This paper compares the various existing LNA design methodologies and verifies the long-channel assumptions using a commercial. 13 mum CMOS technology. After demonstrating that the design assumptions are no longer valid, a new methodology is proposed which enables the LNA design in a systematic way, without the drawback that it is relying on a particular transistor model for computing the input impedance and the noise figure. This makes the proposed technique robust to transistor model changes in future technology nodes.
过去提出了各种基于硅CMOS技术的共源低噪声放大器(LNAs)的设计方法。这些从长通道假设出发，推导出解析设计方程。本文比较了现有的各种LNA设计方法，并使用商业模型验证了长信道假设。13 μ m CMOS技术。在证明设计假设不再有效之后，提出了一种新的方法，使LNA设计能够以系统的方式进行，而没有依赖于特定晶体管模型来计算输入阻抗和噪声系数的缺点。这使得所提出的技术对未来技术节点的晶体管模型变化具有鲁棒性。
{"title":"Scaling friendly design methodology for inductively-degenerated RF low-noise amplifiers","authors":"G. Vandersteen, L. Bos, P. Dobrovolný","doi":"10.1109/EMICC.2007.4412689","DOIUrl":"https://doi.org/10.1109/EMICC.2007.4412689","url":null,"abstract":"Various design methodologies for common-source low noise amplifiers (LNAs) in Si CMOS technologies were proposed in the past. These start from long-channel assumptions to derive analytic design equations. This paper compares the various existing LNA design methodologies and verifies the long-channel assumptions using a commercial. 13 mum CMOS technology. After demonstrating that the design assumptions are no longer valid, a new methodology is proposed which enables the LNA design in a systematic way, without the drawback that it is relying on a particular transistor model for computing the input impedance and the noise figure. This makes the proposed technique robust to transistor model changes in future technology nodes.","PeriodicalId":436391,"journal":{"name":"2007 European Microwave Integrated Circuit Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130248867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-12-26DOI: 10.1109/EMICC.2007.4412690
Liu Liu, S. Chartier, A. Trasser, H. Schumacher
In this paper, we present a fully integrated differential, compact frequency divider with a divide ratio of 32. The circuit utilizes a Si/SiGe 0.25 mum BiCMOS technology and operates beyond 75 GHz. The divider has a die area of 655 mum times 475 mum and consumes 202 mA at 5 V supply voltage. The frequency divider consists of the first stage of a dynamic divider with transimpedance topology and a static divider for the following four stages. The dynamic frequency divider operates from 22 GHz to 93 GHz with 5 V voltage supply and consumes 35 mA current. The static frequency divider operates up to 50 GHz and consumes 43 mA.
{"title":"SiGe V-band 1:32 frequency divider using dynamic and static division stages","authors":"Liu Liu, S. Chartier, A. Trasser, H. Schumacher","doi":"10.1109/EMICC.2007.4412690","DOIUrl":"https://doi.org/10.1109/EMICC.2007.4412690","url":null,"abstract":"In this paper, we present a fully integrated differential, compact frequency divider with a divide ratio of 32. The circuit utilizes a Si/SiGe 0.25 mum BiCMOS technology and operates beyond 75 GHz. The divider has a die area of 655 mum times 475 mum and consumes 202 mA at 5 V supply voltage. The frequency divider consists of the first stage of a dynamic divider with transimpedance topology and a static divider for the following four stages. The dynamic frequency divider operates from 22 GHz to 93 GHz with 5 V voltage supply and consumes 35 mA current. The static frequency divider operates up to 50 GHz and consumes 43 mA.","PeriodicalId":436391,"journal":{"name":"2007 European Microwave Integrated Circuit Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126436395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The design and measurement results of a continuous amplitude/phase control CMOS MMIC are presented in this paper. This circuit uses the vector sum method to achieve continuous phase and amplitude control. The phase shifter demonstrates all continuous phase control and an insertion loss of 17 dB with 30-dB dynamic range from 40 to 75 GHz. The chip size is only 0.7 mm times 0.6 nm. To the best of the authors' knowledge, this circuit is the first demonstration of millimeter-wave phase shifters MMIC using the vector sum method, with the smallest chip size for all MMIC phase shifters and 360deg phase-control circuits in frequencies above 5 GHz reported to date.
本文介绍了一种连续幅相控制CMOS MMIC的设计和测量结果。该电路采用矢量和法实现连续相位和幅度控制。移相器具有全连续相位控制和17 dB的插入损耗，30 dB动态范围为40至75 GHz。芯片尺寸仅为0.7 mm × 0.6 nm。据作者所知，该电路是使用矢量和方法的毫米波移相器MMIC的第一个演示，迄今为止报道的频率高于5 GHz的所有MMIC移相器和360度相位控制电路的芯片尺寸最小。
{"title":"A 40-74 GHz amplitude/phase control MMIC using 90-nm CMOS technology","authors":"Pei-Si Wu, Hong-Yeh Chang, Ming-Fong Lei, Bo-Jr Huang, Huei Wang, Cheng-Ming Yu, J. Chern","doi":"10.1109/EMICC.2007.4412661","DOIUrl":"https://doi.org/10.1109/EMICC.2007.4412661","url":null,"abstract":"The design and measurement results of a continuous amplitude/phase control CMOS MMIC are presented in this paper. This circuit uses the vector sum method to achieve continuous phase and amplitude control. The phase shifter demonstrates all continuous phase control and an insertion loss of 17 dB with 30-dB dynamic range from 40 to 75 GHz. The chip size is only 0.7 mm times 0.6 nm. To the best of the authors' knowledge, this circuit is the first demonstration of millimeter-wave phase shifters MMIC using the vector sum method, with the smallest chip size for all MMIC phase shifters and 360deg phase-control circuits in frequencies above 5 GHz reported to date.","PeriodicalId":436391,"journal":{"name":"2007 European Microwave Integrated Circuit Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126397874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-12-26DOI: 10.1109/EMICC.2007.4412792
A. Sayed, G. Boeck
In this paper, a 1 MHz to 3.4 GHz, 5 W, highly linear power amplifier based on GaN HEMT is reported. Load-pull technique has been applied to introduce a compromising solution for the PA performance trade-off problem. Over the whole bandwidth a measured small signal gain of 14 plusmn 0.7 dB and an output return loss of better than -10 dB have been achieved. The input return loss was better than -10 dB up to 3 GHz. Power and linearity performances have been measured and compared to simulations resulting in a very good agreement. At a frequency spacing of 100 kHz, minimum values of output IP3 and output IP2 have been evaluated and found to be 48.5 dBm and 59.3 dBm. At 1 dB power compression point, minimum Pout, and Gp were found to be ges37.3 dBm and ges13.3 dB, respectively within the whole frequency band.
{"title":"5W Highly Linear GaN power amplifier with 3.4 GHz bandwidth","authors":"A. Sayed, G. Boeck","doi":"10.1109/EMICC.2007.4412792","DOIUrl":"https://doi.org/10.1109/EMICC.2007.4412792","url":null,"abstract":"In this paper, a 1 MHz to 3.4 GHz, 5 W, highly linear power amplifier based on GaN HEMT is reported. Load-pull technique has been applied to introduce a compromising solution for the PA performance trade-off problem. Over the whole bandwidth a measured small signal gain of 14 plusmn 0.7 dB and an output return loss of better than -10 dB have been achieved. The input return loss was better than -10 dB up to 3 GHz. Power and linearity performances have been measured and compared to simulations resulting in a very good agreement. At a frequency spacing of 100 kHz, minimum values of output IP3 and output IP2 have been evaluated and found to be 48.5 dBm and 59.3 dBm. At 1 dB power compression point, minimum Pout, and Gp were found to be ges37.3 dBm and ges13.3 dB, respectively within the whole frequency band.","PeriodicalId":436391,"journal":{"name":"2007 European Microwave Integrated Circuit Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126800045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-12-26DOI: 10.1109/EMICC.2007.4412662
Hao-Ming Chao, Chien-Lung Wang, Wen-Shen Wuen, K. Wen
This paper presents an active guarding circuit employing noise decoupling and inversion feedback for substrate noise suppression in high frequency up to GHz. Proposed inversion feedback circuit can efficiently suppress substrate noise up to GHz range by introducing a zero within an amplitude controller. The noise decoupling circuit not only provides a decoupling path, but also senses the noise level for the amplitude controller to perform noise cancellation. By applying the proposed active guarding circuit, the noise suppression of passive guard ring can be improved more than 14dB in the frequency range from DC to 1 GHz and 7.2 dB up to 5G Hz. For 1 dB degradation of noise suppression performance, the input noise level can be up to 90 mV at 1 MHz and 86 mV at 1 GHz, respectively.
{"title":"An active guarding circuit for giga-hertz substrate noise suppression","authors":"Hao-Ming Chao, Chien-Lung Wang, Wen-Shen Wuen, K. Wen","doi":"10.1109/EMICC.2007.4412662","DOIUrl":"https://doi.org/10.1109/EMICC.2007.4412662","url":null,"abstract":"This paper presents an active guarding circuit employing noise decoupling and inversion feedback for substrate noise suppression in high frequency up to GHz. Proposed inversion feedback circuit can efficiently suppress substrate noise up to GHz range by introducing a zero within an amplitude controller. The noise decoupling circuit not only provides a decoupling path, but also senses the noise level for the amplitude controller to perform noise cancellation. By applying the proposed active guarding circuit, the noise suppression of passive guard ring can be improved more than 14dB in the frequency range from DC to 1 GHz and 7.2 dB up to 5G Hz. For 1 dB degradation of noise suppression performance, the input noise level can be up to 90 mV at 1 MHz and 86 mV at 1 GHz, respectively.","PeriodicalId":436391,"journal":{"name":"2007 European Microwave Integrated Circuit Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134133158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-12-26DOI: 10.1109/EMICC.2007.4412633
R. van Dijk, L. de Boer, A. Megej, J. Hoogland, F.E. van Vlict
A driver amplifier for the ISM band around 60 GHz has been designed and tested. The amplifier has been designed in conjunction with other transceiver sub-systems in the 0.15 mum GaAs pHEMT process of UMS (PH15). The measurements show behaviour very well matched with the extensive circuit and field simulations. The amplifier is approx. 3 times 1.8 mm, consumes 910 mW, has a gain of 22 dB, a P-1 dB at the output of +14 dBm, and is well matched in the band 60-65 GHz.
{"title":"Driver amplifier for 60 GHz communication systems","authors":"R. van Dijk, L. de Boer, A. Megej, J. Hoogland, F.E. van Vlict","doi":"10.1109/EMICC.2007.4412633","DOIUrl":"https://doi.org/10.1109/EMICC.2007.4412633","url":null,"abstract":"A driver amplifier for the ISM band around 60 GHz has been designed and tested. The amplifier has been designed in conjunction with other transceiver sub-systems in the 0.15 mum GaAs pHEMT process of UMS (PH15). The measurements show behaviour very well matched with the extensive circuit and field simulations. The amplifier is approx. 3 times 1.8 mm, consumes 910 mW, has a gain of 22 dB, a P-1 dB at the output of +14 dBm, and is well matched in the band 60-65 GHz.","PeriodicalId":436391,"journal":{"name":"2007 European Microwave Integrated Circuit Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124651308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-12-26DOI: 10.1109/EMICC.2007.4412648
J. Rathmell, A. Parker
We present a novel and simple model of FET trapping based on a study of HEMTs using pulse techniques. This model accounts for the observed variation of extent of gate lag with bias and step potentials, and the variation of gate-lag time constant with drain potential. Because both charge capture and emission are accounted for, the model is appropriate for the simulation of both large-signal and small-signal dynamics. The model is verified by comparison with large-signal transient measurements and is consistent with small-signal gain measurements.
{"title":"Characterization and modeling of substrate trapping in HEMTs","authors":"J. Rathmell, A. Parker","doi":"10.1109/EMICC.2007.4412648","DOIUrl":"https://doi.org/10.1109/EMICC.2007.4412648","url":null,"abstract":"We present a novel and simple model of FET trapping based on a study of HEMTs using pulse techniques. This model accounts for the observed variation of extent of gate lag with bias and step potentials, and the variation of gate-lag time constant with drain potential. Because both charge capture and emission are accounted for, the model is appropriate for the simulation of both large-signal and small-signal dynamics. The model is verified by comparison with large-signal transient measurements and is consistent with small-signal gain measurements.","PeriodicalId":436391,"journal":{"name":"2007 European Microwave Integrated Circuit Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122991351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-12-26DOI: 10.1109/EMICC.2007.4412635
T. Kaho, Y. Yamaguchi, S. Nagamine, Y. Toriyama, T. Taniguchi, K. Uehara
A highly integrated quasi-millimeter wave receiver chip that integrates 22 circuits on a 3 x 2.3 mm chip using three-dimensional MMIC (3D-MMIC) technology is presented. The receiver MMIC operates with an LO signal in the 2.7-3.1 GHz range. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO chain, resulting in an IF center frequency of 2.4 GHz. It can use low-cost VCOs and demodulators in a 2-3 GHz frequency band. The power dissipation of the MMIC is only 450 mW. It also achieved low noise (3.4 dB) and high gain (41 dB) at 26 GHz. Furthermore, it achieved a high dynamic range using two step attenuators in the RF and IF frequency bands with a new built-in inverter using an N-channel depression FET.
{"title":"A highly integrated quasi-millimeter wave receiver chip using 3D-MMIC technology","authors":"T. Kaho, Y. Yamaguchi, S. Nagamine, Y. Toriyama, T. Taniguchi, K. Uehara","doi":"10.1109/EMICC.2007.4412635","DOIUrl":"https://doi.org/10.1109/EMICC.2007.4412635","url":null,"abstract":"A highly integrated quasi-millimeter wave receiver chip that integrates 22 circuits on a 3 x 2.3 mm chip using three-dimensional MMIC (3D-MMIC) technology is presented. The receiver MMIC operates with an LO signal in the 2.7-3.1 GHz range. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO chain, resulting in an IF center frequency of 2.4 GHz. It can use low-cost VCOs and demodulators in a 2-3 GHz frequency band. The power dissipation of the MMIC is only 450 mW. It also achieved low noise (3.4 dB) and high gain (41 dB) at 26 GHz. Furthermore, it achieved a high dynamic range using two step attenuators in the RF and IF frequency bands with a new built-in inverter using an N-channel depression FET.","PeriodicalId":436391,"journal":{"name":"2007 European Microwave Integrated Circuit Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129505710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-12-26DOI: 10.1109/EMICC.2007.4412781
Jiunn‐Nan Hwang, Fu‐Chiarng Chen
In this paper, the stability analysis of the Mur's first order absorbing boundary condition (ABQ in the alternating direction implicit finite-difference time-domain (ADI-FDTD) method is presented. To analysis the stability of this scheme, the amplification matrix is derived. The effect of wave propagation direction on the stability of this scheme is investigated. The numerical dispersion relation of this scheme is also derived analytically from the amplification matrix. From the theoretical stability analysis and numerical simulation, it is found that the Mur's first order ABC in the ADI-FDTD method will be unstable.
{"title":"Analysis of stability and numerical dispersion relation of mur's absorbing boundary condition in the ADI-FDTD method","authors":"Jiunn‐Nan Hwang, Fu‐Chiarng Chen","doi":"10.1109/EMICC.2007.4412781","DOIUrl":"https://doi.org/10.1109/EMICC.2007.4412781","url":null,"abstract":"In this paper, the stability analysis of the Mur's first order absorbing boundary condition (ABQ in the alternating direction implicit finite-difference time-domain (ADI-FDTD) method is presented. To analysis the stability of this scheme, the amplification matrix is derived. The effect of wave propagation direction on the stability of this scheme is investigated. The numerical dispersion relation of this scheme is also derived analytically from the amplification matrix. From the theoretical stability analysis and numerical simulation, it is found that the Mur's first order ABC in the ADI-FDTD method will be unstable.","PeriodicalId":436391,"journal":{"name":"2007 European Microwave Integrated Circuit Conference","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124993663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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