Macropore silicon etching with photo-electro-chemistry was carried out under different experimental conditions, including etching voltage, current density and wave length of optical source et al. The surface, diameter of pore and wall of the macropore silicon were observed with Scanning Electronic Microscope (SEM) and Metallographic Microscope. The influencing factors on morphology of pore were analyzed. Experimental parameters for fabricating high properties macropore silicon were also determined. Macropore silicon with depth of pores up to 300 ¿m and aspect ratios more than 75 was etched with photo-electrochemistry.
{"title":"Optimization of macropore silicon morphology etched by photo-electrochemistry","authors":"Guozheng Wang, Shencheng Fu, Yanjun Gao, Ye Li, Xin Wang, Q. Duanmu","doi":"10.1109/ICSICT.2008.4735058","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4735058","url":null,"abstract":"Macropore silicon etching with photo-electro-chemistry was carried out under different experimental conditions, including etching voltage, current density and wave length of optical source et al. The surface, diameter of pore and wall of the macropore silicon were observed with Scanning Electronic Microscope (SEM) and Metallographic Microscope. The influencing factors on morphology of pore were analyzed. Experimental parameters for fabricating high properties macropore silicon were also determined. Macropore silicon with depth of pores up to 300 ¿m and aspect ratios more than 75 was etched with photo-electrochemistry.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134120104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734894
Xu Zhang, Weihua Pei, Beiju Huang, Hongda Chen
A prototype neuro-stimulus chip for sub-retinal implants in blind patients affected by age-related macular degeneration (AMD) or retinitis pigmentosa (RP) is presented in this paper. This retinal prosthetic chip was designed to replace the degenerated photoreceptor cells, and in order to stimulate directly the remaining healthy layers of retinal neurons. The current stimulus circuits are monolithic integrated with photodiodes (PD) array, which can convert the illumination on the eyes into bi-phasic electrical pulses. In addition, a novel charge cancellation circuit is used to discharge the electrodes for medical safety.The prototype chip is designed and fabricated in HJTC 0.18 ¿m N-well CMOS 1P6M Mix-signal process, with a ± 2.5 V dual voltage power supply.
{"title":"Neuro-stimulus chip with photodiodes array for sub-retinal implants","authors":"Xu Zhang, Weihua Pei, Beiju Huang, Hongda Chen","doi":"10.1109/ICSICT.2008.4734894","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734894","url":null,"abstract":"A prototype neuro-stimulus chip for sub-retinal implants in blind patients affected by age-related macular degeneration (AMD) or retinitis pigmentosa (RP) is presented in this paper. This retinal prosthetic chip was designed to replace the degenerated photoreceptor cells, and in order to stimulate directly the remaining healthy layers of retinal neurons. The current stimulus circuits are monolithic integrated with photodiodes (PD) array, which can convert the illumination on the eyes into bi-phasic electrical pulses. In addition, a novel charge cancellation circuit is used to discharge the electrodes for medical safety.The prototype chip is designed and fabricated in HJTC 0.18 ¿m N-well CMOS 1P6M Mix-signal process, with a ± 2.5 V dual voltage power supply.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133999735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734951
Cuncai Zhang, Hui Wang, Yuhua Cheng
In this paper, a 10-bit 50-MS/s analog-to-digital converter (ADC) is presented. A power consumption of 10.6 mW is designed by using low power gain-boosted OP-Amp and dynamic comparator. Bootstrapped switch achieves rail-to-rail signal swing at low-voltage power supply. This circuit is designed in a SMIC 1.2-V 0.13-um CMOS technology. The results show that the proposed Nyquist rate ADC provides a potential solution for low-power high-speed applications, e.g., DVB-H, DVB-T and WLANs.
本文介绍了一种10位50毫秒/秒的模数转换器(ADC)。采用低功率增益增强运算放大器和动态比较器，设计功耗为10.6 mW。自举开关实现低压电源的轨间信号摆动。该电路采用中芯国际1.2 v 0.13 um CMOS技术设计。结果表明，所提出的奈奎斯特速率ADC为DVB-H、DVB-T和wlan等低功耗高速应用提供了一种潜在的解决方案。
{"title":"A study of a10-bit 50MS/s low voltage low power pipelined ADC","authors":"Cuncai Zhang, Hui Wang, Yuhua Cheng","doi":"10.1109/ICSICT.2008.4734951","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734951","url":null,"abstract":"In this paper, a 10-bit 50-MS/s analog-to-digital converter (ADC) is presented. A power consumption of 10.6 mW is designed by using low power gain-boosted OP-Amp and dynamic comparator. Bootstrapped switch achieves rail-to-rail signal swing at low-voltage power supply. This circuit is designed in a SMIC 1.2-V 0.13-um CMOS technology. The results show that the proposed Nyquist rate ADC provides a potential solution for low-power high-speed applications, e.g., DVB-H, DVB-T and WLANs.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134275547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4735040
Gang Dong, Peng Leng, Yintang Yang, C. Chai
Based on the equivalent Elmore delay model, a new delay model that takes inductance and thermal effect into consideration is presented in this paper. The proposed model with high efficiency has closed-form expression. Its solution exhibits high accuracy as compared to the other models. Simulation results show that the error in the propagation delay is less than 10% for RLC tree example.
{"title":"Analysis of RLC interconnect delay considering thermal effect","authors":"Gang Dong, Peng Leng, Yintang Yang, C. Chai","doi":"10.1109/ICSICT.2008.4735040","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4735040","url":null,"abstract":"Based on the equivalent Elmore delay model, a new delay model that takes inductance and thermal effect into consideration is presented in this paper. The proposed model with high efficiency has closed-form expression. Its solution exhibits high accuracy as compared to the other models. Simulation results show that the error in the propagation delay is less than 10% for RLC tree example.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131467387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734702
S. Maikap, S. Z. Rahaman, W. Banerjee, C. Lin, P. Tzeng, C. Wang, M. Kao, M. Tsai
Enhanced flash memory device characteristics using ALD TiN/Al2O3 nanolaminate charge storage layers have been investigated. After annealing treatment, the TiN nanocrystals embedded in Al2O3 films with a small diameter of ~3 nm and a high-density of >1×1012/cm2 have been formed. The memory devices show a high programming speed of ¿Vt >1 V@Vg/Vd=8 V/8 V, 10 ¿s and an erasing speed of ¿Vt >1 V@Vg/Vd=-12 V/0 V, 1 ms. The memory window is increased (¿Vt >6.7 V) with increasing the operation voltage. The memory window is also increased with increasing the number of TiN/Al2O3 nanolaminate layers. Good endurance (104 cycles) and retention (charge loss of ~14% at 20°C and ~17% at 85°C after 10 years) characteristics of the TiN nanocrystal memory devices can be explained by both of the high-density and layer-by-layer charge storage in the TiN nanocrystals. This novel nanocrystal memory structure can be useful in future nanoscale flash memory device applications.
{"title":"Enhanced flash memory device characteristics using ALD TiN/Al2O3 nanolaminate charge storage layers","authors":"S. Maikap, S. Z. Rahaman, W. Banerjee, C. Lin, P. Tzeng, C. Wang, M. Kao, M. Tsai","doi":"10.1109/ICSICT.2008.4734702","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734702","url":null,"abstract":"Enhanced flash memory device characteristics using ALD TiN/Al<sub>2</sub>O<sub>3</sub> nanolaminate charge storage layers have been investigated. After annealing treatment, the TiN nanocrystals embedded in Al<sub>2</sub>O<sub>3</sub> films with a small diameter of ~3 nm and a high-density of >1×10<sup>12</sup>/cm<sup>2</sup> have been formed. The memory devices show a high programming speed of ¿V<sub>t</sub> >1 V@V<sub>g</sub>/V<sub>d</sub>=8 V/8 V, 10 ¿s and an erasing speed of ¿V<sub>t</sub> >1 V@V<sub>g</sub>/V<sub>d</sub>=-12 V/0 V, 1 ms. The memory window is increased (¿V<sub>t</sub> >6.7 V) with increasing the operation voltage. The memory window is also increased with increasing the number of TiN/Al<sub>2</sub>O<sub>3</sub> nanolaminate layers. Good endurance (10<sup>4</sup> cycles) and retention (charge loss of ~14% at 20°C and ~17% at 85°C after 10 years) characteristics of the TiN nanocrystal memory devices can be explained by both of the high-density and layer-by-layer charge storage in the TiN nanocrystals. This novel nanocrystal memory structure can be useful in future nanoscale flash memory device applications.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"32 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131552323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734638
Shu-Yi Liu, Tao Chen, Yu-Long Jiang, G. Ru, Bingzong Li, X. Qu
The effect of the ZnO homo-buffer layer on the structural, optical and electrical properties of the Sol-gel ZnO films was systematically investigated. The XRD and SEM results show that the homo-buffer layer can improve the degree of the preferential c-axis orientation (the best Lotering orientation factor (F) can reach 0.915), the grain size and the surface morphology of thereon ZnO films. A narrower UV emission at 380 nm was observed with weaker deep-level visible emission for the ZnO films with a homo-buffer layer using room-temperature (RT) photoluminescence (PL) spectra. The electrical results show that the carrier concentration of the films with buffer layer is decreased and the Hall mobility is increased, indicating that a ZnO homo-buffer layer can effectively improve the crystallinity of the films and improve both electrical and optical properties.
{"title":"Improvement of the crystallinity and optical properties of sol-gel ZnO thin film by a PVD ZnO buffer layer","authors":"Shu-Yi Liu, Tao Chen, Yu-Long Jiang, G. Ru, Bingzong Li, X. Qu","doi":"10.1109/ICSICT.2008.4734638","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734638","url":null,"abstract":"The effect of the ZnO homo-buffer layer on the structural, optical and electrical properties of the Sol-gel ZnO films was systematically investigated. The XRD and SEM results show that the homo-buffer layer can improve the degree of the preferential c-axis orientation (the best Lotering orientation factor (F) can reach 0.915), the grain size and the surface morphology of thereon ZnO films. A narrower UV emission at 380 nm was observed with weaker deep-level visible emission for the ZnO films with a homo-buffer layer using room-temperature (RT) photoluminescence (PL) spectra. The electrical results show that the carrier concentration of the films with buffer layer is decreased and the Hall mobility is increased, indicating that a ZnO homo-buffer layer can effectively improve the crystallinity of the films and improve both electrical and optical properties.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130800726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734723
Z. Ma, Hao-Chih Yuan, G. Celler
In this paper, the materials, processing and device characteristics of flexible Si CMOS on plastic substrates are reviewed. The methods to create transferrable single-crystal Si nanomembranes are described first followed by the description of doping and transfer techniques developed for the nanomembranes. The preliminary device characteristics of CMOS and inverters on plastic substrates are presented.
{"title":"Flexible plastic single-crystal si CMOS","authors":"Z. Ma, Hao-Chih Yuan, G. Celler","doi":"10.1109/ICSICT.2008.4734723","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734723","url":null,"abstract":"In this paper, the materials, processing and device characteristics of flexible Si CMOS on plastic substrates are reviewed. The methods to create transferrable single-crystal Si nanomembranes are described first followed by the description of doping and transfer techniques developed for the nanomembranes. The preliminary device characteristics of CMOS and inverters on plastic substrates are presented.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133369142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734672
Wei He, D. Chan, B. Cho
LaAlOx with a permittivity of 17 is fabricated successfully by ALD method. Enhanced deposition rate, improved uniformity and self-limiting behavior were observed for LaAlOx compare to La2O3 deposition. The mechanism behind improvement is proposed. ALD LaAlOx is found to be thermally stable up to 850°C anneal. Compared with Al2O3 blocking oxide control samples, the SONOS devices with LaAlOx blocking oxide demonstrate similar retention performance with much faster operation speed and better resistance to high operation voltage and high stress. The results indicate that LaAlOx is an attractive candidate as a blocking layer in SONOS type flash memory application.
{"title":"SONOS type memory cell with ALD LaAlO blocking oxide for high speed operation","authors":"Wei He, D. Chan, B. Cho","doi":"10.1109/ICSICT.2008.4734672","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734672","url":null,"abstract":"LaAlO<sub>x</sub> with a permittivity of 17 is fabricated successfully by ALD method. Enhanced deposition rate, improved uniformity and self-limiting behavior were observed for LaAlO<sub>x</sub> compare to La<sub>2</sub>O<sub>3</sub> deposition. The mechanism behind improvement is proposed. ALD LaAlO<sub>x</sub> is found to be thermally stable up to 850°C anneal. Compared with Al<sub>2</sub>O<sub>3</sub> blocking oxide control samples, the SONOS devices with LaAlO<sub>x</sub> blocking oxide demonstrate similar retention performance with much faster operation speed and better resistance to high operation voltage and high stress. The results indicate that LaAlO<sub>x</sub> is an attractive candidate as a blocking layer in SONOS type flash memory application.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133311426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734585
B. Jie, C. Sah
This article summarizes the history and progresses on our development of the Bipolar Field-Effect Transistor Theory (BiFET). The 2-Dimensional (2-D) rectangular geometry of the transistor (uniform in the width or Z-direction) is employed to decompose the 2-D equation into two 1-D equations which are parametrically coupled by the surface-electric-potential. This decomposition enables us to obtain the generic baseline solutions, both analytical and numerical, without the 2-D features which are then treated as the modifications of the 1-D solutions. The 1952-Shockley 2-section model used for the volume-channel geometry of his Junction-Gate (JG) FET is employed to both the surface and the volume-channels of the MOS BiFET, which we have designated and coined as the emitter and collector sections, each can simultaneously be electron and hole, surface or volume channels.
{"title":"The bipolar theory of the Bipolar Field-Effect Transistor: Recent advances","authors":"B. Jie, C. Sah","doi":"10.1109/ICSICT.2008.4734585","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734585","url":null,"abstract":"This article summarizes the history and progresses on our development of the Bipolar Field-Effect Transistor Theory (BiFET). The 2-Dimensional (2-D) rectangular geometry of the transistor (uniform in the width or Z-direction) is employed to decompose the 2-D equation into two 1-D equations which are parametrically coupled by the surface-electric-potential. This decomposition enables us to obtain the generic baseline solutions, both analytical and numerical, without the 2-D features which are then treated as the modifications of the 1-D solutions. The 1952-Shockley 2-section model used for the volume-channel geometry of his Junction-Gate (JG) FET is employed to both the surface and the volume-channels of the MOS BiFET, which we have designated and coined as the emitter and collector sections, each can simultaneously be electron and hole, surface or volume channels.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"42 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133420133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734898
H. T. Russell, R. Carter, W. Davis
A wide-band current mirror for precision biasing has been fabricated in a complementary SOI bipolar process. The mirror is a feedback circuit using common-base transistor in the loop to compensate for base current loss.
{"title":"A wide-band all-NPN current mirror for precision biasing of multiple circuits","authors":"H. T. Russell, R. Carter, W. Davis","doi":"10.1109/ICSICT.2008.4734898","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734898","url":null,"abstract":"A wide-band current mirror for precision biasing has been fabricated in a complementary SOI bipolar process. The mirror is a feedback circuit using common-base transistor in the loop to compensate for base current loss.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"257 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132176603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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