Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734614
W. Liu, Z. Liu, Y. Luo, G. Jiao, X. Huang, D. Huang, C. Liao, L. Zhang, Z. Gan, W. Wong, Ming-Fu Li
Negative bias temperature instability in pMOSFETs with thermally and plasma nitrided oxides is investigated using quasi-DC Id-Vg (slow Id-Vg) and on-the-fly interface trap (OFIT) measurement methods. By comparing the OFIT results with those observed from Id-Vg measurements, we found that the threshold voltage shift measured by slow Id-Vg is mainly due to the interface trap since the oxide charge is essentially detrapped during the measurement delay. Quantitatively, the interface trap density measured by OFIT method is higher than that by slow Id-Vg measurement, since the latter measurement is subjected to the recovery effect. For the thermally and plasma nitrided oxides, we found the interface trap density is higher for thermally nitride oxide. However, the power law time exponent n as stress time is the same for the pMOSFETs with both processes.
{"title":"Characteristics of NBTI in pMOSFETs with thermally and plasma nitrided gate oxides","authors":"W. Liu, Z. Liu, Y. Luo, G. Jiao, X. Huang, D. Huang, C. Liao, L. Zhang, Z. Gan, W. Wong, Ming-Fu Li","doi":"10.1109/ICSICT.2008.4734614","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734614","url":null,"abstract":"Negative bias temperature instability in pMOSFETs with thermally and plasma nitrided oxides is investigated using quasi-DC Id-Vg (slow Id-Vg) and on-the-fly interface trap (OFIT) measurement methods. By comparing the OFIT results with those observed from Id-Vg measurements, we found that the threshold voltage shift measured by slow Id-Vg is mainly due to the interface trap since the oxide charge is essentially detrapped during the measurement delay. Quantitatively, the interface trap density measured by OFIT method is higher than that by slow Id-Vg measurement, since the latter measurement is subjected to the recovery effect. For the thermally and plasma nitrided oxides, we found the interface trap density is higher for thermally nitride oxide. However, the power law time exponent n as stress time is the same for the pMOSFETs with both processes.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124828625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734558
Sung-Min Hong, C. Jungemann
The Boltzmann equation is solved by a spherical harmonics expansion including a magnetic force perpendicular to the two-dimensional simulation plane in real space. The new approach is used to verify a methodology for extracting the electron minority mobility of SiGe HBTs. Magnetotransport in a silicon n+nn+ device is simulated and a strong impact of the maximum number of spherical harmonics on the simulation result is found.
{"title":"Simulation of magnetotransport in nanoscale devices","authors":"Sung-Min Hong, C. Jungemann","doi":"10.1109/ICSICT.2008.4734558","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734558","url":null,"abstract":"The Boltzmann equation is solved by a spherical harmonics expansion including a magnetic force perpendicular to the two-dimensional simulation plane in real space. The new approach is used to verify a methodology for extracting the electron minority mobility of SiGe HBTs. Magnetotransport in a silicon n+nn+ device is simulated and a strong impact of the maximum number of spherical harmonics on the simulation result is found.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126171609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734466
Zhenhua Wang, R. Huang
The Impact Ionization MOS (IMOS) transistor is a kind of promising concept as a candidate of MOS transistor due to its abrupt switching. However, some key issues will limit IMOS transistors for practical applications. In this paper, detailed physical explanations for the non-saturation of IMOS output characteristics and the unanticipated low drive current are presented. A new method to enhance the drive current of IMOS devices is reported and briefly discussed as well.
{"title":"Investigations on the performance limits of the IMOS transistor","authors":"Zhenhua Wang, R. Huang","doi":"10.1109/ICSICT.2008.4734466","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734466","url":null,"abstract":"The Impact Ionization MOS (IMOS) transistor is a kind of promising concept as a candidate of MOS transistor due to its abrupt switching. However, some key issues will limit IMOS transistors for practical applications. In this paper, detailed physical explanations for the non-saturation of IMOS output characteristics and the unanticipated low drive current are presented. A new method to enhance the drive current of IMOS devices is reported and briefly discussed as well.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123554719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734785
B. Mizuno, Y. Sasaki, C. Jin, K. Okashita, K. Nakamoto, T. Kitaoka, K. Tsutsui, H. Sauddin, H. Iwai
Semiconductors have been successfully produced by the miniaturization of planar transistors and their transformation into a 3D structure. This innovation will realize ideal performance in electric devices. In this article, plasma doping combined with He plasma amorphization (He-PA) and several state-of-the-art rapid thermal processing is shown to be a technology for enabling the fabrication of miniaturized 2D devices and advanced 3D structures.
{"title":"Production-worthy approach of plasma doping (PD)","authors":"B. Mizuno, Y. Sasaki, C. Jin, K. Okashita, K. Nakamoto, T. Kitaoka, K. Tsutsui, H. Sauddin, H. Iwai","doi":"10.1109/ICSICT.2008.4734785","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734785","url":null,"abstract":"Semiconductors have been successfully produced by the miniaturization of planar transistors and their transformation into a 3D structure. This innovation will realize ideal performance in electric devices. In this article, plasma doping combined with He plasma amorphization (He-PA) and several state-of-the-art rapid thermal processing is shown to be a technology for enabling the fabrication of miniaturized 2D devices and advanced 3D structures.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123752882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734582
X.Y. Liu, Y.C. Song, G. Du, R. Han, Z. Xia, D. Kim, K. Lee
The floating gate type of flash memory is impossible to scale down to beyond 45 nm due to the difficulty in scaling the tunnel oxide and the gate coupling ratio. Because of the difficulty in maintaining high gate coupling ratio and preventing cross talk between neighboring cells, NAND technology is forecasted to migrate gradually from floating gate devices (FG) to charge trapping memory (CTM). CTM are not sensitive to tunnel oxide damage since the charge is stored in discrete traps and one weak spot does not cause all stored charge to leak out as in floating gate devices. The NAND HC-TANOS flash cell has been generated in three dimensional TCAD tools with 38 nm gate length, 34 nm channel width and charge trapping structures. A structure of Al2O3 (15 nm)/Si3Na (6.5 nm)/SiO2 (4.5 nm) with TaN gate was employed as the gate stack. To study the effects of gate stack coverage on flash cell's performance, the shape of gate stack is varied while keeping all other structural parameters fixed.
{"title":"Simulation of charge trapping memory with novel structures","authors":"X.Y. Liu, Y.C. Song, G. Du, R. Han, Z. Xia, D. Kim, K. Lee","doi":"10.1109/ICSICT.2008.4734582","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734582","url":null,"abstract":"The floating gate type of flash memory is impossible to scale down to beyond 45 nm due to the difficulty in scaling the tunnel oxide and the gate coupling ratio. Because of the difficulty in maintaining high gate coupling ratio and preventing cross talk between neighboring cells, NAND technology is forecasted to migrate gradually from floating gate devices (FG) to charge trapping memory (CTM). CTM are not sensitive to tunnel oxide damage since the charge is stored in discrete traps and one weak spot does not cause all stored charge to leak out as in floating gate devices. The NAND HC-TANOS flash cell has been generated in three dimensional TCAD tools with 38 nm gate length, 34 nm channel width and charge trapping structures. A structure of Al2O3 (15 nm)/Si3Na (6.5 nm)/SiO2 (4.5 nm) with TaN gate was employed as the gate stack. To study the effects of gate stack coverage on flash cell's performance, the shape of gate stack is varied while keeping all other structural parameters fixed.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114918823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734998
Jie Pan, Haigang Yang, Li-wu Yang
A high-speed low-power programmable pulse-swallow divider is designed and fabricated in SMIC 0.18-¿m CMOS process. Two critical paths that limit the operating frequency are analyzed. The proposed prescaler based on a shift-register-ring is insensitive to the Modulus Control (MC) during its first few input cycles, and thus wrong divide ratio caused by the MC¿s delay can be avoided. The proposed pulse generator works as a sample/hold block to widen the time slot of the reading process, and thus failure in reading external control words into the swallow counter can also be avoided. A 3.5-GHz integer phase-locked loop (PLL) that uses the divider employing the proposed prescaler and pulse generator provides 21 channels with a 1.2-ppm precision in measurements. The power dissipation is 0.475-mW from a 1.2-V supply under 1.6-GHz operating frequency.
采用中芯国际0.18- m CMOS工艺，设计制作了一种高速低功耗可编程吞脉分压器。分析了限制工作频率的两条关键路径。所提出的基于移位寄存器环的预分频器在前几个输入周期内对模量控制(MC)不敏感，因此可以避免模量控制延迟引起的错除比。所提出的脉冲发生器作为采样/保持块来扩大读取过程的时隙，因此也可以避免将外部控制字读取到吞咽计数器中的失败。3.5 ghz整数锁相环(PLL)使用采用所提出的预量器和脉冲发生器的分频器，提供21个通道，测量精度为1.2 ppm。在1.6 ghz工作频率下，1.2 v电源功耗为0.475 mw。
{"title":"A high-speed low-power pulse-swallow divider with robustness consideration","authors":"Jie Pan, Haigang Yang, Li-wu Yang","doi":"10.1109/ICSICT.2008.4734998","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734998","url":null,"abstract":"A high-speed low-power programmable pulse-swallow divider is designed and fabricated in SMIC 0.18-¿m CMOS process. Two critical paths that limit the operating frequency are analyzed. The proposed prescaler based on a shift-register-ring is insensitive to the Modulus Control (MC) during its first few input cycles, and thus wrong divide ratio caused by the MC¿s delay can be avoided. The proposed pulse generator works as a sample/hold block to widen the time slot of the reading process, and thus failure in reading external control words into the swallow counter can also be avoided. A 3.5-GHz integer phase-locked loop (PLL) that uses the divider employing the proposed prescaler and pulse generator provides 21 channels with a 1.2-ppm precision in measurements. The power dissipation is 0.475-mW from a 1.2-V supply under 1.6-GHz operating frequency.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115498170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4735045
Hui Dai, Qiang Zhou, Jinian Bian, Yanhua Wang
In this paper, we present a multilevel hierarchical FPGA (MFPGA) architecture model and propose a cluster-based placement algorithm for this model. The algorithm has a multi-scale optimized V-shape flow including constructive bottom-up clustering process and top-down placement process. Experimental results indicate that our algorithm improves total wire-length and logic utilization by more than 15% and 10% on average for MCNC benchmark designs compared with the start-of-art vpr tool.
{"title":"Cluster-based Placement for multilevel hierarchical FPGA","authors":"Hui Dai, Qiang Zhou, Jinian Bian, Yanhua Wang","doi":"10.1109/ICSICT.2008.4735045","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4735045","url":null,"abstract":"In this paper, we present a multilevel hierarchical FPGA (MFPGA) architecture model and propose a cluster-based placement algorithm for this model. The algorithm has a multi-scale optimized V-shape flow including constructive bottom-up clustering process and top-down placement process. Experimental results indicate that our algorithm improves total wire-length and logic utilization by more than 15% and 10% on average for MCNC benchmark designs compared with the start-of-art vpr tool.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115579690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734658
E. Seebauer
The behavior of point defects within silicon can be changed significantly by controlling the chemical state at the surface. In ultrashallow junction applications for integrated circuits, such effects can be exploited to reduce transient enhanced diffusion, increase dopant activation, and reduce end-of-range damage.
{"title":"Surfaces and interfaces for controlled defect engineering","authors":"E. Seebauer","doi":"10.1109/ICSICT.2008.4734658","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734658","url":null,"abstract":"The behavior of point defects within silicon can be changed significantly by controlling the chemical state at the surface. In ultrashallow junction applications for integrated circuits, such effects can be exploited to reduce transient enhanced diffusion, increase dopant activation, and reduce end-of-range damage.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116128350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734778
R. Xie, Chunxiang Zhu
In this paper, various interface engineering techniques for high-k/Ge gate stack for advanced CMOS device applications are reviewed. High-k gate stack formation on Ge substrate is first addressed with emphasis on pre-gate surface passivation. Post gate dielectric (post-gate) treatments are then discussed to further improve the high-k/Ge interface quality.
{"title":"Interface engineering for high-k/Ge gate stack","authors":"R. Xie, Chunxiang Zhu","doi":"10.1109/ICSICT.2008.4734778","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734778","url":null,"abstract":"In this paper, various interface engineering techniques for high-k/Ge gate stack for advanced CMOS device applications are reviewed. High-k gate stack formation on Ge substrate is first addressed with emphasis on pre-gate surface passivation. Post gate dielectric (post-gate) treatments are then discussed to further improve the high-k/Ge interface quality.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114284018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734808
Liu Jihua, Li Zhiqun, Wang Zhigong, Shen Jianjun
A 3.33 GHz-3.53 GHz power amplifier for satellite communications is designed by using JAZZ 0.35 ¿m SiGe BiCMOS process. This power amplifier works in class AB type with single-ended structure. With a supply voltage of 3.3 V, the power gain is 23 dB at its center operation frequency and it can transmit 29.98 dBm output power to a 50 ¿ load at 1 dB power compression point with 33.84% power added efficiency. The simulation results show that the input and output matching are well and it can work stably.
{"title":"3.43GHz power amplifier design for satellite communications","authors":"Liu Jihua, Li Zhiqun, Wang Zhigong, Shen Jianjun","doi":"10.1109/ICSICT.2008.4734808","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734808","url":null,"abstract":"A 3.33 GHz-3.53 GHz power amplifier for satellite communications is designed by using JAZZ 0.35 ¿m SiGe BiCMOS process. This power amplifier works in class AB type with single-ended structure. With a supply voltage of 3.3 V, the power gain is 23 dB at its center operation frequency and it can transmit 29.98 dBm output power to a 50 ¿ load at 1 dB power compression point with 33.84% power added efficiency. The simulation results show that the input and output matching are well and it can work stably.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"223 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122094181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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