Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734818
Huaming Wang, Xueguan Liu, Wenfeng Cai, Hongfang Cao
A new compact branch-line directional coupler is proposed combined the T-model branch line coupler with defected ground structure (DGS). Using transmission theory, the parameter selection limit about the T-Model equivalent structure is discussed firstly. Then a T-model branch line coupler with DGS is proposed and optimum designed with simulation software. The measurement results show that the proposed coupler has the advantages as compact and well passband flatness.
{"title":"Design and realization of a new compact branch-line coupler using defected ground structure","authors":"Huaming Wang, Xueguan Liu, Wenfeng Cai, Hongfang Cao","doi":"10.1109/ICSICT.2008.4734818","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734818","url":null,"abstract":"A new compact branch-line directional coupler is proposed combined the T-model branch line coupler with defected ground structure (DGS). Using transmission theory, the parameter selection limit about the T-Model equivalent structure is discussed firstly. Then a T-model branch line coupler with DGS is proposed and optimum designed with simulation software. The measurement results show that the proposed coupler has the advantages as compact and well passband flatness.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116982407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4735024
Wei Xiong, Jinyu Zhang, M. Tsai, Yan Wang, Zhiping Yu
Inverse Lithography Technology (ILT) is a promising solution to enhance the resolution of the optical system in deep-subwavelength lithography. In this paper, we introduce a gradient-based framework for mask synthesis. Firstly, we model the mask-to-wafer process using a continuous transfer function. Then Newton iterations are employed to solve the continuous inverse problems. Finally, we apply our framework to the mask synthesis for 65 nm SRAM manufacturing. The simulation results show that the optimized masks can be efficiently obtained and good fidelity in patterning is achieved.
{"title":"Mask synthesis for 65nm SRAM manufacturing using gradient-based Inverse Lithography Technology (ILT)","authors":"Wei Xiong, Jinyu Zhang, M. Tsai, Yan Wang, Zhiping Yu","doi":"10.1109/ICSICT.2008.4735024","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4735024","url":null,"abstract":"Inverse Lithography Technology (ILT) is a promising solution to enhance the resolution of the optical system in deep-subwavelength lithography. In this paper, we introduce a gradient-based framework for mask synthesis. Firstly, we model the mask-to-wafer process using a continuous transfer function. Then Newton iterations are employed to solve the continuous inverse problems. Finally, we apply our framework to the mask synthesis for 65 nm SRAM manufacturing. The simulation results show that the optimized masks can be efficiently obtained and good fidelity in patterning is achieved.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121993222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734813
T. Miracco
Higher-order modulation schemes such as orthogonal frequency division multiplexing (OFDM) employed by some current and virtually all next-generation wireless systems demand the highest possible transmitter linearity and power-added efficiency (PAE). This requirement extends from RF power transistors to the power amplifiers (PAs) in which they are employed. As a result, PA designers must find ways to effectively balance the need to achieve the highest PAE with ensuring the resulting RF output signal does not interfere with neighboring signals through spectral re-growth. Techniques including digital pre-distortion and crest factor reduction have been developed to achieve maximum efficiency and dynamic range while minimizing spectral re-growth through high adjacent-channel leakage power (ACLR). This paper describes both techniques, illustrates how the benefits achievable with each one can be effectively determined during the early stages of design, and shows the level of potential improvement using a multi-carrier 3GPP WCDMA HSDPA signal as an example.
{"title":"Crest factor reduction and digital pre-distortion for wireless RF power amplifier optimization","authors":"T. Miracco","doi":"10.1109/ICSICT.2008.4734813","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734813","url":null,"abstract":"Higher-order modulation schemes such as orthogonal frequency division multiplexing (OFDM) employed by some current and virtually all next-generation wireless systems demand the highest possible transmitter linearity and power-added efficiency (PAE). This requirement extends from RF power transistors to the power amplifiers (PAs) in which they are employed. As a result, PA designers must find ways to effectively balance the need to achieve the highest PAE with ensuring the resulting RF output signal does not interfere with neighboring signals through spectral re-growth. Techniques including digital pre-distortion and crest factor reduction have been developed to achieve maximum efficiency and dynamic range while minimizing spectral re-growth through high adjacent-channel leakage power (ACLR). This paper describes both techniques, illustrates how the benefits achievable with each one can be effectively determined during the early stages of design, and shows the level of potential improvement using a multi-carrier 3GPP WCDMA HSDPA signal as an example.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120841697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4735053
W. Chang, Jian-an Lin, W. Yeh
This study evaluated metal oxide semiconductor field-effect transistor (MOSFETs) with channel lengths/widths of 0.135/10, 0.45/10, and 10/10 ¿m for both the n- and p- channel types used as sensing elements. The results show that the devices with channel lengths/widths of 0.45/10 and 10/10 ¿m have flat saturation current. It suggests that there is a requirement for a device to have a channel length of over 0.45 ¿m to provide better sensing characterization to normalized current change. The experimental result also demonstrates the fine linear dependence of stress distribution to the distance of tested devices from the clamping end for a silicon cantilever. The stress distribution is detected via normalized current change for all the three sizes of channel length and for both the n and p- types. Moreover, the device with larger channel length has better stress sensitivity than that with the smaller one, when the channel width is fixed at 10 ¿m.
{"title":"Piezoresistive sensor of short- and long- channel MOSFETs on (100) silicon","authors":"W. Chang, Jian-an Lin, W. Yeh","doi":"10.1109/ICSICT.2008.4735053","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4735053","url":null,"abstract":"This study evaluated metal oxide semiconductor field-effect transistor (MOSFETs) with channel lengths/widths of 0.135/10, 0.45/10, and 10/10 ¿m for both the n- and p- channel types used as sensing elements. The results show that the devices with channel lengths/widths of 0.45/10 and 10/10 ¿m have flat saturation current. It suggests that there is a requirement for a device to have a channel length of over 0.45 ¿m to provide better sensing characterization to normalized current change. The experimental result also demonstrates the fine linear dependence of stress distribution to the distance of tested devices from the clamping end for a silicon cantilever. The stress distribution is detected via normalized current change for all the three sizes of channel length and for both the n and p- types. Moreover, the device with larger channel length has better stress sensitivity than that with the smaller one, when the channel width is fixed at 10 ¿m.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124083361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734514
Ning-Juan Wang, Ning Li, Zhong-li Liu, Fang Yu, Guohua Li
FD SOI MOSFETs with MESA and Irradiated FD SOI MOSFETs with LOCOS isolation usually show the edge effect, that is, the leakage current called hump is generated in the subthreshold region. According to different reasons for generating the edge effect, rounded corner process and BTS structure are applied to improve device performance. The results indicate that the above two methods are effective to reduce the edge effect and qualified devices are fabricated successfully.
带MESA的FD SOI mosfet和带LOCOS隔离的辐照FD SOI mosfet通常表现出边缘效应，即在亚阈值区域产生称为驼峰的泄漏电流。针对产生边缘效应的不同原因，采用圆角工艺和BTS结构来提高器件性能。结果表明，上述两种方法都能有效地减小边缘效应，并成功制备出合格的器件。
{"title":"Fabrication of improved FD SOIMOSFETs for suppressing edge effect","authors":"Ning-Juan Wang, Ning Li, Zhong-li Liu, Fang Yu, Guohua Li","doi":"10.1109/ICSICT.2008.4734514","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734514","url":null,"abstract":"FD SOI MOSFETs with MESA and Irradiated FD SOI MOSFETs with LOCOS isolation usually show the edge effect, that is, the leakage current called hump is generated in the subthreshold region. According to different reasons for generating the edge effect, rounded corner process and BTS structure are applied to improve device performance. The results indicate that the above two methods are effective to reduce the edge effect and qualified devices are fabricated successfully.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124471864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734626
Hai-Yan Jin, E.Z. Liu, N. Cheung
The fabrication of Germanium-On-Insulator (GeOI) by wafer bonding and ion-cut approach was investigated. With cyclic HF/DIW cleaning and N2 plasma surface activation, large-area layer transfer of GeOI substrates was realized by ion-cut processes with bulk Ge wafer as the donor wafer. The GeOI substrates are thermally stable up to 550°C annealing and surface roughness can be smoothed down to 0.3 nm RMS by Chemical Mechanical Planarization (CMP). After surface polishing, Epi-Ge on Si wafer can also be used as the donor wafer to realize layer transfer. Four-probe configuration Pseudo-MOSFET was employed to characterize the electrical properties of the transferred Ge and the Ge/SiO2 bonding interface. At Ge/SiO2 interface, GeOI substrates show both accumulation and inversion conduction modes. High-temperature forming gas annealing in the vicinity of 500°C¿600°C has shown the best carrier mobilities, with the interface trap density and interface fixed charge density as low as 1010/cm2. The extracted bulk hole mobility of the annealed GeOI is near 500 cm2/V-s, which is higher than that of silicon (300 cm2/V-s) at the same doping concentration level.
{"title":"Fabrication and characteristics of Germanium-On-Insulator substrates","authors":"Hai-Yan Jin, E.Z. Liu, N. Cheung","doi":"10.1109/ICSICT.2008.4734626","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734626","url":null,"abstract":"The fabrication of Germanium-On-Insulator (GeOI) by wafer bonding and ion-cut approach was investigated. With cyclic HF/DIW cleaning and N2 plasma surface activation, large-area layer transfer of GeOI substrates was realized by ion-cut processes with bulk Ge wafer as the donor wafer. The GeOI substrates are thermally stable up to 550°C annealing and surface roughness can be smoothed down to 0.3 nm RMS by Chemical Mechanical Planarization (CMP). After surface polishing, Epi-Ge on Si wafer can also be used as the donor wafer to realize layer transfer. Four-probe configuration Pseudo-MOSFET was employed to characterize the electrical properties of the transferred Ge and the Ge/SiO2 bonding interface. At Ge/SiO2 interface, GeOI substrates show both accumulation and inversion conduction modes. High-temperature forming gas annealing in the vicinity of 500°C¿600°C has shown the best carrier mobilities, with the interface trap density and interface fixed charge density as low as 1010/cm2. The extracted bulk hole mobility of the annealed GeOI is near 500 cm2/V-s, which is higher than that of silicon (300 cm2/V-s) at the same doping concentration level.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"17 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125785511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734637
M. Yoshimi, D. Delpra, I. Cayrefourcq, G. Celler, C. Mazure, B. Aspar
The current status of SOI technology using wafer bonding is reviewed and its technological positioning in CMOS scaling is discussed. While bulk CMOS technology is encountering various kinds of critical issues, SOI technology using wafer bonding provides unique solutions by virtue of its flexible material design. Mobility enhancement through strained-SOI (sSOI) or optimization of crystal orientation (HOT, DSB), dynamic threshold voltage control by back-biasing (UT-BOX SOI), capacitor-less DRAM, etc., are promising options that can bring a breakthrough and continue proper scaling. Also, circuit layer transfer technology applied to back-side illumination of CMOS imager is presented, as a technology giving linkage with future 3D-integration of LSI system.
{"title":"Current status and possibilities of wafer-bonding-based SOI technology in 45nm or below CMOS LSIs","authors":"M. Yoshimi, D. Delpra, I. Cayrefourcq, G. Celler, C. Mazure, B. Aspar","doi":"10.1109/ICSICT.2008.4734637","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734637","url":null,"abstract":"The current status of SOI technology using wafer bonding is reviewed and its technological positioning in CMOS scaling is discussed. While bulk CMOS technology is encountering various kinds of critical issues, SOI technology using wafer bonding provides unique solutions by virtue of its flexible material design. Mobility enhancement through strained-SOI (sSOI) or optimization of crystal orientation (HOT, DSB), dynamic threshold voltage control by back-biasing (UT-BOX SOI), capacitor-less DRAM, etc., are promising options that can bring a breakthrough and continue proper scaling. Also, circuit layer transfer technology applied to back-side illumination of CMOS imager is presented, as a technology giving linkage with future 3D-integration of LSI system.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"156 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125911272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734964
J. Day, P. Vulpoiu, D. Johnson, J. Julich, D. Lie
This paper discusses an 8MHz square wave oscillator used for a clock signal of the digital core of a mixed signal integrated circuit (IC). The frequency is determined by a bias current that charges a capacitor until it triggers a comparator with a voltage reference as the second input. A low drop out (LDO) voltage regulator is used to supply the oscillator so that variations in the battery voltage do not affect the oscillator.. The circuits have been designed and taped out and the measured results are closed to the SPICE simulated values. The oscillator has very low power consumption of 165 μW which is very attractive for a general handheld device that is operated off of a battery.
{"title":"A 65μA 8MHz On-Chip Oscillator with LDO regulator for low-power handheld SoC applications","authors":"J. Day, P. Vulpoiu, D. Johnson, J. Julich, D. Lie","doi":"10.1109/ICSICT.2008.4734964","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734964","url":null,"abstract":"This paper discusses an 8MHz square wave oscillator used for a clock signal of the digital core of a mixed signal integrated circuit (IC). The frequency is determined by a bias current that charges a capacitor until it triggers a comparator with a voltage reference as the second input. A low drop out (LDO) voltage regulator is used to supply the oscillator so that variations in the battery voltage do not affect the oscillator.. The circuits have been designed and taped out and the measured results are closed to the SPICE simulated values. The oscillator has very low power consumption of 165 μW which is very attractive for a general handheld device that is operated off of a battery.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125989728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734876
Peng Luo, Xinan Wang, Jun Feng, Ying Xu
RFID tags have gradually become popular tools for identification of products. To ensure the secure information transaction of tags, a scheme of RFID system authentication protocol based on Elliptic Curve Cryptography (ECC) is proposed. However, hardware implementation of ECC processor for RFID tags is a challenge for the requirements of low-power consumption and low-cost chip resource. In the paper we propose a novel ALU architecture for ECC processor on tags. By specially restructured the conventional mathematical expressions of Montgomery algorithm, the ALU operation of point multiplication in our design is reduced by nearly 47%. Also, various multipliers, such as bit-serial multiplier, digit-serial multiplier and the divided algorithm are adopted to balance between power consumption and speed. To attain ultra low power consumption, other techniques, such as finite state machines (FSM) optimization, clock gating, pipelining operations and low-power target library are used in the design. The area of the ECC processor is equal to 16.9 k gates equivalents. It performs an elliptic curve point multiplication in 36174 clock cycles and has a power consumption of 6.607 ¿W at 1.28 MHz using TSMC 0.18 ¿m low-voltage cell library.
{"title":"Low-power hardware implementation of ECC processor suitable for low-cost RFID tags","authors":"Peng Luo, Xinan Wang, Jun Feng, Ying Xu","doi":"10.1109/ICSICT.2008.4734876","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734876","url":null,"abstract":"RFID tags have gradually become popular tools for identification of products. To ensure the secure information transaction of tags, a scheme of RFID system authentication protocol based on Elliptic Curve Cryptography (ECC) is proposed. However, hardware implementation of ECC processor for RFID tags is a challenge for the requirements of low-power consumption and low-cost chip resource. In the paper we propose a novel ALU architecture for ECC processor on tags. By specially restructured the conventional mathematical expressions of Montgomery algorithm, the ALU operation of point multiplication in our design is reduced by nearly 47%. Also, various multipliers, such as bit-serial multiplier, digit-serial multiplier and the divided algorithm are adopted to balance between power consumption and speed. To attain ultra low power consumption, other techniques, such as finite state machines (FSM) optimization, clock gating, pipelining operations and low-power target library are used in the design. The area of the ECC processor is equal to 16.9 k gates equivalents. It performs an elliptic curve point multiplication in 36174 clock cycles and has a power consumption of 6.607 ¿W at 1.28 MHz using TSMC 0.18 ¿m low-voltage cell library.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124617381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734701
Jin Lu, Guangli Wang, Yubin Chen, Z. Zuo, Yi Shi, L. Pu, Youdou Zheng
The gradual Ge1-xSix/Si heteronanocrystals on ultra thin SiO2 were fabricated to form the metal-oxide-semiconductor (MOS) memory structure with asymmetric tunnel barriers through combining self-assembled growth and selective chemical etching technique. Charge storage characteristics in such memory structure have been investigated by using capacitance-voltage measurements. The observations demonstrate that the holes reach a longer retention time even with an ultra thin tunnel oxide, owing to the high band offset at the valence band between Ge and Si.
{"title":"Gradual Ge1−xSix/Si heteronanocrystals based non-volatile floating gate memory device with asymmetric tunnel barriers","authors":"Jin Lu, Guangli Wang, Yubin Chen, Z. Zuo, Yi Shi, L. Pu, Youdou Zheng","doi":"10.1109/ICSICT.2008.4734701","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734701","url":null,"abstract":"The gradual Ge1-xSix/Si heteronanocrystals on ultra thin SiO2 were fabricated to form the metal-oxide-semiconductor (MOS) memory structure with asymmetric tunnel barriers through combining self-assembled growth and selective chemical etching technique. Charge storage characteristics in such memory structure have been investigated by using capacitance-voltage measurements. The observations demonstrate that the holes reach a longer retention time even with an ultra thin tunnel oxide, owing to the high band offset at the valence band between Ge and Si.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124764376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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