Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4735082
Wei-xia Ou-yang, XingLong Guo, Chao Wang, Yong-hua Zhang, Zong-sheng Lai
This paper addresses the design and the realization of millimeter wave tunable filters using multiple-contact MEMS switches. The two unit cell filter based on slow-wave coplanar waveguide(CPW) periodic structure are reconfigured into a self-similar single unit cell by the operation of MEMS switches with single actuation. The 3-dB cutoff frequency of the low-pass filter was shifted from 12.5 GHz to 6.1 GHz, which exhibits excellent performance on small size, low insertion loss and is compatible with monolithic microwave integrated circuit technologies. The tested results show that the pass-band ripple is less than 0.5 dB and the out-of-band rejection is better than 40 dB. The driven voltages of the switches are around 25 V.
{"title":"A reconfigurable RF MEMS low-pass filter, based on CPW periodic structures","authors":"Wei-xia Ou-yang, XingLong Guo, Chao Wang, Yong-hua Zhang, Zong-sheng Lai","doi":"10.1109/ICSICT.2008.4735082","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4735082","url":null,"abstract":"This paper addresses the design and the realization of millimeter wave tunable filters using multiple-contact MEMS switches. The two unit cell filter based on slow-wave coplanar waveguide(CPW) periodic structure are reconfigured into a self-similar single unit cell by the operation of MEMS switches with single actuation. The 3-dB cutoff frequency of the low-pass filter was shifted from 12.5 GHz to 6.1 GHz, which exhibits excellent performance on small size, low insertion loss and is compatible with monolithic microwave integrated circuit technologies. The tested results show that the pass-band ripple is less than 0.5 dB and the out-of-band rejection is better than 40 dB. The driven voltages of the switches are around 25 V.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117069087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734899
Jianghua Chen, Xiaoxin Cui, Xuewen Ni, Bangxian Mo
This paper describes a low-noise low-offset CMOS readout circuit for MEMS capacitive accelerometers. It employs a feedback capacitance and a combination of switches to have the input parasitic capacitance and the offset voltage canceled. The raised current IDS of the input differential pair in the first stage is used to help reduce sharply the total low-frequency noises without increasing the complexity of the proposed circuit. The simulation result of the proposed circuit shows that an average 60% noise reduction at low frequencies has been achieved when the current in the current source of the first stage is raised six times the original. The root mean square equivalent input noise voltage is about 6.1nV/rtHz@1kHz. The experimental result shows that the capacitance resolution of the whole readout circuit is 10aF/rtHz@1kHz.
{"title":"A low-noise low-offset CMOS readout circuit for MEMS capacitive accelerometers","authors":"Jianghua Chen, Xiaoxin Cui, Xuewen Ni, Bangxian Mo","doi":"10.1109/ICSICT.2008.4734899","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734899","url":null,"abstract":"This paper describes a low-noise low-offset CMOS readout circuit for MEMS capacitive accelerometers. It employs a feedback capacitance and a combination of switches to have the input parasitic capacitance and the offset voltage canceled. The raised current IDS of the input differential pair in the first stage is used to help reduce sharply the total low-frequency noises without increasing the complexity of the proposed circuit. The simulation result of the proposed circuit shows that an average 60% noise reduction at low frequencies has been achieved when the current in the current source of the first stage is raised six times the original. The root mean square equivalent input noise voltage is about 6.1nV/rtHz@1kHz. The experimental result shows that the capacitance resolution of the whole readout circuit is 10aF/rtHz@1kHz.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128361683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
65 nm BEOL trench etch is apt to suffer the marginal PR issue. It is a big challenge for trench etch process to simultaneously satisfy the requirements for both metal resistance (Rs) and breakdown Voltage (VBD). The copper surface condition of via bottom is a big concern of trench etch process as well. In this paper, we present several electrical parameter issues that occurred at 65 nm trench etch process such as Rs, via resistance (Rc) and VBD. The feasible solutions and related etching mechanisms are also addressed for the above issues from the point view of the improvement of line-edge roughness (LER), within wafer AEI CDU (critical dimension uniformity) and interface conditions of via-bottom.
{"title":"A study of 65nm BEOL trench etch issues","authors":"Linlin Zhao, Manhua Shen, Qiu-hua Han, Hai-yang Zhang, Shih-Mou Chang","doi":"10.1109/ICSICT.2008.4734747","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734747","url":null,"abstract":"65 nm BEOL trench etch is apt to suffer the marginal PR issue. It is a big challenge for trench etch process to simultaneously satisfy the requirements for both metal resistance (Rs) and breakdown Voltage (VBD). The copper surface condition of via bottom is a big concern of trench etch process as well. In this paper, we present several electrical parameter issues that occurred at 65 nm trench etch process such as Rs, via resistance (Rc) and VBD. The feasible solutions and related etching mechanisms are also addressed for the above issues from the point view of the improvement of line-edge roughness (LER), within wafer AEI CDU (critical dimension uniformity) and interface conditions of via-bottom.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128622991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734493
A. Kinoshita
Schottky barrier MOSFETs (SBTs) have attracted much attention as a candidate for achieving high-performance in future ULSIs. Their potential advantages are low electrode resistance, short channel effect immunity and high carrier injection velocity, and many more. The major obstacle is however, to reduce the Schottky barrier height (øb) in these devices (both n- and pMOSFETs) since large øb severely limits the current drivability. One promising candidate to achieve the low øb, is dopant-segregated Schottky (DSS) junctions. In this paper, we report process and characteristics of DSS junctions.
{"title":"Dopant-segregated source/drain technology for high-performance CMOS","authors":"A. Kinoshita","doi":"10.1109/ICSICT.2008.4734493","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734493","url":null,"abstract":"Schottky barrier MOSFETs (SBTs) have attracted much attention as a candidate for achieving high-performance in future ULSIs. Their potential advantages are low electrode resistance, short channel effect immunity and high carrier injection velocity, and many more. The major obstacle is however, to reduce the Schottky barrier height (øb) in these devices (both n- and pMOSFETs) since large øb severely limits the current drivability. One promising candidate to achieve the low øb, is dopant-segregated Schottky (DSS) junctions. In this paper, we report process and characteristics of DSS junctions.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129301424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734965
Yundong He, Zhangming Zhu, Yintang Yang
Based on Simulink tool, the high-level model of 2.0A/375 kHz current controlling PWM buck converter is presented adopting state vector averaging method. The high-level model is verified using Beiling 2¿m/20V bipolar process and 30V/5.0A P-ch power MOSFET. The measured results show that the typical conversion efficiency can be over 90%, the maximum ripple value of output voltage is 32.8 mV, the output voltage error can be in the range of ±3%, the maximum output voltage load regulation is less than 0.3% and the PWM frequency falls to 11.01 kHz during the output circuits being shorted. The current controlling PWM buck DC/DC converter high-level model has been verified by the good performance of the 2.0A/375 kHz buck DC/DC converter.
{"title":"A high efficiency PWM buck DC/DC converter high-level model and verification","authors":"Yundong He, Zhangming Zhu, Yintang Yang","doi":"10.1109/ICSICT.2008.4734965","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734965","url":null,"abstract":"Based on Simulink tool, the high-level model of 2.0A/375 kHz current controlling PWM buck converter is presented adopting state vector averaging method. The high-level model is verified using Beiling 2¿m/20V bipolar process and 30V/5.0A P-ch power MOSFET. The measured results show that the typical conversion efficiency can be over 90%, the maximum ripple value of output voltage is 32.8 mV, the output voltage error can be in the range of ±3%, the maximum output voltage load regulation is less than 0.3% and the PWM frequency falls to 11.01 kHz during the output circuits being shorted. The current controlling PWM buck DC/DC converter high-level model has been verified by the good performance of the 2.0A/375 kHz buck DC/DC converter.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126861747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734579
Yuan Yuan, Chen Yang, T. Ren, J. Zhan, Li-tian Liu, A. Wang
Magnetic inductor has becoming a new promising way to achieve super compact, high performance on-chip spiral inductors for RF ICs. Systematical design and simulation for typical on-chip stacked inductors with magnetic materials are conducted in this paper. Different structure and material parameters are simulated and analyzed. Improvements of the inductance L up to +20% have been achieved over multi-GHz.
{"title":"Design and simulation of on-chip magnetic inductors for RF ICs","authors":"Yuan Yuan, Chen Yang, T. Ren, J. Zhan, Li-tian Liu, A. Wang","doi":"10.1109/ICSICT.2008.4734579","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734579","url":null,"abstract":"Magnetic inductor has becoming a new promising way to achieve super compact, high performance on-chip spiral inductors for RF ICs. Systematical design and simulation for typical on-chip stacked inductors with magnetic materials are conducted in this paper. Different structure and material parameters are simulated and analyzed. Improvements of the inductance L up to +20% have been achieved over multi-GHz.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126961453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734744
J. Yuan, V. Chan, M. Eller, N. Rovedo, H.K. Lee, Y. Gao, V. Sardesai, N. Kanike, V. Vidya, O. Kwon, O. Kwon, J. Yan, S. Fang, W. Wille, H. Wang, Y. Chow, R. Booth, T. Kebede, W. Clark, H. Mo, C. Ryou, J. Liang, J. Yang, C.W. Lai, S.S. Naragad, O. Gluschenkov, M. Visokay, C. Radens, S. Deshpande, H. Shang, Y. Li, N. Cave, J. Sudijono, J. Ku, R. Divakaruni
This paper presents a cost-effective low power 45 nm bulk technology platform, primarily designed to serve the wireless multimedia and consumer electronics need. This technology platform features carbon co-IIP in the nMOS halo, laser annealing scheme, stress liner on the 45°-rotated wafer (<100>) for process simplicity to achieve high device performance and low leakage together. Drive current as high as 650/320 uA/um at Ioff of 0.5 nA/um with Vdd=1.1V has been achieved for both NMOS and PMOS respectively. Ring oscillator speed (FO=1) has been boosted up by 30% with the device optimization. SRAM Vt mismatch is also improved by 10% with carbon co-IIP with good SRAM characteristics and low leakage current in 0.299 um2 cell.
{"title":"A 45nm low power bulk technology featuring carbon co-implantation and laser anneal on 45°-rotated substrate","authors":"J. Yuan, V. Chan, M. Eller, N. Rovedo, H.K. Lee, Y. Gao, V. Sardesai, N. Kanike, V. Vidya, O. Kwon, O. Kwon, J. Yan, S. Fang, W. Wille, H. Wang, Y. Chow, R. Booth, T. Kebede, W. Clark, H. Mo, C. Ryou, J. Liang, J. Yang, C.W. Lai, S.S. Naragad, O. Gluschenkov, M. Visokay, C. Radens, S. Deshpande, H. Shang, Y. Li, N. Cave, J. Sudijono, J. Ku, R. Divakaruni","doi":"10.1109/ICSICT.2008.4734744","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734744","url":null,"abstract":"This paper presents a cost-effective low power 45 nm bulk technology platform, primarily designed to serve the wireless multimedia and consumer electronics need. This technology platform features carbon co-IIP in the nMOS halo, laser annealing scheme, stress liner on the 45°-rotated wafer (<100>) for process simplicity to achieve high device performance and low leakage together. Drive current as high as 650/320 uA/um at Ioff of 0.5 nA/um with Vdd=1.1V has been achieved for both NMOS and PMOS respectively. Ring oscillator speed (FO=1) has been boosted up by 30% with the device optimization. SRAM Vt mismatch is also improved by 10% with carbon co-IIP with good SRAM characteristics and low leakage current in 0.299 um2 cell.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130653192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4735017
Jie Jin, Dun Shan, X. Cui
In this paper, we propose a simple but effective method to reduce the power in the design of the speed negotiation algorithm(SNA). Based on thoroughly analyzing the algorithm and the results of simulation, we identify the large timers, the most commonly used in the SNA, as the most power consuming parts. This paper further develops a partition algorithm to tackle the power issue of the large timers. Utilizing the proposed method, we can reduce the power by 30% as opposed to only 19% if directly applying clock-gating methodology. Combined with clock-gating methodology, we can get 38% reduction in power with no more than 5% increase in area.
{"title":"A method to lower power in speed negotiation algorithm of fiber channel","authors":"Jie Jin, Dun Shan, X. Cui","doi":"10.1109/ICSICT.2008.4735017","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4735017","url":null,"abstract":"In this paper, we propose a simple but effective method to reduce the power in the design of the speed negotiation algorithm(SNA). Based on thoroughly analyzing the algorithm and the results of simulation, we identify the large timers, the most commonly used in the SNA, as the most power consuming parts. This paper further develops a partition algorithm to tackle the power issue of the large timers. Utilizing the proposed method, we can reduce the power by 30% as opposed to only 19% if directly applying clock-gating methodology. Combined with clock-gating methodology, we can get 38% reduction in power with no more than 5% increase in area.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123979925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4735072
Li Li, Xiang Han, Wengang Wu, F. Ding, Qinghua Chen
As a first step to realize novel cantilevers to be used in the atomic force microscopy (AFM), we have fabricated a Poly-Si cantilever with enhanced high-aspect-ratio nanotips. The tips with well controlled dimensions are fabricated by crossed spacer technology and the flexibility of the cantilever and the nanotips according to demand can be easily realized by designing the pattern and tuning the etching time in the fabrication process. The tips on the cantilever, with 1.2 ¿m height, have a high aspect ratio of 7:1. This nanotip on the cantilevers can not only be used as an AFM probe, it can also be extended to any two-dimensional nanotip arrays to be widely used in biomedical field such as biomedical specimen micro-extractions and transportations.
{"title":"Fabrication of novel cantilever with nanotip for AFM applications","authors":"Li Li, Xiang Han, Wengang Wu, F. Ding, Qinghua Chen","doi":"10.1109/ICSICT.2008.4735072","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4735072","url":null,"abstract":"As a first step to realize novel cantilevers to be used in the atomic force microscopy (AFM), we have fabricated a Poly-Si cantilever with enhanced high-aspect-ratio nanotips. The tips with well controlled dimensions are fabricated by crossed spacer technology and the flexibility of the cantilever and the nanotips according to demand can be easily realized by designing the pattern and tuning the etching time in the fabrication process. The tips on the cantilever, with 1.2 ¿m height, have a high aspect ratio of 7:1. This nanotip on the cantilevers can not only be used as an AFM probe, it can also be extended to any two-dimensional nanotip arrays to be widely used in biomedical field such as biomedical specimen micro-extractions and transportations.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"27 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120845230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734722
E. Charbon
Four years ago [1] we assessed the status of CMOS imaging for high-speed applications. We also gave an outlook of the near future in high-speed imaging. In this paper we revisit the topic of high speed imaging in a slightly different angle and make the point of recent developments in the field, with emphasis to bioimaging applications.
{"title":"High speed cmos imaging: Four years later","authors":"E. Charbon","doi":"10.1109/ICSICT.2008.4734722","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734722","url":null,"abstract":"Four years ago [1] we assessed the status of CMOS imaging for high-speed applications. We also gave an outlook of the near future in high-speed imaging. In this paper we revisit the topic of high speed imaging in a slightly different angle and make the point of recent developments in the field, with emphasis to bioimaging applications.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114327817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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