Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734699
Bei Li, Yan Zhu, Huimei Zhou, Jianlin Liu
Metal-oxide-semiconductor field effect transistor (MOSFET) memories with self-aligned hetero-nanocrystals (TiSi2/Si and Ge/Si) as the floating gates were fabricated and characterized. Better performances were found in hetero-nanocrystal memory, including longer retention time, larger storage capability and improved writing efficiency.
{"title":"High-performance hetero-nanocrystal memories","authors":"Bei Li, Yan Zhu, Huimei Zhou, Jianlin Liu","doi":"10.1109/ICSICT.2008.4734699","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734699","url":null,"abstract":"Metal-oxide-semiconductor field effect transistor (MOSFET) memories with self-aligned hetero-nanocrystals (TiSi2/Si and Ge/Si) as the floating gates were fabricated and characterized. Better performances were found in hetero-nanocrystal memory, including longer retention time, larger storage capability and improved writing efficiency.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125046323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734988
L. Dai, Zhi-bin Liu, Shao-chi Liang, Meng Yang, Ling-li Wang
Static-random-access-memory(SRAM)-based field programmable gate arrays (FPGAs) consists of 50% ~70% routing resources. A simple programmable interconnect point (PIP) is a switch controlled by SRAM configuration cell connecting two wires. A novel traverse algorithm targeted for the detection of PIP open faults is proposed. Experimental results run on the Fudan design system (FDS) platform show that the algorithm is effective to examine the open faults of the routing paths caused by the PIPs fault configuration.
{"title":"FPGA interconnect testing algorithm based on routing-resource graph","authors":"L. Dai, Zhi-bin Liu, Shao-chi Liang, Meng Yang, Ling-li Wang","doi":"10.1109/ICSICT.2008.4734988","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734988","url":null,"abstract":"Static-random-access-memory(SRAM)-based field programmable gate arrays (FPGAs) consists of 50% ~70% routing resources. A simple programmable interconnect point (PIP) is a switch controlled by SRAM configuration cell connecting two wires. A novel traverse algorithm targeted for the detection of PIP open faults is proposed. Experimental results run on the Fudan design system (FDS) platform show that the algorithm is effective to examine the open faults of the routing paths caused by the PIPs fault configuration.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116769716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734930
Chungan Peng, Y. Li, Xiaoxin Cui, Xixin Cao, Dunshan Yu
A synthesis frequency inflexion phenomenon of VLSI synthesis process is discussed, and then a VLSI structural optimization method with its workflow based on the analysis of synthesis frequency infrexion and register insertion is proposed. Registers are usually used for sequential synchronization and increasing maximum operating frequency, but in this issue, they are utilized to avoid excessively high combinational logic expenditure. In the H.264 macroblock-level SAD tree case, 50.6% improvement in speed is achieved at the expense of 2.9% increment in area. This method contains no complex algorithm, but exhibits good operability and generality. It is very suitable and useful for complicated VLSI structural design and/or their critical path optimization.
{"title":"A VLSI structural optimization method and workflow based on synthesis frequency inflexion","authors":"Chungan Peng, Y. Li, Xiaoxin Cui, Xixin Cao, Dunshan Yu","doi":"10.1109/ICSICT.2008.4734930","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734930","url":null,"abstract":"A synthesis frequency inflexion phenomenon of VLSI synthesis process is discussed, and then a VLSI structural optimization method with its workflow based on the analysis of synthesis frequency infrexion and register insertion is proposed. Registers are usually used for sequential synchronization and increasing maximum operating frequency, but in this issue, they are utilized to avoid excessively high combinational logic expenditure. In the H.264 macroblock-level SAD tree case, 50.6% improvement in speed is achieved at the expense of 2.9% increment in area. This method contains no complex algorithm, but exhibits good operability and generality. It is very suitable and useful for complicated VLSI structural design and/or their critical path optimization.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125126325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734479
Wei-lian Guo, Wei Wang, P. Niu, Xiao-yun Li, Xin Yu, Lu-hong Mao, Hongwei Liu, Guang-hua Yang, Ruiliang Song
In this paper, a novel device - MOS-NDR transistor is proposed and fabricated which is composed of four N-channel metal-oxide-semiconductor field effect-transistor (NMOS) devices. This MOS-NDR transistor could exhibit the negative differential resistance (NDR) characteristics similar to the conventional NDR device such as compound material based RTD (resonant tunneling diode) in the current-voltage characteristics by suitably modulating the MOS parameters, at the same time it could realize good modulation effect by the third terminal and has advantages of low working voltage (peak voltage Vp=0.7 V) and high PVCR (Peak to Valley Current Ratio) (nearly 10:1). The design and fabrication of this device are completely compatible with the standard 0.35 ¿m CMOS process, thus can considerably extend the functions of the CMOS circuits into new scope.
本文提出并制作了一种由4个n沟道金属氧化物半导体场效应晶体管(NMOS)组成的新型器件——MOS-NDR晶体管。通过适当调制MOS参数，该MOS-NDR晶体管在电流-电压特性上具有与基于复合材料的谐振隧道二极管(RTD)等传统NDR器件相似的负差分电阻(NDR)特性，同时在第三端实现良好的调制效果，具有工作电压低(峰值电压Vp=0.7 V)和高峰谷电流比(PVCR)(接近10:1)的优点。该器件的设计和制造与标准的0.35 μ m CMOS工艺完全兼容，从而可以将CMOS电路的功能扩展到新的范围。
{"title":"CMOS-NDR transistor","authors":"Wei-lian Guo, Wei Wang, P. Niu, Xiao-yun Li, Xin Yu, Lu-hong Mao, Hongwei Liu, Guang-hua Yang, Ruiliang Song","doi":"10.1109/ICSICT.2008.4734479","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734479","url":null,"abstract":"In this paper, a novel device - MOS-NDR transistor is proposed and fabricated which is composed of four N-channel metal-oxide-semiconductor field effect-transistor (NMOS) devices. This MOS-NDR transistor could exhibit the negative differential resistance (NDR) characteristics similar to the conventional NDR device such as compound material based RTD (resonant tunneling diode) in the current-voltage characteristics by suitably modulating the MOS parameters, at the same time it could realize good modulation effect by the third terminal and has advantages of low working voltage (peak voltage Vp=0.7 V) and high PVCR (Peak to Valley Current Ratio) (nearly 10:1). The design and fabrication of this device are completely compatible with the standard 0.35 ¿m CMOS process, thus can considerably extend the functions of the CMOS circuits into new scope.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125279417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734540
Du Xiaoyang, Dong Yan, J. Liou
A novel dual direction SCR (DDSCR) ESD protection device is implemented in HJTK 0.18-¿m CMOS process without deep N-well or T-well masks. Both parallel and anti-parallel metal routing method of multi-fingered DDSCR is investigated in this paper. It shows that metal routing in layout design plays an important role in the performance of multi-fingered DDSCR due to its symmetrical TLP I-V plot characteristics.
{"title":"Analysis of metal routing technique in a novel dual direction multi-finger SCR ESD protection device","authors":"Du Xiaoyang, Dong Yan, J. Liou","doi":"10.1109/ICSICT.2008.4734540","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734540","url":null,"abstract":"A novel dual direction SCR (DDSCR) ESD protection device is implemented in HJTK 0.18-¿m CMOS process without deep N-well or T-well masks. Both parallel and anti-parallel metal routing method of multi-fingered DDSCR is investigated in this paper. It shows that metal routing in layout design plays an important role in the performance of multi-fingered DDSCR due to its symmetrical TLP I-V plot characteristics.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123858107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734666
A. Chin, H.J. Yang, S.H. Lin, C. Liao, W. Chen, F. Yeh
We have compared the device performance of double-quantum-barrier charge-trapping memory of a TaN/Ir3Si-[HfAlO-LaAlO3]-HfON0.2-[HfAlO-SiO2]-Si device with single barrier non-volatile memory MONOS devices at close EOT. At 150°C under fast 100 ¿s and low ±9 V P/E, the double-quantum-barrier charge-trapping device shows a 3.2 V initial ¿Vth and 2.7 V 10-year extrapolated retention. This retention decay rate is much improved from single barrier device.
我们比较了TaN/Ir3Si-[HfAlO-LaAlO3]- hfon0.2 -[HfAlO-SiO2]- si双量子势垒电荷捕获存储器与单势垒非易失性存储器MONOS器件在接近EOT时的器件性能。在150°C，快速100°s和低±9 V P/E下，双量子势垒电荷捕获装置显示出3.2 V的初始电压和2.7 V的10年外推保留率。这种保留衰减率比单势垒器件有很大提高。
{"title":"Improved high temperature retention and endurance in HfON trapping memory with double quantum barriers","authors":"A. Chin, H.J. Yang, S.H. Lin, C. Liao, W. Chen, F. Yeh","doi":"10.1109/ICSICT.2008.4734666","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734666","url":null,"abstract":"We have compared the device performance of double-quantum-barrier charge-trapping memory of a TaN/Ir<sub>3</sub>Si-[HfAlO-LaAlO<sub>3</sub>]-HfON<sub>0.2</sub>-[HfAlO-SiO<sub>2</sub>]-Si device with single barrier non-volatile memory MONOS devices at close EOT. At 150°C under fast 100 ¿s and low ±9 V P/E, the double-quantum-barrier charge-trapping device shows a 3.2 V initial ¿V<sub>th</sub> and 2.7 V 10-year extrapolated retention. This retention decay rate is much improved from single barrier device.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121240044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734673
J. Pu, D. Chan, B. Cho
We propose one novel approach on engineering floating gate (FG) of Flash memory cell: carbon incorporation into polysilicon FG. This technique demonstrated improvement in retention and larger program/erase Vth window, especially for smaller capacitance coupling ratio cell which is important for future scaled Flash memory cells.
{"title":"A novel floating gate engineering technique for improved data retention of flash memory devices","authors":"J. Pu, D. Chan, B. Cho","doi":"10.1109/ICSICT.2008.4734673","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734673","url":null,"abstract":"We propose one novel approach on engineering floating gate (FG) of Flash memory cell: carbon incorporation into polysilicon FG. This technique demonstrated improvement in retention and larger program/erase Vth window, especially for smaller capacitance coupling ratio cell which is important for future scaled Flash memory cells.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127713724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734539
Y. Zhou, J. Hajjar
Most integrated circuit ESD damages are caused by CDM stresses. This paper discusses CDM failure modes. The most common such failure is damage to the gate oxide in the MOS device. A new methodology that uses a gate oxide damage monitor and modified VFTLP testing is proposed for assessing CDM protection effectiveness and robustness in I/O circuits. A test structure for such an evaluation is also introduced.
{"title":"CDM ESD failure modes and VFTLP testing for protection evaluation","authors":"Y. Zhou, J. Hajjar","doi":"10.1109/ICSICT.2008.4734539","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734539","url":null,"abstract":"Most integrated circuit ESD damages are caused by CDM stresses. This paper discusses CDM failure modes. The most common such failure is damage to the gate oxide in the MOS device. A new methodology that uses a gate oxide damage monitor and modified VFTLP testing is proposed for assessing CDM protection effectiveness and robustness in I/O circuits. A test structure for such an evaluation is also introduced.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132527710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734592
Xin Yu, Shilin Zhang, L. Mao, Weilian Guo, Xiaoli Wang
We reported the standard ¿¿¿ shape negative differential resistance as well as a level and smooth valley region in real space transfer transistor (RSTT) with dual-quantum-well channel, which are formed by ¿-doping GaAs quantum-well and InGaAs/GaAs heterojunction quantum-well. The highest peak-to-valley current ratio (PVCR) of RSTT reaches 4 at room temperature. The highest peak current density transconductance (¿JP/¿VGS) is 130 ms/mm, which demonstrates the control ability of gate to JP. The mechanism of obvious NDR of RSTT can be explained that the hot electron in the InGaAs U-shaped quantum-well channel transfers into V-shaped ¿-doping GaAs quantum-well channel, and the hot electron transfers into gate electrode from V-shaped ¿-doping GaAs quantum-well channel. This novel NDR device would be expected to applied in NDR circuits to instead of RTD+HEMT.
{"title":"Fabrication and DC current-voltage characteristics of real space transfer transistor with dual-quantum-well channel","authors":"Xin Yu, Shilin Zhang, L. Mao, Weilian Guo, Xiaoli Wang","doi":"10.1109/ICSICT.2008.4734592","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734592","url":null,"abstract":"We reported the standard ¿¿¿ shape negative differential resistance as well as a level and smooth valley region in real space transfer transistor (RSTT) with dual-quantum-well channel, which are formed by ¿-doping GaAs quantum-well and InGaAs/GaAs heterojunction quantum-well. The highest peak-to-valley current ratio (PVCR) of RSTT reaches 4 at room temperature. The highest peak current density transconductance (¿JP/¿VGS) is 130 ms/mm, which demonstrates the control ability of gate to JP. The mechanism of obvious NDR of RSTT can be explained that the hot electron in the InGaAs U-shaped quantum-well channel transfers into V-shaped ¿-doping GaAs quantum-well channel, and the hot electron transfers into gate electrode from V-shaped ¿-doping GaAs quantum-well channel. This novel NDR device would be expected to applied in NDR circuits to instead of RTD+HEMT.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132736626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734848
Yuan Liu, Zhi-gang Wang, Jie Wen, B. Yan, R. Xu
Using the GaAs MMICs, other components and advanced package techniques, we realized a compact transceiver module with high power (about 35 dBm), receiver noise figure less than 4.5 dB and bandwidth 1% in Ka-band operating frequencies. This module consists of 15 MMICs and over 100 components, and demonstrates narrow bandwidth with high power in millimeter-wave transceiver module. This work has also laid a good foundation for the technology of combining the MMIC and other component for a versatile millimeter-wave transceiver module.
{"title":"A compact transceiver for narrow bandwidth and high power Ka-band application","authors":"Yuan Liu, Zhi-gang Wang, Jie Wen, B. Yan, R. Xu","doi":"10.1109/ICSICT.2008.4734848","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734848","url":null,"abstract":"Using the GaAs MMICs, other components and advanced package techniques, we realized a compact transceiver module with high power (about 35 dBm), receiver noise figure less than 4.5 dB and bandwidth 1% in Ka-band operating frequencies. This module consists of 15 MMICs and over 100 components, and demonstrates narrow bandwidth with high power in millimeter-wave transceiver module. This work has also laid a good foundation for the technology of combining the MMIC and other component for a versatile millimeter-wave transceiver module.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133904560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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