Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4735050
Kanwen Wang, Meng Yang, Lingli Wang, Xuegong Zhou, J. Tong
The cluster-based FPGA can significantly improve timing and routability. Packing is introduced in the CAD flow to pack logic elements into clusters. In order to reduce unnecessary connectivity within a cluster, sparse crossbar FPGA architectures are under investigation. This paper proposes a novel packing algorithm using direct graph searching method and connection gain function. Experimental results show that half populated crossbar FPGA architecture achieves 7% area improvement compared to fully populated counterpart with only 3% number of external nets overhead.
{"title":"A novel packing algorithm for sparse crossbar FPGA architectures","authors":"Kanwen Wang, Meng Yang, Lingli Wang, Xuegong Zhou, J. Tong","doi":"10.1109/ICSICT.2008.4735050","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4735050","url":null,"abstract":"The cluster-based FPGA can significantly improve timing and routability. Packing is introduced in the CAD flow to pack logic elements into clusters. In order to reduce unnecessary connectivity within a cluster, sparse crossbar FPGA architectures are under investigation. This paper proposes a novel packing algorithm using direct graph searching method and connection gain function. Experimental results show that half populated crossbar FPGA architecture achieves 7% area improvement compared to fully populated counterpart with only 3% number of external nets overhead.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129699802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734473
Runsheng Wang, J. Zhuge, Ru Huang, Liangliang Zhang, Dong-Won Kim, Xing Zhang, Donggun Park, Yangyuan Wang
In this paper, experimental studies on the carrier transport in silicon nanowire transistors (SNWTs) are reported, demonstrating their great potential as an alternative device structure for near-ballistic transport from top-down approach. Both ballistic efficiency and apparent mobility were characterized. A modified experimental extraction methodology for SNWTs is proposed, which takes into account the impact of quantum contact resistance. The highest ballistic efficiency is observed in sub-40 nm n-channel SNWTs due to their quasi-1D carrier transport. The apparent mobility is also extracted in comparison with the ballistic limit, which indicates that the gate-all-around SNWT can really be considered as a promising device architecture in close proximity to the ballistic transport.
{"title":"An experimental study on carrier transport in silicon nanowire transistors: How close to the ballistic limit?","authors":"Runsheng Wang, J. Zhuge, Ru Huang, Liangliang Zhang, Dong-Won Kim, Xing Zhang, Donggun Park, Yangyuan Wang","doi":"10.1109/ICSICT.2008.4734473","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734473","url":null,"abstract":"In this paper, experimental studies on the carrier transport in silicon nanowire transistors (SNWTs) are reported, demonstrating their great potential as an alternative device structure for near-ballistic transport from top-down approach. Both ballistic efficiency and apparent mobility were characterized. A modified experimental extraction methodology for SNWTs is proposed, which takes into account the impact of quantum contact resistance. The highest ballistic efficiency is observed in sub-40 nm n-channel SNWTs due to their quasi-1D carrier transport. The apparent mobility is also extracted in comparison with the ballistic limit, which indicates that the gate-all-around SNWT can really be considered as a promising device architecture in close proximity to the ballistic transport.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128698401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734718
Liangchen Wang, X. Yi, Xiaodong Wang, Guohong Wang, Jinmin Li
In this paper fabrication of high power light emitting diodes (LEDs) with combined transparent electrodes on both P-GaN and N-GaN have been demonstrated. Simulation and experimental results show that comparing with traditional metal N electrodes the efficacy of LEDs with transparent N electrode is increased by more than 10% and it is easier in process than the other techniques. Further more, combining the transparent electrodes with dielectric anti-reflection film, the extraction efficiency can be improved by 5%. At the same time, the transparent electrodes were protected by the dielectric film and the reliability of LEDs can be improved.
{"title":"Combined transparent electrodes for high power GaN-based LEDs with long life time","authors":"Liangchen Wang, X. Yi, Xiaodong Wang, Guohong Wang, Jinmin Li","doi":"10.1109/ICSICT.2008.4734718","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734718","url":null,"abstract":"In this paper fabrication of high power light emitting diodes (LEDs) with combined transparent electrodes on both P-GaN and N-GaN have been demonstrated. Simulation and experimental results show that comparing with traditional metal N electrodes the efficacy of LEDs with transparent N electrode is increased by more than 10% and it is easier in process than the other techniques. Further more, combining the transparent electrodes with dielectric anti-reflection film, the extraction efficiency can be improved by 5%. At the same time, the transparent electrodes were protected by the dielectric film and the reliability of LEDs can be improved.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129523170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734535
T. Chiang
Based on the exact resultant solution of two dimensional Poisson equation, a new analytical subthreshold behavior model consisting of two dimensional potential, threshold voltage and subthreshold swing for the dual material gate (DMG) SOI MESFETs is developed. The model is verified by the good agreement when compared with the numerical simulation of device simulator MEDICI. The model not only offers the physical insight into device physics but also provides the efficient device model for the circuit simulation.
基于二维泊松方程的精确结果解，建立了双材料栅极(DMG) SOI mesfet的二维电位、阈值电压和阈值摆幅的解析亚阈行为模型。通过与器件模拟器MEDICI的数值仿真比较，验证了模型的一致性。该模型不仅提供了对器件物理特性的物理洞察，而且为电路仿真提供了有效的器件模型。
{"title":"The new analytical subthreshold behavior model for dual material gate (DMG) SOI MESFET","authors":"T. Chiang","doi":"10.1109/ICSICT.2008.4734535","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734535","url":null,"abstract":"Based on the exact resultant solution of two dimensional Poisson equation, a new analytical subthreshold behavior model consisting of two dimensional potential, threshold voltage and subthreshold swing for the dual material gate (DMG) SOI MESFETs is developed. The model is verified by the good agreement when compared with the numerical simulation of device simulator MEDICI. The model not only offers the physical insight into device physics but also provides the efficient device model for the circuit simulation.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129554966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734522
Gang Zhang, W. Yoo
In this paper, an analytical model is proposed to study the carrier recombination-generation (R-G) processes in silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFET's). The correlations of the carrier lifetimes and the external perturbation rates have been investigated to examine the applicability and accuracy of techniques for carrier lifetimes measurement in device characterization and modeling. The credibility of the proposed model is supported by the consistent experimental and simulation results.
{"title":"An analytical model for carrier recombination and generation lifetimes measurement in SOI MOSFET’s","authors":"Gang Zhang, W. Yoo","doi":"10.1109/ICSICT.2008.4734522","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734522","url":null,"abstract":"In this paper, an analytical model is proposed to study the carrier recombination-generation (R-G) processes in silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFET's). The correlations of the carrier lifetimes and the external perturbation rates have been investigated to examine the applicability and accuracy of techniques for carrier lifetimes measurement in device characterization and modeling. The credibility of the proposed model is supported by the consistent experimental and simulation results.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129564615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734773
Yan-ping Liu, Fei Li
Metal clipping issue was observed in semiconductor manufacturing, which will result in the electronic property failure of metal line. The process parameters of HDP FSG deposition were investigated in order to discover the mechanism of metal clipping. The results indicated that ion bombardment effect is the dominated factor for metal clipping, it also accelerate the chemical etch of F ions. According to the standard manufacturing procedure, several progresses were used to avoid the metal clipping issue successfully.
{"title":"Investigation on the metal-clipping issue after FSG deposition","authors":"Yan-ping Liu, Fei Li","doi":"10.1109/ICSICT.2008.4734773","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734773","url":null,"abstract":"Metal clipping issue was observed in semiconductor manufacturing, which will result in the electronic property failure of metal line. The process parameters of HDP FSG deposition were investigated in order to discover the mechanism of metal clipping. The results indicated that ion bombardment effect is the dominated factor for metal clipping, it also accelerate the chemical etch of F ions. According to the standard manufacturing procedure, several progresses were used to avoid the metal clipping issue successfully.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127199548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734530
Jin He, Yan Song, Feng Liu, Feilong Liu, Lining Zhang, Jian Zhang, Xing Zhang
A complete surface potential-based current-voltage and capacitance-voltage core model for cylindrical undoped surrounding-gate (SRG) MOSFETs is presented in this paper. This model allows the current-voltage (IV) and capacitance-voltage (CV) characteristics to be adequately described by a single set of the equations in terms of the surface potential. The model is valid for all operation regions and predicted SRG-MOSFET¿s characteristics by the 3-D numerical simulation.
{"title":"A complete surface potential-based current-voltage and capacitance-voltage core model for undoped surrounding-gate MOSFETs","authors":"Jin He, Yan Song, Feng Liu, Feilong Liu, Lining Zhang, Jian Zhang, Xing Zhang","doi":"10.1109/ICSICT.2008.4734530","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734530","url":null,"abstract":"A complete surface potential-based current-voltage and capacitance-voltage core model for cylindrical undoped surrounding-gate (SRG) MOSFETs is presented in this paper. This model allows the current-voltage (IV) and capacitance-voltage (CV) characteristics to be adequately described by a single set of the equations in terms of the surface potential. The model is valid for all operation regions and predicted SRG-MOSFET¿s characteristics by the 3-D numerical simulation.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129110267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4735063
R. Nikolic, A. Conway, C. Reinhardt, R. Graff, T. Wang, N. Deo, C. L. Cheung
This work describes an innovative solid state device structure that leverages advanced semiconductor fabrication technology to produce an efficient device for thermal neutron detection which we have coined the ¿Pillar Detector¿. State-of-the-art thermal neutron detectors have shortcomings in simultaneously achieving high efficiency, low operating voltage while maintaining adequate fieldability performance. By using a three dimensional silicon PIN diode pillar array filled with isotopic 10boron (10B), a high efficiency device is theoretically possible. Here we review the design considerations for going from a 2-D to 3-D device and discuss the materials trade-offs. The relationship between the geometrical features and efficiency within our 3-D device is investigated by Monte Carlo radiation transport method coupled with finite element drift-diffusion carrier transport simulations. To benchmark our simulations and validate the predicted efficiency scaling, experimental results of a prototype device are illustrated. The fabricated pillar structures reported in this work are composed of 2 ¿m diameter silicon pillars with a 2 ¿m spacing and pillar height of 12 ¿m. The pillar detector with a 12 ¿m height achieved a thermal neutron detection efficiency of 7.3% at a reverse bias of - 2 V.
{"title":"Pillar structured thermal neutron detector","authors":"R. Nikolic, A. Conway, C. Reinhardt, R. Graff, T. Wang, N. Deo, C. L. Cheung","doi":"10.1109/ICSICT.2008.4735063","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4735063","url":null,"abstract":"This work describes an innovative solid state device structure that leverages advanced semiconductor fabrication technology to produce an efficient device for thermal neutron detection which we have coined the ¿Pillar Detector¿. State-of-the-art thermal neutron detectors have shortcomings in simultaneously achieving high efficiency, low operating voltage while maintaining adequate fieldability performance. By using a three dimensional silicon PIN diode pillar array filled with isotopic 10boron (10B), a high efficiency device is theoretically possible. Here we review the design considerations for going from a 2-D to 3-D device and discuss the materials trade-offs. The relationship between the geometrical features and efficiency within our 3-D device is investigated by Monte Carlo radiation transport method coupled with finite element drift-diffusion carrier transport simulations. To benchmark our simulations and validate the predicted efficiency scaling, experimental results of a prototype device are illustrated. The fabricated pillar structures reported in this work are composed of 2 ¿m diameter silicon pillars with a 2 ¿m spacing and pillar height of 12 ¿m. The pillar detector with a 12 ¿m height achieved a thermal neutron detection efficiency of 7.3% at a reverse bias of - 2 V.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122351821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Stiction as one of the most failures both in MEMS fabrication and operation has been widely studied. With the decrease in the dimension and material, the ubiquitous surface effect between the device and substrate has become more and more effective. Surface-micromachined structures formed by the wet etching of sacrificial layers are commonly plagued by problems of sticking to the substrate. This paper presents a useful diagnosis system for fully detecting and characterizing the stiction failure occurring in MEMS. The system consists of an LDV (laser Doppler vibrometer), a chamber with controllable environment such as pressure and temperature, and a diagnosis program developed by Matlab software. Full knowledge about the stiction, including its position, shape, stiction releasing configuration and probability of re-stiction can be accessed using the system. We also present an experimental way to analyze two important forces of the surface effect: the capillary force and the van der Waals force. The experimental diagnosis methodology and theoretical summary could provide a useful reference for detecting and predicting the stiction failure of micro-structures.
{"title":"Detection of stiction of suspending structures in MEMS by A Laser Doppler Vibrometer systems","authors":"Junwen Liu, Qing‐An Huang, Jing Song, Jie-ying Tang","doi":"10.1109/ICSICT.2008.4735092","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4735092","url":null,"abstract":"Stiction as one of the most failures both in MEMS fabrication and operation has been widely studied. With the decrease in the dimension and material, the ubiquitous surface effect between the device and substrate has become more and more effective. Surface-micromachined structures formed by the wet etching of sacrificial layers are commonly plagued by problems of sticking to the substrate. This paper presents a useful diagnosis system for fully detecting and characterizing the stiction failure occurring in MEMS. The system consists of an LDV (laser Doppler vibrometer), a chamber with controllable environment such as pressure and temperature, and a diagnosis program developed by Matlab software. Full knowledge about the stiction, including its position, shape, stiction releasing configuration and probability of re-stiction can be accessed using the system. We also present an experimental way to analyze two important forces of the surface effect: the capillary force and the van der Waals force. The experimental diagnosis methodology and theoretical summary could provide a useful reference for detecting and predicting the stiction failure of micro-structures.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130605307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734603
Bao Liu
Carbon Nanotube (CNT) interconnects provide one of the most promising on-chip interconnect techniques for future VLSI systems, although significant process and runtime variabilities remain challenging for CNT interconnects. In this paper, we propose a performance variation adaptive differential signaling scheme, particularly for carbon nanotube bundle on-chip interconnects. Estimation based on published data demonstrate 37% signal propagation performance variation reduction achieved by the proposed scheme implemented in CNT bundles compared with CNT interconnects with the conventional signaling scheme.
{"title":"Performance variation adaptive differential signaling via Carbon Nanotube bundles","authors":"Bao Liu","doi":"10.1109/ICSICT.2008.4734603","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734603","url":null,"abstract":"Carbon Nanotube (CNT) interconnects provide one of the most promising on-chip interconnect techniques for future VLSI systems, although significant process and runtime variabilities remain challenging for CNT interconnects. In this paper, we propose a performance variation adaptive differential signaling scheme, particularly for carbon nanotube bundle on-chip interconnects. Estimation based on published data demonstrate 37% signal propagation performance variation reduction achieved by the proposed scheme implemented in CNT bundles compared with CNT interconnects with the conventional signaling scheme.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132134741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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