Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206279
M. Fathipour, N. Peyvast, Reza Azadvari
In this paper we have investigated the effectiveness of employing the Single Field-Plate (SFP) technique to enhance the breakdown voltage (BV) of AlGaN/GaN power High Electron Mobility Transistors (HEMTs).A systematic procedure is provided for designing the SFP device, using two dimensional (2-D) simulation to obtain the maximum improvement in the drain-source current (IDS) and to achieve maximum breakdown voltage. It is found that significantly higher breakdown voltages and IDS can be achieved by just raising the thickness of the passivation layer Si3N4 beneath SFP (t) and raising SFP length (Lsfp) between the source and drain. We demonstrate that when a single field-plate connected to the source is employed, both breakdown voltage and IDS can be enhanced by optimizing the passivation layer Si3N4 thickness beneath the SFP as well as the SFP geometry.
{"title":"Improving performance in single field plate power High Electron Mobility Transistors (HEMTs) based on AlGaN/GaN","authors":"M. Fathipour, N. Peyvast, Reza Azadvari","doi":"10.1109/ASQED.2009.5206279","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206279","url":null,"abstract":"In this paper we have investigated the effectiveness of employing the Single Field-Plate (SFP) technique to enhance the breakdown voltage (BV) of AlGaN/GaN power High Electron Mobility Transistors (HEMTs).A systematic procedure is provided for designing the SFP device, using two dimensional (2-D) simulation to obtain the maximum improvement in the drain-source current (IDS) and to achieve maximum breakdown voltage. It is found that significantly higher breakdown voltages and IDS can be achieved by just raising the thickness of the passivation layer Si3N4 beneath SFP (t) and raising SFP length (Lsfp) between the source and drain. We demonstrate that when a single field-plate connected to the source is employed, both breakdown voltage and IDS can be enhanced by optimizing the passivation layer Si3N4 thickness beneath the SFP as well as the SFP geometry.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120947517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206238
M. A. Ismail, I. M. Nasir, R. Ismail
Temperature effect is one of the critical factors in manufacturing variability which could affect the designed circuit. This paper presents a MOSFET mismatch model with the consideration of temperature variations using physical based SPICE model parameters. The model development includes the mismatch measurement at different temperatures and enhancement of standard device model card. Mismatch temperature coefficients with respect to threshold voltage and carrier mobility are used to improve the prediction of mismatch model. The comparison between measured and Monte Carlo simulated data is presented for the verification purpose. The model is applied into the circuit design example to show the significant of the extracted mismatch temperature coefficients.
{"title":"Modeling of temperature variations in MOSFET mismatch for circuit simulations","authors":"M. A. Ismail, I. M. Nasir, R. Ismail","doi":"10.1109/ASQED.2009.5206238","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206238","url":null,"abstract":"Temperature effect is one of the critical factors in manufacturing variability which could affect the designed circuit. This paper presents a MOSFET mismatch model with the consideration of temperature variations using physical based SPICE model parameters. The model development includes the mismatch measurement at different temperatures and enhancement of standard device model card. Mismatch temperature coefficients with respect to threshold voltage and carrier mobility are used to improve the prediction of mismatch model. The comparison between measured and Monte Carlo simulated data is presented for the verification purpose. The model is applied into the circuit design example to show the significant of the extracted mismatch temperature coefficients.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124757946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206267
N. H. Seng, Koo Sang Sool
This paper presents an investigation of low oxide breakdown voltage on Polysilicon-Oxide-Diffusion (POD) capacitor. The dielectric was 7nm thermal oxide which was grown simultaneously for MOS transistor as gate oxide. The V-Ramp measurement showed bimodal distribution of Vbd with one circular patch having ≪7V instead of the target Vbd (10V). The size of the patch depends on the POD capacitor area. This behavior was not observed on gate oxide of MOS transistor and 22.5nm POD capacitor. Process partition check, including wafer orientation and wafer slot arrangement was conducted. The specific process step causing the patch signature has been identified successfully.
{"title":"Investigation of low Vbd on 7nm oxide POD capacitor","authors":"N. H. Seng, Koo Sang Sool","doi":"10.1109/ASQED.2009.5206267","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206267","url":null,"abstract":"This paper presents an investigation of low oxide breakdown voltage on Polysilicon-Oxide-Diffusion (POD) capacitor. The dielectric was 7nm thermal oxide which was grown simultaneously for MOS transistor as gate oxide. The V-Ramp measurement showed bimodal distribution of Vbd with one circular patch having ≪7V instead of the target Vbd (10V). The size of the patch depends on the POD capacitor area. This behavior was not observed on gate oxide of MOS transistor and 22.5nm POD capacitor. Process partition check, including wafer orientation and wafer slot arrangement was conducted. The specific process step causing the patch signature has been identified successfully.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122871061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206295
Xiaoxiao Zhang, A. Bermak, F. Boussaid
Low-power design is essential for computation-intensive systems such as Digital Signal Processors (DSP) as well as battery-powered devices. This paper presents a novel low-power multiplier architecture, which exploits the effective dynamic range of the input data and performs a run-time multi-precision multiplication. Block-wise shutdown and voltage scaling techniques are combined to disable unused resources and adjust the supply voltage and clock frequency to reduce power consumption. This results in nearly a cubic reduction in dynamic power dissipation. Furthermore, by using modified Booth encoding scheme, partial products generating algorithm, and compression topology, our multiplier achieves both delay and power reduction. The design is synthesized using TSMC 0:18µm standard cell library and evaluated in Synopsys design environment. Reported results show that our multiplier achieves up to 75% power reduction with less than 10% overhead in terms of silicon area.
{"title":"Power optimization in multipliers using multi-precision combined with voltage scaling techniques","authors":"Xiaoxiao Zhang, A. Bermak, F. Boussaid","doi":"10.1109/ASQED.2009.5206295","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206295","url":null,"abstract":"Low-power design is essential for computation-intensive systems such as Digital Signal Processors (DSP) as well as battery-powered devices. This paper presents a novel low-power multiplier architecture, which exploits the effective dynamic range of the input data and performs a run-time multi-precision multiplication. Block-wise shutdown and voltage scaling techniques are combined to disable unused resources and adjust the supply voltage and clock frequency to reduce power consumption. This results in nearly a cubic reduction in dynamic power dissipation. Furthermore, by using modified Booth encoding scheme, partial products generating algorithm, and compression topology, our multiplier achieves both delay and power reduction. The design is synthesized using TSMC 0:18µm standard cell library and evaluated in Synopsys design environment. Reported results show that our multiplier achieves up to 75% power reduction with less than 10% overhead in terms of silicon area.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127197965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206254
Yawen Dai, Quan Wang, Xiaoqiang Li
Energy efficiency has been known as the most important problem in wireless sensor networks. However, different applications need different energy efficiency protocols. A centralized wireless sensor network with mesh topology can enable the reliable monitoring of a variety of environments, such as plant monitoring, city traffic monitoring. In this paper, we propose the MEBRSS (Mesh Network Energy Balancing Route Scheduling) algorithm for the network of this type. This algorithm considers both the traffic and the remaining power of all nodes. In addition, the shortest path is selected after such considerations to meet the delay requirement of many applications. The algorithm computes an energy consumption balancing factor for each node, which can represent a balance of the traffic and the remaining energy of each node. We use several matrices to describe the relative information to make the decision, which makes the algorithm simple and efficient. The simulation shows good result for its applicability.
在无线传感器网络中，能量效率一直是最重要的问题。然而，不同的应用需要不同的能效协议。具有网状拓扑结构的集中式无线传感器网络可以实现各种环境的可靠监控，如工厂监控、城市交通监控等。本文针对这类网络提出了MEBRSS (Mesh Network Energy Balancing Route Scheduling)算法。该算法同时考虑了所有节点的流量和剩余功率。此外，考虑这些因素后选择最短路径，以满足许多应用的延迟要求。该算法为每个节点计算一个能量消耗平衡因子，该因子可以表示每个节点的流量和剩余能量的平衡。我们使用多个矩阵来描述相关信息来进行决策，使得算法简单高效。仿真结果表明，该方法具有较好的适用性。
{"title":"MEBRS: Energy balancing route scheduling in centralized wireless sensor networks","authors":"Yawen Dai, Quan Wang, Xiaoqiang Li","doi":"10.1109/ASQED.2009.5206254","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206254","url":null,"abstract":"Energy efficiency has been known as the most important problem in wireless sensor networks. However, different applications need different energy efficiency protocols. A centralized wireless sensor network with mesh topology can enable the reliable monitoring of a variety of environments, such as plant monitoring, city traffic monitoring. In this paper, we propose the MEBRSS (Mesh Network Energy Balancing Route Scheduling) algorithm for the network of this type. This algorithm considers both the traffic and the remaining power of all nodes. In addition, the shortest path is selected after such considerations to meet the delay requirement of many applications. The algorithm computes an energy consumption balancing factor for each node, which can represent a balance of the traffic and the remaining energy of each node. We use several matrices to describe the relative information to make the decision, which makes the algorithm simple and efficient. The simulation shows good result for its applicability.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124088503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206236
B. Davaji, M. Fathipour, M. Vadizadeh
In this paper we review the operational principles of silicon opening switch (SOS) process the utilizing realistic physical models provided by a commercial TCAD tool. We discuses qualitatively the difference between silicon opening process and conventional junction recovery mode. We show that p-n junction has no effect on current interruption.
{"title":"A numerical study of silicon opening process","authors":"B. Davaji, M. Fathipour, M. Vadizadeh","doi":"10.1109/ASQED.2009.5206236","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206236","url":null,"abstract":"In this paper we review the operational principles of silicon opening switch (SOS) process the utilizing realistic physical models provided by a commercial TCAD tool. We discuses qualitatively the difference between silicon opening process and conventional junction recovery mode. We show that p-n junction has no effect on current interruption.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126902704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206240
Anshul Agarwal, S. Mandavilli
This paper is devoted to describe a voltage reference circuit which employs a feedback control technique to achieve a stable reference voltage. It has a facility to obtain any reference voltage in the range of 0.7V to 1.4V with high stability. As an example, it has been shown through simulations that a voltage reference for 0.73V with a temperature stability of about 1 ppm/°C over the temperature range of 0 to 80°C is possible. Proposed voltage reference circuit is simulated using transistor models of 0.18-µm CMOS process.
{"title":"Variable voltage reference using feedback control technique","authors":"Anshul Agarwal, S. Mandavilli","doi":"10.1109/ASQED.2009.5206240","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206240","url":null,"abstract":"This paper is devoted to describe a voltage reference circuit which employs a feedback control technique to achieve a stable reference voltage. It has a facility to obtain any reference voltage in the range of 0.7V to 1.4V with high stability. As an example, it has been shown through simulations that a voltage reference for 0.73V with a temperature stability of about 1 ppm/°C over the temperature range of 0 to 80°C is possible. Proposed voltage reference circuit is simulated using transistor models of 0.18-µm CMOS process.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127540131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206259
S. Jairam, S. Roy
An adjoint network sensitivity based incremental power pad optimization approach is proposed. The power grid is formulated as a linear network of resistive elements. Sensitivity of power pads due to the grid elements is computed. An overall cost metric is then formulated in conjuction with IR drop. This metric is then used to refine a prior optimized source location incrementally, while meeting the IR Drop constraint. The power of the approach lies in its much reduced computational complexity. Results are presented in terms of sensitivity computations before and after the incremental refinements to demonstrate the relative in-sensitivity of the power pads towards the grid elements.
{"title":"Incremental optimization of power pads based on adjoint network sensitivity","authors":"S. Jairam, S. Roy","doi":"10.1109/ASQED.2009.5206259","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206259","url":null,"abstract":"An adjoint network sensitivity based incremental power pad optimization approach is proposed. The power grid is formulated as a linear network of resistive elements. Sensitivity of power pads due to the grid elements is computed. An overall cost metric is then formulated in conjuction with IR drop. This metric is then used to refine a prior optimized source location incrementally, while meeting the IR Drop constraint. The power of the approach lies in its much reduced computational complexity. Results are presented in terms of sensitivity computations before and after the incremental refinements to demonstrate the relative in-sensitivity of the power pads towards the grid elements.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126432041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Due to the advanced lithography technologies in current semiconductor process, X-architecture has been widely used in VLSI physical design. The architecture contributes more improvements in clock delay, wire length, and power consumption than those of Manhattan architecture. This work proposed an X-architecture zero skew clock tree construction with buffer insertion and sizing. A pattern matching method for paired points is applied to determine tapping points and simplify the merging procedure of DME approach. Next, Two unit-size buffers are respectively inserted into two branches of a tapping point and then the sizes of buffers are adjusted to minimize two branch delays. Moreover, X-flip and wire sizing techniques are sequentially applied to shorten wire length and keep zero skew. Given a set of n clock sinks and a B-type buffer library, the proposed algorithm can obtain a buffered X-architecture zero skew clock tree with minimal delay and power consumption in O(B2nlogn). Experimental results on benchmarks compared with other bufferless X-routing algorithms show the improvements of 98.9%, 1.4%, 90.2%, and 90.2% in terms of clock delay, wire length, downstream capacitance, and power consumption, respectively.
{"title":"X-architecture clock tree construction associated with buffer insertion and sizing","authors":"Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee, Jan-Ou Wu","doi":"10.1109/ASQED.2009.5206248","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206248","url":null,"abstract":"Due to the advanced lithography technologies in current semiconductor process, X-architecture has been widely used in VLSI physical design. The architecture contributes more improvements in clock delay, wire length, and power consumption than those of Manhattan architecture. This work proposed an X-architecture zero skew clock tree construction with buffer insertion and sizing. A pattern matching method for paired points is applied to determine tapping points and simplify the merging procedure of DME approach. Next, Two unit-size buffers are respectively inserted into two branches of a tapping point and then the sizes of buffers are adjusted to minimize two branch delays. Moreover, X-flip and wire sizing techniques are sequentially applied to shorten wire length and keep zero skew. Given a set of n clock sinks and a B-type buffer library, the proposed algorithm can obtain a buffered X-architecture zero skew clock tree with minimal delay and power consumption in O(B2nlogn). Experimental results on benchmarks compared with other bufferless X-routing algorithms show the improvements of 98.9%, 1.4%, 90.2%, and 90.2% in terms of clock delay, wire length, downstream capacitance, and power consumption, respectively.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130038604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206290
S. Kuriyama, A. Yoshikawa, G. Tanaka
A novel variation-aware STA methodology is proposed. And with 65nm process, the impact of this methodology is estimated. Statistical STA has come into use in order to consider process variation. But methodologies to consider SI such as crosstalk and PI such as voltage drop are still under investigations. In the point of PI, process variations are considered definitely [1–3]. With the power shut off circuit, it is important to recognize which part in the circuit, power routing, normal transistors, or switch transistors is most sensitive to performance. From this acknowledgement, it is necessary to control variation of most sensitive elements and develop validation flow to handle these phenomena.
{"title":"Novel variation-aware STA methodology","authors":"S. Kuriyama, A. Yoshikawa, G. Tanaka","doi":"10.1109/ASQED.2009.5206290","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206290","url":null,"abstract":"A novel variation-aware STA methodology is proposed. And with 65nm process, the impact of this methodology is estimated. Statistical STA has come into use in order to consider process variation. But methodologies to consider SI such as crosstalk and PI such as voltage drop are still under investigations. In the point of PI, process variations are considered definitely [1–3]. With the power shut off circuit, it is important to recognize which part in the circuit, power routing, normal transistors, or switch transistors is most sensitive to performance. From this acknowledgement, it is necessary to control variation of most sensitive elements and develop validation flow to handle these phenomena.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131003584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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