Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206229
S.M. Low, M. Phoon, A. Suffian, Johan
In the realm of high speed semiconductor IC testing, the medium whereby the test signals passed has important role in order to ensure that the signal transmitted and received are the correct signals. One of the media that the signal passed in IC testing is the device interface board or load board in short. Load board is basically a printed circuit board with test socket(s) for inserting device under test (DUT) during the testing. It consists of numerous conductive traces connecting the DUT to the tester. They are carefully designed according to impedance design and control for the task they have to perform for the specific semiconductor devices. Once they are fabricated it is not possible to physically measure the trace length and impedance to validate their correctness since the traces are built internally. TDR has recently been used in the semiconductor industry for transmission line characterization and signal integrity analysis. TDR method was used successfully in this study to verify the trace length and impedance of the fabricated load board used for semiconductor's speed testing. The trace length of the evaluation load board was verified to within 8% accuracy. The trace impedance was measured to be 48 ohms which is very close to the theoretical value of 50 ohm. Thus the TDR method served as an useful tool for verification of the trace length and trace impedance of the load board.
{"title":"Verification of trace length and trace impedance of fabricated load board using TDR","authors":"S.M. Low, M. Phoon, A. Suffian, Johan","doi":"10.1109/ASQED.2009.5206229","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206229","url":null,"abstract":"In the realm of high speed semiconductor IC testing, the medium whereby the test signals passed has important role in order to ensure that the signal transmitted and received are the correct signals. One of the media that the signal passed in IC testing is the device interface board or load board in short. Load board is basically a printed circuit board with test socket(s) for inserting device under test (DUT) during the testing. It consists of numerous conductive traces connecting the DUT to the tester. They are carefully designed according to impedance design and control for the task they have to perform for the specific semiconductor devices. Once they are fabricated it is not possible to physically measure the trace length and impedance to validate their correctness since the traces are built internally. TDR has recently been used in the semiconductor industry for transmission line characterization and signal integrity analysis. TDR method was used successfully in this study to verify the trace length and impedance of the fabricated load board used for semiconductor's speed testing. The trace length of the evaluation load board was verified to within 8% accuracy. The trace impedance was measured to be 48 ohms which is very close to the theoretical value of 50 ohm. Thus the TDR method served as an useful tool for verification of the trace length and trace impedance of the load board.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125119331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206282
M. Vadizadeh, B. Davaji, M. Fathipour
In this paper, we have shown that off-state current in the Tunneling Field Effect Transistor (TFET) can be reduced dramatically by using a low-k oxide and employing gate work function engineering. In order to enhance Ion/Ioff ratio in the TFET, the effect of second gate employing has been investigated, hence using a low-k oxide for the gate near the drain side (Gate2) resulted in omission of fringing field effects. Therefore, the leakage current is decreased. Also a work function engineering method has been employed for the gate near the source (Gate1) to further reduce the off state current.
{"title":"New challenges on leakage current improvement in tunnel FET by using low-k oxide","authors":"M. Vadizadeh, B. Davaji, M. Fathipour","doi":"10.1109/ASQED.2009.5206282","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206282","url":null,"abstract":"In this paper, we have shown that off-state current in the Tunneling Field Effect Transistor (TFET) can be reduced dramatically by using a low-k oxide and employing gate work function engineering. In order to enhance Ion/Ioff ratio in the TFET, the effect of second gate employing has been investigated, hence using a low-k oxide for the gate near the drain side (Gate2) resulted in omission of fringing field effects. Therefore, the leakage current is decreased. Also a work function engineering method has been employed for the gate near the source (Gate1) to further reduce the off state current.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116518970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206252
Fang Tang, A. Bermak
A novel ultra-low power control mechanism is presented for Mega-pixels current-mediated CMOS imagers. Within the proposed technique, the operating read-out pixel and reset pixel are located in the same column, controlled by only 2-bit lines/pixel compared with 4-bit in previous reported design. The number of transistors for each pixel is reduced from the standard 6 transistors to 4 in the current design. Because the read-out and reset modes are separated into two phases in series for the proposed mechanism, only one reference current source is used, by which the power consumption can further be saved and also the chip area would be shrunk. Minimum wiring overhead is required in the proposed pixel as two control lines are removed. Furthermore, a programmable electronic shutter is adopted to adjust the integration time. The proposed design is simulated using TSMC 0.18um technology, with more than 80% fill factor for a 17×17um2 pixel dimension.
{"title":"A programmable compact control mechanism for ultra-Low power Current-Mediated CMOS Imager","authors":"Fang Tang, A. Bermak","doi":"10.1109/ASQED.2009.5206252","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206252","url":null,"abstract":"A novel ultra-low power control mechanism is presented for Mega-pixels current-mediated CMOS imagers. Within the proposed technique, the operating read-out pixel and reset pixel are located in the same column, controlled by only 2-bit lines/pixel compared with 4-bit in previous reported design. The number of transistors for each pixel is reduced from the standard 6 transistors to 4 in the current design. Because the read-out and reset modes are separated into two phases in series for the proposed mechanism, only one reference current source is used, by which the power consumption can further be saved and also the chip area would be shrunk. Minimum wiring overhead is required in the proposed pixel as two control lines are removed. Furthermore, a programmable electronic shutter is adopted to adjust the integration time. The proposed design is simulated using TSMC 0.18um technology, with more than 80% fill factor for a 17×17um2 pixel dimension.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129944787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206237
Jae In Lee, Jong-Won Choi, Young-seok Bae, M. Sung
General IGBTs are of two basic types, the planar IGBT and the trench IGBT. The trench IGBT has certain advantages when compared with the planar IGBT, such as a lower on-state voltage drop and a smaller cell pitch, but it also has a disadvantage in its lower breakdown voltage. The lower breakdown voltage is caused by the electric field being concentrated in a corner along the bottom of the trench gate. Therefore in this paper we propose a new trench IGBT structure that is designed to offer improved breakdown voltage.
{"title":"A novel trench IGBT with a rectangular oxide beneath the trench gate","authors":"Jae In Lee, Jong-Won Choi, Young-seok Bae, M. Sung","doi":"10.1109/ASQED.2009.5206237","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206237","url":null,"abstract":"General IGBTs are of two basic types, the planar IGBT and the trench IGBT. The trench IGBT has certain advantages when compared with the planar IGBT, such as a lower on-state voltage drop and a smaller cell pitch, but it also has a disadvantage in its lower breakdown voltage. The lower breakdown voltage is caused by the electric field being concentrated in a corner along the bottom of the trench gate. Therefore in this paper we propose a new trench IGBT structure that is designed to offer improved breakdown voltage.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126929731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206243
Lip-Kai Soh, Y.-F.K. Edwin
In this paper, an adjustable reset pulse phase frequency detector (PFD) for phase-locked loop (PLL) is proposed and analyzed. The proposed PFD adjust the width of the reset pulse when the reference clock and the feedback clock of the PLL are in phase to reduce the static phase error at the PLL output. The proposed PFD is implemented using 45nm CMOS thin oxide device with a 0.9-V supply voltage. A comparison between PLL using proposed PFD architecture and PLL using conventional PFD architecture is done. The pre-layout simulation results show a reduction of ∼61% in static phase error when the proposed PFD is implemented on the PLL compared to when the conventional PFD is implemented.
{"title":"An adjustable reset pulse phase frequency detector for phase locked loop","authors":"Lip-Kai Soh, Y.-F.K. Edwin","doi":"10.1109/ASQED.2009.5206243","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206243","url":null,"abstract":"In this paper, an adjustable reset pulse phase frequency detector (PFD) for phase-locked loop (PLL) is proposed and analyzed. The proposed PFD adjust the width of the reset pulse when the reference clock and the feedback clock of the PLL are in phase to reduce the static phase error at the PLL output. The proposed PFD is implemented using 45nm CMOS thin oxide device with a 0.9-V supply voltage. A comparison between PLL using proposed PFD architecture and PLL using conventional PFD architecture is done. The pre-layout simulation results show a reduction of ∼61% in static phase error when the proposed PFD is implemented on the PLL compared to when the conventional PFD is implemented.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125462315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206274
H. H. Ardakani, Morteza Mashayekhi
In this paper, a new self-testing method for combinational circuits backed up with polymorphic gates is presented. Testing feature is completely merged with normal circuit operation where the single stuck at fault model is applied. Experimental results show that our method is able to detect all stuck-at-faults with reduced number of test vectors and insignificant amount of redundancy and high fault detection probability compared to other methods. Also, the proposed approach can be scaled up to utilize in testing of not only small scale, but also large scale circuits.
{"title":"A self-testing method for combinational circuits using polymorphic gates","authors":"H. H. Ardakani, Morteza Mashayekhi","doi":"10.1109/ASQED.2009.5206274","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206274","url":null,"abstract":"In this paper, a new self-testing method for combinational circuits backed up with polymorphic gates is presented. Testing feature is completely merged with normal circuit operation where the single stuck at fault model is applied. Experimental results show that our method is able to detect all stuck-at-faults with reduced number of test vectors and insignificant amount of redundancy and high fault detection probability compared to other methods. Also, the proposed approach can be scaled up to utilize in testing of not only small scale, but also large scale circuits.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126254829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206278
Hsuan-Ming Huang, Yiming Li
Display is the most power-hungry component in electronics industry. Power-efficient design is strongly required in thin film transistor liquid-crystal display (TFT-LCD) portable products. This work proposes a unified parameterization technique for modeling and multi-objective optimization of TFT-LCD panel using a two-stage response surface model (RSM) and genetic algorithm (GA). To achieve designing specification in circuit and system levels with minimal power consumption simultaneously, a power-delay product is considered as the object function of the TFT-LCD panel optimization. Simulation-validated RSMs and GA are thus implemented into a unified optimization framework for the design optimization problem. Comparing with the conventional design flow using CAD tools, a 21.5% reduction in the power-delay of TFT-LCD panel is achieved with 95% accuracy. Moreover, the time required for the optimization process is significantly reduced by 288 times. We notice that the proposed unified parameterization technique is object flexible and can further optimize the multi-objective system performances (i.e. crosstalk, leakage current, brightness, etc.). The unified parameterization framework may benefit the high performance display panel design in the photonics industry.
{"title":"A unified parameterization technique for TFT-LCD panel design optimization","authors":"Hsuan-Ming Huang, Yiming Li","doi":"10.1109/ASQED.2009.5206278","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206278","url":null,"abstract":"Display is the most power-hungry component in electronics industry. Power-efficient design is strongly required in thin film transistor liquid-crystal display (TFT-LCD) portable products. This work proposes a unified parameterization technique for modeling and multi-objective optimization of TFT-LCD panel using a two-stage response surface model (RSM) and genetic algorithm (GA). To achieve designing specification in circuit and system levels with minimal power consumption simultaneously, a power-delay product is considered as the object function of the TFT-LCD panel optimization. Simulation-validated RSMs and GA are thus implemented into a unified optimization framework for the design optimization problem. Comparing with the conventional design flow using CAD tools, a 21.5% reduction in the power-delay of TFT-LCD panel is achieved with 95% accuracy. Moreover, the time required for the optimization process is significantly reduced by 288 times. We notice that the proposed unified parameterization technique is object flexible and can further optimize the multi-objective system performances (i.e. crosstalk, leakage current, brightness, etc.). The unified parameterization framework may benefit the high performance display panel design in the photonics industry.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126582345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206251
Sanjay G. Talekar, S. Ramasamy, G. Lakshminarayanan, B. Venkataramani
The design and implementation details of a 4-bit time interleaved Successive approximation register (SAR) analog to digital converter (ADC) for UWB application is presented in this paper. Major contribution of this paper is the proposal for a novel digital to analog converter (DAC) architecture which reduces the area required for capacitors by a factor of three, while the maximum error due mismatch between capacitors is reduced by 33% compared to the architecture reported in the literature. The ADC is implemented in .18µm CMOS technology and has total power consumption of 17.6mw at sampling frequency of 500MS/s for an input swing of 1V peak to peak. Proposed SAR ADC gives SNDR of 23.7dB, SFDR of 31.5dB and THD of −32.2dB at Nyquist rate. The proposed ADC enables the input swing to be increased by 25% while maintaining Figure of merit same compared to a SAR ADC reported in the literature.
{"title":"500MS/s 4-b time interleaved SAR ADC using novel DAC architecture","authors":"Sanjay G. Talekar, S. Ramasamy, G. Lakshminarayanan, B. Venkataramani","doi":"10.1109/ASQED.2009.5206251","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206251","url":null,"abstract":"The design and implementation details of a 4-bit time interleaved Successive approximation register (SAR) analog to digital converter (ADC) for UWB application is presented in this paper. Major contribution of this paper is the proposal for a novel digital to analog converter (DAC) architecture which reduces the area required for capacitors by a factor of three, while the maximum error due mismatch between capacitors is reduced by 33% compared to the architecture reported in the literature. The ADC is implemented in .18µm CMOS technology and has total power consumption of 17.6mw at sampling frequency of 500MS/s for an input swing of 1V peak to peak. Proposed SAR ADC gives SNDR of 23.7dB, SFDR of 31.5dB and THD of −32.2dB at Nyquist rate. The proposed ADC enables the input swing to be increased by 25% while maintaining Figure of merit same compared to a SAR ADC reported in the literature.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116832118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206292
Sekedi B. Kobenge, Huazhong Yang
Digitally programmable delay elements (DPDE) are required to be monotonic and low power. In this paper, a low power digitally programmable delay element (DPDE) with monotonic delay characteristics is proposed. A dynamic current mirror together with a feedback technique enables a current-on-demand operation. To avoid direct currents in the output transistors, an extra inverter is introduced to independently control the NMOS of the output inverter. The static power is eliminated while dynamic power is made proportional to the delay with a maximum of 36uW when the unit is operating at 450MHz.
{"title":"A power efficient digitally programmable delay element for low power VLSI applications","authors":"Sekedi B. Kobenge, Huazhong Yang","doi":"10.1109/ASQED.2009.5206292","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206292","url":null,"abstract":"Digitally programmable delay elements (DPDE) are required to be monotonic and low power. In this paper, a low power digitally programmable delay element (DPDE) with monotonic delay characteristics is proposed. A dynamic current mirror together with a feedback technique enables a current-on-demand operation. To avoid direct currents in the output transistors, an extra inverter is introduced to independently control the NMOS of the output inverter. The static power is eliminated while dynamic power is made proportional to the delay with a maximum of 36uW when the unit is operating at 450MHz.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116919155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206276
K. Lata, S. Roy, H. S. Jamadagni
An extension to a formal verification approach of hybrid systems is proposed to verify analog and mixed signal (AMS) designs. AMS designs can be formally modeled as hybrid systems and therefore lend themselves to the formal analysis and verification techniques applied to hybrid systems. The proposed approach employs simulation traces obtained from an actual design implementation of AMS circuit blocks (for example, in the form of SPICE netlists) to carry out formal analysis and verification. This enables the same platform used for formally validating an abstract model of an AMS design, to be also used for validating its different refinements and design implementation; thereby, providing a simple route to formal verification at different levels of implementation. The feasibility of the proposed approach is demonstrated with a case study based on a tunnel diode oscillator. Since the device characteristic of a tunnel diode is highly non-linear with a negative resistance region, dynamic behavior of circuits in which it is employed as an element is difficult to model, analyze and verify within a general hybrid system formal verification tool. In the case study presented the formal model and the proposed computational techniques have been incorporated into CheckMate, a formal verification tool based on MATLAB and Simulink-Stateflow Framework from MathWorks.
{"title":"Towards formal verification of analog mixed signal designs using SPICE circuit simulation traces","authors":"K. Lata, S. Roy, H. S. Jamadagni","doi":"10.1109/ASQED.2009.5206276","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206276","url":null,"abstract":"An extension to a formal verification approach of hybrid systems is proposed to verify analog and mixed signal (AMS) designs. AMS designs can be formally modeled as hybrid systems and therefore lend themselves to the formal analysis and verification techniques applied to hybrid systems. The proposed approach employs simulation traces obtained from an actual design implementation of AMS circuit blocks (for example, in the form of SPICE netlists) to carry out formal analysis and verification. This enables the same platform used for formally validating an abstract model of an AMS design, to be also used for validating its different refinements and design implementation; thereby, providing a simple route to formal verification at different levels of implementation. The feasibility of the proposed approach is demonstrated with a case study based on a tunnel diode oscillator. Since the device characteristic of a tunnel diode is highly non-linear with a negative resistance region, dynamic behavior of circuits in which it is employed as an element is difficult to model, analyze and verify within a general hybrid system formal verification tool. In the case study presented the formal model and the proposed computational techniques have been incorporated into CheckMate, a formal verification tool based on MATLAB and Simulink-Stateflow Framework from MathWorks.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129901203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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