Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206306
Amir-Reza Ahmadimehr, B. Ebrahimi, A. Afzali-Kusha
In this paper, we propose a subthreshold SRAM cell structure which can be read differentially. The main advantage of the cell is its high read current while the static noise margin and power consumption are reasonable. The cell is suitable for high performance applications where the speed is of prime concern. To assess the efficiency of the proposed cell, we compare its characteristics to three subthreshold SRAM cell structures recently introduced in the literature. The cells are implemented in both the bulk and SOI-FinFET technologies at the node of 32nm.
{"title":"A high speed subthreshold SRAM cell design","authors":"Amir-Reza Ahmadimehr, B. Ebrahimi, A. Afzali-Kusha","doi":"10.1109/ASQED.2009.5206306","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206306","url":null,"abstract":"In this paper, we propose a subthreshold SRAM cell structure which can be read differentially. The main advantage of the cell is its high read current while the static noise margin and power consumption are reasonable. The cell is suitable for high performance applications where the speed is of prime concern. To assess the efficiency of the proposed cell, we compare its characteristics to three subthreshold SRAM cell structures recently introduced in the literature. The cells are implemented in both the bulk and SOI-FinFET technologies at the node of 32nm.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122429765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206256
S. Gupta
Functional verification (namely early verification of multimedia processing capabilities) is one of the main challenges in developing SoC-based products, such as consumer electronic devices and portables that incorporate complex audio and video interfaces. Due to rising design complexity, increasingly intricate hardware/software interactions and rising demand for lower power operation are putting pressure on SoC functional verification strategies. These trends are the threats to SoC predictability and product development schedules. In this paper I am discussing hybrid functional verification methodology well suited for Video/Audio SoC.
{"title":"Hybrid functional verification methodology for video/audio SoC","authors":"S. Gupta","doi":"10.1109/ASQED.2009.5206256","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206256","url":null,"abstract":"Functional verification (namely early verification of multimedia processing capabilities) is one of the main challenges in developing SoC-based products, such as consumer electronic devices and portables that incorporate complex audio and video interfaces. Due to rising design complexity, increasingly intricate hardware/software interactions and rising demand for lower power operation are putting pressure on SoC functional verification strategies. These trends are the threats to SoC predictability and product development schedules. In this paper I am discussing hybrid functional verification methodology well suited for Video/Audio SoC.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122658054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206242
D. Vasudevan, M. Goudarzi, E. Popovici, M. Schellekens
Design of sequential circuits involves memory elements and combinational gates. The specification of these circuits is usually done by using the finite state machines. A microprocessor can be visualized as a large finite state machine. Thus it is a known fact that FSM design plays major role in specifying the sequential circuits. A reversible design of the infamous MIPS multi-cycle FSM is introduced in this paper. Three FSMs namely original, reverse and reversible FSM of the MIPS control circuit is designed, synthesized and simulated. Synthesis and simulation results are provided for the three implementations. The overhead for designing the reversible FSM are ┌ log2(N)┐ conflict pins and one direction pin along with extra logic for inserting them.
{"title":"A Reversible MIPS multi-cycle control FSM design","authors":"D. Vasudevan, M. Goudarzi, E. Popovici, M. Schellekens","doi":"10.1109/ASQED.2009.5206242","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206242","url":null,"abstract":"Design of sequential circuits involves memory elements and combinational gates. The specification of these circuits is usually done by using the finite state machines. A microprocessor can be visualized as a large finite state machine. Thus it is a known fact that FSM design plays major role in specifying the sequential circuits. A reversible design of the infamous MIPS multi-cycle FSM is introduced in this paper. Three FSMs namely original, reverse and reversible FSM of the MIPS control circuit is designed, synthesized and simulated. Synthesis and simulation results are provided for the three implementations. The overhead for designing the reversible FSM are ┌ log2(N)┐ conflict pins and one direction pin along with extra logic for inserting them.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134353459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206228
D. Saab, Vivek Nagubadi, F. Kocan, J. Abraham
Off-the-shelf Integrated Circuits (ICs) are used in the design of many products. The IC is supposed to implement a set of available specifications describing the function of the IC. Users of off-the-shelf ICs need a simple and effective method to validate the specifications to insure that the IC implements exclusively the set of available specifications. In this paper, we propose an approach to validate these specifications by a set of IC re-engineering experiments. The proposed approach is based on the construction of a high-level description of the packaged IC and on using the extracted description to validate the specifications. The approach uses the scan operations (available for manufacturing test of the IC) and the IC specification to disassemble the states/flip-flops and output functions of the packaged IC. Using the disassembled functions, a Register Transfer Level (RTL) model suitable for Computer-Aided Design manipulation is constructed. The disassembling is based on an ATPG scan experiment. Information on the scan chains is employed to construct the connectivity of the logic function. The connectivity is then used to discover the implemented logic. Using the proposed approach, we re-constructed over 90% of the system functions for an example IC.
{"title":"Extraction based verification method for off the shelf integrated circuits","authors":"D. Saab, Vivek Nagubadi, F. Kocan, J. Abraham","doi":"10.1109/ASQED.2009.5206228","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206228","url":null,"abstract":"Off-the-shelf Integrated Circuits (ICs) are used in the design of many products. The IC is supposed to implement a set of available specifications describing the function of the IC. Users of off-the-shelf ICs need a simple and effective method to validate the specifications to insure that the IC implements exclusively the set of available specifications. In this paper, we propose an approach to validate these specifications by a set of IC re-engineering experiments. The proposed approach is based on the construction of a high-level description of the packaged IC and on using the extracted description to validate the specifications. The approach uses the scan operations (available for manufacturing test of the IC) and the IC specification to disassemble the states/flip-flops and output functions of the packaged IC. Using the disassembled functions, a Register Transfer Level (RTL) model suitable for Computer-Aided Design manipulation is constructed. The disassembling is based on an ATPG scan experiment. Information on the scan chains is employed to construct the connectivity of the logic function. The connectivity is then used to discover the implemented logic. Using the proposed approach, we re-constructed over 90% of the system functions for an example IC.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128632418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206250
Chun-Chieh Chen, Yu-Lun Chung, C. Chiu
This work presents a novel flash analog-to-digital converter (ADC) with low input capacitance. Utilizing the proposed distributed track-and-hold pre-comparators (THPCs) architecture, the loading capacitances of the ADC front-end sampling sub-circuits can be markedly reduced, thereby improving operation speed. In a standard 0.18µm CMOS process, a 1.6GS/s 6-bit flash ADC is implemented to demonstrate the feasibility of the proposed distributed THPC architecture. The equivalent input capacitance of each input port of the proposed flash ADC is only 400fF, which is an easily driven interface. Furthermore, clocked timing buffers are inserted in the encoder to accelerate the operational speed of the proposed flash ADC. Post-layout simulation results demonstrate that the proposed ADC achieves an SNDR of 35.81dB, which is 5.66 ENOB at 1.6GS/s with a 793.8MHz input signal frequency. The proposed ADC consumes 300mW from a 1.8-V supply at full operating speed.
{"title":"6-bit 1.6GS/s ADC with low input capacitance in a 0.18µm CMOS","authors":"Chun-Chieh Chen, Yu-Lun Chung, C. Chiu","doi":"10.1109/ASQED.2009.5206250","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206250","url":null,"abstract":"This work presents a novel flash analog-to-digital converter (ADC) with low input capacitance. Utilizing the proposed distributed track-and-hold pre-comparators (THPCs) architecture, the loading capacitances of the ADC front-end sampling sub-circuits can be markedly reduced, thereby improving operation speed. In a standard 0.18µm CMOS process, a 1.6GS/s 6-bit flash ADC is implemented to demonstrate the feasibility of the proposed distributed THPC architecture. The equivalent input capacitance of each input port of the proposed flash ADC is only 400fF, which is an easily driven interface. Furthermore, clocked timing buffers are inserted in the encoder to accelerate the operational speed of the proposed flash ADC. Post-layout simulation results demonstrate that the proposed ADC achieves an SNDR of 35.81dB, which is 5.66 ENOB at 1.6GS/s with a 793.8MHz input signal frequency. The proposed ADC consumes 300mW from a 1.8-V supply at full operating speed.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128715737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206291
Chung-Hsin Lin, Hung-Ming Chen
In recent years, in order to handle various sources of noise (including substrate and power supply noises) and process variation in high-end mixed-signal circuit design, analog circuits are often required to be placed symmetrically to the common axis, and high noise digital circuits need to be placed far away from noise interference to the analog blocks. In this paper, we obtain the mixed-signal SoC floorplan with the two-phase approach. In the first phase, we place the symmetry groups and non-symmetry blocks by sequence pair representation with improved implementation. In the second phase, we obtain a floorplan with minimized digital blocks noise interference to analog blocks by the effective decap fills with substrate noise model. We have compared our experimental results with the recent works in symmetry constraints and mixed-signal SOC floorplan with minimized substrate noise. The results demonstrate the effectiveness of our approach.
{"title":"On minimizing various sources of noise and meeting symmetry constraint in mixed-signal SoC floorplan design","authors":"Chung-Hsin Lin, Hung-Ming Chen","doi":"10.1109/ASQED.2009.5206291","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206291","url":null,"abstract":"In recent years, in order to handle various sources of noise (including substrate and power supply noises) and process variation in high-end mixed-signal circuit design, analog circuits are often required to be placed symmetrically to the common axis, and high noise digital circuits need to be placed far away from noise interference to the analog blocks. In this paper, we obtain the mixed-signal SoC floorplan with the two-phase approach. In the first phase, we place the symmetry groups and non-symmetry blocks by sequence pair representation with improved implementation. In the second phase, we obtain a floorplan with minimized digital blocks noise interference to analog blocks by the effective decap fills with substrate noise model. We have compared our experimental results with the recent works in symmetry constraints and mixed-signal SOC floorplan with minimized substrate noise. The results demonstrate the effectiveness of our approach.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133664615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206275
Subhadip Kundu, S. Chattopadhyay
This paper addresses the issue of blocking pattern selection to reduce both leakage and dynamic power consumption during circuit testing using scan-based approach. The blocking pattern is used to prevent the scan-chain transitions to reach circuit inputs. This, though reduce dynamic power significantly; can result in quite an increase in the leakage power. We have presented a novel approach to select a blocking pattern using Genetic Algorithm and use it properly so that both dynamic and leakage power are reduced. The average improvement in dynamic power is 20.4% and for leakage power it is about 10.8% (best is around 97.0% and 22.8% respectively) with respect to full scan circuit.
{"title":"Scan-chain masking technique for low power circuit testing","authors":"Subhadip Kundu, S. Chattopadhyay","doi":"10.1109/ASQED.2009.5206275","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206275","url":null,"abstract":"This paper addresses the issue of blocking pattern selection to reduce both leakage and dynamic power consumption during circuit testing using scan-based approach. The blocking pattern is used to prevent the scan-chain transitions to reach circuit inputs. This, though reduce dynamic power significantly; can result in quite an increase in the leakage power. We have presented a novel approach to select a blocking pattern using Genetic Algorithm and use it properly so that both dynamic and leakage power are reduced. The average improvement in dynamic power is 20.4% and for leakage power it is about 10.8% (best is around 97.0% and 22.8% respectively) with respect to full scan circuit.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131172514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206279
M. Fathipour, N. Peyvast, Reza Azadvari
In this paper we have investigated the effectiveness of employing the Single Field-Plate (SFP) technique to enhance the breakdown voltage (BV) of AlGaN/GaN power High Electron Mobility Transistors (HEMTs).A systematic procedure is provided for designing the SFP device, using two dimensional (2-D) simulation to obtain the maximum improvement in the drain-source current (IDS) and to achieve maximum breakdown voltage. It is found that significantly higher breakdown voltages and IDS can be achieved by just raising the thickness of the passivation layer Si3N4 beneath SFP (t) and raising SFP length (Lsfp) between the source and drain. We demonstrate that when a single field-plate connected to the source is employed, both breakdown voltage and IDS can be enhanced by optimizing the passivation layer Si3N4 thickness beneath the SFP as well as the SFP geometry.
{"title":"Improving performance in single field plate power High Electron Mobility Transistors (HEMTs) based on AlGaN/GaN","authors":"M. Fathipour, N. Peyvast, Reza Azadvari","doi":"10.1109/ASQED.2009.5206279","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206279","url":null,"abstract":"In this paper we have investigated the effectiveness of employing the Single Field-Plate (SFP) technique to enhance the breakdown voltage (BV) of AlGaN/GaN power High Electron Mobility Transistors (HEMTs).A systematic procedure is provided for designing the SFP device, using two dimensional (2-D) simulation to obtain the maximum improvement in the drain-source current (IDS) and to achieve maximum breakdown voltage. It is found that significantly higher breakdown voltages and IDS can be achieved by just raising the thickness of the passivation layer Si3N4 beneath SFP (t) and raising SFP length (Lsfp) between the source and drain. We demonstrate that when a single field-plate connected to the source is employed, both breakdown voltage and IDS can be enhanced by optimizing the passivation layer Si3N4 thickness beneath the SFP as well as the SFP geometry.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120947517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206233
T. N. Kumar, C. Inn
This paper presents a new fine-grain diagnostics technique that is able to locate multiple interconnect faults of an FPGA. The proposed methodology uses the concept of remove, reroute and replace technique to automatically diagnose the precise location of the faulty interconnect resources and to self-repair them. In this technique, the net under test (NUT) is removed completely and rerouted using the unused fault-free net, and then the original NUT is replaced segment by segment for testing. The fault models we use are stuck at open, stuck at close and resistive open. The proposed methodology was implemented and tested on the Spartan series FPGAs via an automated approach utilizing parallel port communication. The automation program has been written in PERL and C languages. The experiment results show that approximately 34 faulty resources could be tested per second. Moreover this method uses minimal input output blocks. This proposed technique provides high degree of resolution in exactly locating the multiple interconnect faults and thus provides 100% fault coverage.
{"title":"An automated approach for the diagnosis of multiple faults in FPGA interconnects","authors":"T. N. Kumar, C. Inn","doi":"10.1109/ASQED.2009.5206233","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206233","url":null,"abstract":"This paper presents a new fine-grain diagnostics technique that is able to locate multiple interconnect faults of an FPGA. The proposed methodology uses the concept of remove, reroute and replace technique to automatically diagnose the precise location of the faulty interconnect resources and to self-repair them. In this technique, the net under test (NUT) is removed completely and rerouted using the unused fault-free net, and then the original NUT is replaced segment by segment for testing. The fault models we use are stuck at open, stuck at close and resistive open. The proposed methodology was implemented and tested on the Spartan series FPGAs via an automated approach utilizing parallel port communication. The automation program has been written in PERL and C languages. The experiment results show that approximately 34 faulty resources could be tested per second. Moreover this method uses minimal input output blocks. This proposed technique provides high degree of resolution in exactly locating the multiple interconnect faults and thus provides 100% fault coverage.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115590762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206266
C. Lun, Yew Teong Guan, Yoon Chee Kheong, Fabian Kung Wai Lee, Wong Hin Yong, G. Vetharatnam
This paper discusses the validity of platform stitching capacitors in facilitating high-speed differential links signal return path on non-ideal reference plane. A platform design guideline for the stitching capacitor is recommended at the end of this study. The results from this study were used to enable a huge reduction in the number of platform stitching capacitors, which scored major design wins to both Intel internal and external customers. The cost saving is estimated to be approximately $10M cost saving following this design guidelines, more cost saving are expected if proliferate to other product platforms and establish good method for future product implementation. Our study shows that stitching capacitors have neither significantly improve nor degrade differential signal integrity performance on non-ideal return path. There is no direct relationship between the stitching capacitors and the frequency characteristics of the differential links on non-ideal return path. Before concluding this study, we perform time-domain analysis in Hspice and lab measurement was taken on actual system board for SATA and PCIe interfaces. All the eye diagram results captured are showing similar trend between simulation and measurement.
{"title":"Platform stitching capacitors impact to high-speed differential links on non-ideal return path","authors":"C. Lun, Yew Teong Guan, Yoon Chee Kheong, Fabian Kung Wai Lee, Wong Hin Yong, G. Vetharatnam","doi":"10.1109/ASQED.2009.5206266","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206266","url":null,"abstract":"This paper discusses the validity of platform stitching capacitors in facilitating high-speed differential links signal return path on non-ideal reference plane. A platform design guideline for the stitching capacitor is recommended at the end of this study. The results from this study were used to enable a huge reduction in the number of platform stitching capacitors, which scored major design wins to both Intel internal and external customers. The cost saving is estimated to be approximately $10M cost saving following this design guidelines, more cost saving are expected if proliferate to other product platforms and establish good method for future product implementation. Our study shows that stitching capacitors have neither significantly improve nor degrade differential signal integrity performance on non-ideal return path. There is no direct relationship between the stitching capacitors and the frequency characteristics of the differential links on non-ideal return path. Before concluding this study, we perform time-domain analysis in Hspice and lab measurement was taken on actual system board for SATA and PCIe interfaces. All the eye diagram results captured are showing similar trend between simulation and measurement.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125471842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：