Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206250
Chun-Chieh Chen, Yu-Lun Chung, C. Chiu
This work presents a novel flash analog-to-digital converter (ADC) with low input capacitance. Utilizing the proposed distributed track-and-hold pre-comparators (THPCs) architecture, the loading capacitances of the ADC front-end sampling sub-circuits can be markedly reduced, thereby improving operation speed. In a standard 0.18µm CMOS process, a 1.6GS/s 6-bit flash ADC is implemented to demonstrate the feasibility of the proposed distributed THPC architecture. The equivalent input capacitance of each input port of the proposed flash ADC is only 400fF, which is an easily driven interface. Furthermore, clocked timing buffers are inserted in the encoder to accelerate the operational speed of the proposed flash ADC. Post-layout simulation results demonstrate that the proposed ADC achieves an SNDR of 35.81dB, which is 5.66 ENOB at 1.6GS/s with a 793.8MHz input signal frequency. The proposed ADC consumes 300mW from a 1.8-V supply at full operating speed.
{"title":"6-bit 1.6GS/s ADC with low input capacitance in a 0.18µm CMOS","authors":"Chun-Chieh Chen, Yu-Lun Chung, C. Chiu","doi":"10.1109/ASQED.2009.5206250","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206250","url":null,"abstract":"This work presents a novel flash analog-to-digital converter (ADC) with low input capacitance. Utilizing the proposed distributed track-and-hold pre-comparators (THPCs) architecture, the loading capacitances of the ADC front-end sampling sub-circuits can be markedly reduced, thereby improving operation speed. In a standard 0.18µm CMOS process, a 1.6GS/s 6-bit flash ADC is implemented to demonstrate the feasibility of the proposed distributed THPC architecture. The equivalent input capacitance of each input port of the proposed flash ADC is only 400fF, which is an easily driven interface. Furthermore, clocked timing buffers are inserted in the encoder to accelerate the operational speed of the proposed flash ADC. Post-layout simulation results demonstrate that the proposed ADC achieves an SNDR of 35.81dB, which is 5.66 ENOB at 1.6GS/s with a 793.8MHz input signal frequency. The proposed ADC consumes 300mW from a 1.8-V supply at full operating speed.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128715737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206293
S. Sutanthavibul, Suresh Kumar Perabala
The paper describes a design IP-reuse methodology used in a new Intel Low Cost IA (LCIA) System-on-Chip (SoC) design, call Pineview (PNV). The PNV SoC is used in the next generation Intel Nettop/Netbook platform. The SoC chip integrates several Intel internal Intellectual Property (IP) blocks on the same die: mainly two Atom CPU cores, a Graphic engine, a memory controller, and IO interfaces. The IP-reuse methodology provides high design efficiency and productivity. It also allows flexibility and customization for lower power consumption and a floorplan optimization needed for the Nettop/Netbook market segment. The paper also provides an overview of the PNV based Nettop/Netbook platform architecture. It also explains IP-reuse methodology and full chip integration which is performed by a design team in Intel Penang Design Center.
{"title":"First Intel Low-Cost IA Atom-based System-On-Chip for Nettop/Netbook","authors":"S. Sutanthavibul, Suresh Kumar Perabala","doi":"10.1109/ASQED.2009.5206293","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206293","url":null,"abstract":"The paper describes a design IP-reuse methodology used in a new Intel Low Cost IA (LCIA) System-on-Chip (SoC) design, call Pineview (PNV). The PNV SoC is used in the next generation Intel Nettop/Netbook platform. The SoC chip integrates several Intel internal Intellectual Property (IP) blocks on the same die: mainly two Atom CPU cores, a Graphic engine, a memory controller, and IO interfaces. The IP-reuse methodology provides high design efficiency and productivity. It also allows flexibility and customization for lower power consumption and a floorplan optimization needed for the Nettop/Netbook market segment. The paper also provides an overview of the PNV based Nettop/Netbook platform architecture. It also explains IP-reuse methodology and full chip integration which is performed by a design team in Intel Penang Design Center.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127598687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206283
F. Karbassian, M. Moradinasab, M. Fathipour
The carbon nanotube field-effect transistor (CNTFET) is a promising candidate for future electronic devices. Numerical studies are performed to investigate the impact of structural and process parameters on the conventional CNTFETs. The impact of channel length, gate dielectric thickness and permittivity, source/drain dopant concentration, workfunction of the gate, and drain voltage are studied. The drain current of the transistor increases as the nanotube diameter increases or as the gate workfunction decreases. The transistor current is almost independent of source/drain dopant concentration at high dopant densities. But at low dopant concentrations it increases as dopant density increases.
{"title":"Numerical study of scaling issues of C-CNTFETs","authors":"F. Karbassian, M. Moradinasab, M. Fathipour","doi":"10.1109/ASQED.2009.5206283","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206283","url":null,"abstract":"The carbon nanotube field-effect transistor (CNTFET) is a promising candidate for future electronic devices. Numerical studies are performed to investigate the impact of structural and process parameters on the conventional CNTFETs. The impact of channel length, gate dielectric thickness and permittivity, source/drain dopant concentration, workfunction of the gate, and drain voltage are studied. The drain current of the transistor increases as the nanotube diameter increases or as the gate workfunction decreases. The transistor current is almost independent of source/drain dopant concentration at high dopant densities. But at low dopant concentrations it increases as dopant density increases.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125762314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206304
M. Moradinasab, F. Karbassian, M. Fathipour
In this paper we investigate the effects of supply voltage and the temperature on the characteristics of the Static Random Access Memory (SRAM). Two nanoscale SRAM cells based on Carbon Nanotube Field Effect Transistors (CNFETs) and Silicon MOSFET Transistors (Si-MOSFETs) were investigated for application in 32nm technology node. Simulation studies show that the stability of CNFET SRAM against supply voltage variation and temperature influences is larger than those of its Si-MOSFET SRAM counterpart. Furthermore, the circuit performance affected by these two parameters in a 32k SRAM array was investigated. The results show that the read access time in CNFET SRAM arrays based on chirality vectors bigger than (23,0), is less than conventional MOSFET SRAM array.
{"title":"A comparison study of the effects of supply voltage and temperature on the stability and performance of CNFET and nanoscale Si-MOSFET SRAMs","authors":"M. Moradinasab, F. Karbassian, M. Fathipour","doi":"10.1109/ASQED.2009.5206304","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206304","url":null,"abstract":"In this paper we investigate the effects of supply voltage and the temperature on the characteristics of the Static Random Access Memory (SRAM). Two nanoscale SRAM cells based on Carbon Nanotube Field Effect Transistors (CNFETs) and Silicon MOSFET Transistors (Si-MOSFETs) were investigated for application in 32nm technology node. Simulation studies show that the stability of CNFET SRAM against supply voltage variation and temperature influences is larger than those of its Si-MOSFET SRAM counterpart. Furthermore, the circuit performance affected by these two parameters in a 32k SRAM array was investigated. The results show that the read access time in CNFET SRAM arrays based on chirality vectors bigger than (23,0), is less than conventional MOSFET SRAM array.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"324 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122990288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206291
Chung-Hsin Lin, Hung-Ming Chen
In recent years, in order to handle various sources of noise (including substrate and power supply noises) and process variation in high-end mixed-signal circuit design, analog circuits are often required to be placed symmetrically to the common axis, and high noise digital circuits need to be placed far away from noise interference to the analog blocks. In this paper, we obtain the mixed-signal SoC floorplan with the two-phase approach. In the first phase, we place the symmetry groups and non-symmetry blocks by sequence pair representation with improved implementation. In the second phase, we obtain a floorplan with minimized digital blocks noise interference to analog blocks by the effective decap fills with substrate noise model. We have compared our experimental results with the recent works in symmetry constraints and mixed-signal SOC floorplan with minimized substrate noise. The results demonstrate the effectiveness of our approach.
{"title":"On minimizing various sources of noise and meeting symmetry constraint in mixed-signal SoC floorplan design","authors":"Chung-Hsin Lin, Hung-Ming Chen","doi":"10.1109/ASQED.2009.5206291","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206291","url":null,"abstract":"In recent years, in order to handle various sources of noise (including substrate and power supply noises) and process variation in high-end mixed-signal circuit design, analog circuits are often required to be placed symmetrically to the common axis, and high noise digital circuits need to be placed far away from noise interference to the analog blocks. In this paper, we obtain the mixed-signal SoC floorplan with the two-phase approach. In the first phase, we place the symmetry groups and non-symmetry blocks by sequence pair representation with improved implementation. In the second phase, we obtain a floorplan with minimized digital blocks noise interference to analog blocks by the effective decap fills with substrate noise model. We have compared our experimental results with the recent works in symmetry constraints and mixed-signal SOC floorplan with minimized substrate noise. The results demonstrate the effectiveness of our approach.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133664615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206242
D. Vasudevan, M. Goudarzi, E. Popovici, M. Schellekens
Design of sequential circuits involves memory elements and combinational gates. The specification of these circuits is usually done by using the finite state machines. A microprocessor can be visualized as a large finite state machine. Thus it is a known fact that FSM design plays major role in specifying the sequential circuits. A reversible design of the infamous MIPS multi-cycle FSM is introduced in this paper. Three FSMs namely original, reverse and reversible FSM of the MIPS control circuit is designed, synthesized and simulated. Synthesis and simulation results are provided for the three implementations. The overhead for designing the reversible FSM are ┌ log2(N)┐ conflict pins and one direction pin along with extra logic for inserting them.
{"title":"A Reversible MIPS multi-cycle control FSM design","authors":"D. Vasudevan, M. Goudarzi, E. Popovici, M. Schellekens","doi":"10.1109/ASQED.2009.5206242","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206242","url":null,"abstract":"Design of sequential circuits involves memory elements and combinational gates. The specification of these circuits is usually done by using the finite state machines. A microprocessor can be visualized as a large finite state machine. Thus it is a known fact that FSM design plays major role in specifying the sequential circuits. A reversible design of the infamous MIPS multi-cycle FSM is introduced in this paper. Three FSMs namely original, reverse and reversible FSM of the MIPS control circuit is designed, synthesized and simulated. Synthesis and simulation results are provided for the three implementations. The overhead for designing the reversible FSM are ┌ log2(N)┐ conflict pins and one direction pin along with extra logic for inserting them.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134353459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206275
Subhadip Kundu, S. Chattopadhyay
This paper addresses the issue of blocking pattern selection to reduce both leakage and dynamic power consumption during circuit testing using scan-based approach. The blocking pattern is used to prevent the scan-chain transitions to reach circuit inputs. This, though reduce dynamic power significantly; can result in quite an increase in the leakage power. We have presented a novel approach to select a blocking pattern using Genetic Algorithm and use it properly so that both dynamic and leakage power are reduced. The average improvement in dynamic power is 20.4% and for leakage power it is about 10.8% (best is around 97.0% and 22.8% respectively) with respect to full scan circuit.
{"title":"Scan-chain masking technique for low power circuit testing","authors":"Subhadip Kundu, S. Chattopadhyay","doi":"10.1109/ASQED.2009.5206275","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206275","url":null,"abstract":"This paper addresses the issue of blocking pattern selection to reduce both leakage and dynamic power consumption during circuit testing using scan-based approach. The blocking pattern is used to prevent the scan-chain transitions to reach circuit inputs. This, though reduce dynamic power significantly; can result in quite an increase in the leakage power. We have presented a novel approach to select a blocking pattern using Genetic Algorithm and use it properly so that both dynamic and leakage power are reduced. The average improvement in dynamic power is 20.4% and for leakage power it is about 10.8% (best is around 97.0% and 22.8% respectively) with respect to full scan circuit.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131172514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206233
T. N. Kumar, C. Inn
This paper presents a new fine-grain diagnostics technique that is able to locate multiple interconnect faults of an FPGA. The proposed methodology uses the concept of remove, reroute and replace technique to automatically diagnose the precise location of the faulty interconnect resources and to self-repair them. In this technique, the net under test (NUT) is removed completely and rerouted using the unused fault-free net, and then the original NUT is replaced segment by segment for testing. The fault models we use are stuck at open, stuck at close and resistive open. The proposed methodology was implemented and tested on the Spartan series FPGAs via an automated approach utilizing parallel port communication. The automation program has been written in PERL and C languages. The experiment results show that approximately 34 faulty resources could be tested per second. Moreover this method uses minimal input output blocks. This proposed technique provides high degree of resolution in exactly locating the multiple interconnect faults and thus provides 100% fault coverage.
{"title":"An automated approach for the diagnosis of multiple faults in FPGA interconnects","authors":"T. N. Kumar, C. Inn","doi":"10.1109/ASQED.2009.5206233","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206233","url":null,"abstract":"This paper presents a new fine-grain diagnostics technique that is able to locate multiple interconnect faults of an FPGA. The proposed methodology uses the concept of remove, reroute and replace technique to automatically diagnose the precise location of the faulty interconnect resources and to self-repair them. In this technique, the net under test (NUT) is removed completely and rerouted using the unused fault-free net, and then the original NUT is replaced segment by segment for testing. The fault models we use are stuck at open, stuck at close and resistive open. The proposed methodology was implemented and tested on the Spartan series FPGAs via an automated approach utilizing parallel port communication. The automation program has been written in PERL and C languages. The experiment results show that approximately 34 faulty resources could be tested per second. Moreover this method uses minimal input output blocks. This proposed technique provides high degree of resolution in exactly locating the multiple interconnect faults and thus provides 100% fault coverage.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115590762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206266
C. Lun, Yew Teong Guan, Yoon Chee Kheong, Fabian Kung Wai Lee, Wong Hin Yong, G. Vetharatnam
This paper discusses the validity of platform stitching capacitors in facilitating high-speed differential links signal return path on non-ideal reference plane. A platform design guideline for the stitching capacitor is recommended at the end of this study. The results from this study were used to enable a huge reduction in the number of platform stitching capacitors, which scored major design wins to both Intel internal and external customers. The cost saving is estimated to be approximately $10M cost saving following this design guidelines, more cost saving are expected if proliferate to other product platforms and establish good method for future product implementation. Our study shows that stitching capacitors have neither significantly improve nor degrade differential signal integrity performance on non-ideal return path. There is no direct relationship between the stitching capacitors and the frequency characteristics of the differential links on non-ideal return path. Before concluding this study, we perform time-domain analysis in Hspice and lab measurement was taken on actual system board for SATA and PCIe interfaces. All the eye diagram results captured are showing similar trend between simulation and measurement.
{"title":"Platform stitching capacitors impact to high-speed differential links on non-ideal return path","authors":"C. Lun, Yew Teong Guan, Yoon Chee Kheong, Fabian Kung Wai Lee, Wong Hin Yong, G. Vetharatnam","doi":"10.1109/ASQED.2009.5206266","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206266","url":null,"abstract":"This paper discusses the validity of platform stitching capacitors in facilitating high-speed differential links signal return path on non-ideal reference plane. A platform design guideline for the stitching capacitor is recommended at the end of this study. The results from this study were used to enable a huge reduction in the number of platform stitching capacitors, which scored major design wins to both Intel internal and external customers. The cost saving is estimated to be approximately $10M cost saving following this design guidelines, more cost saving are expected if proliferate to other product platforms and establish good method for future product implementation. Our study shows that stitching capacitors have neither significantly improve nor degrade differential signal integrity performance on non-ideal return path. There is no direct relationship between the stitching capacitors and the frequency characteristics of the differential links on non-ideal return path. Before concluding this study, we perform time-domain analysis in Hspice and lab measurement was taken on actual system board for SATA and PCIe interfaces. All the eye diagram results captured are showing similar trend between simulation and measurement.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125471842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206303
N. Peyvast, M. Fathipour
In this paper, a new structure for a power UMOSFET_ACCUFET, based-on 4H-SiC, has been represented. We have demonstrated that by using vertical P and N pillars under the trench of a conventional UMOSFET, a superior characteristic for this device is achieved. The structure may be optimized by appropriate choice of N and P pillar's doping concentrations as well as widths.
{"title":"A novel 4H-SiC UMOSFET_ACCUFET with large blocking voltage","authors":"N. Peyvast, M. Fathipour","doi":"10.1109/ASQED.2009.5206303","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206303","url":null,"abstract":"In this paper, a new structure for a power UMOSFET_ACCUFET, based-on 4H-SiC, has been represented. We have demonstrated that by using vertical P and N pillars under the trench of a conventional UMOSFET, a superior characteristic for this device is achieved. The structure may be optimized by appropriate choice of N and P pillar's doping concentrations as well as widths.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124230997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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