Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206235
Somnath Banerjee, T. Gupta
Targetless logic emulation refers to a verification system in which there are no external hardware targets interfacing with the emulator. In such systems input stimuli to the DUT come either from a user provided vector file or a HDL testbench running on a software simulator and the DUT runs on hardware based logic emulator. Many users use such targetless environment for automated long-running verification tests consisting of huge sets of input stimuli, consequently an automatic recovery method is of significant interest in such systems. The automatic error recovery method shall be able to complete the emulation session gracefully skipping error points and subsequently report various errors and mismatch conditions for user debug. The paper presents a novel methodology and verification infrastructure based on periodic checkpointing, which provides a robust way of error condition detection, subsequent restoration of last saved system state and resume emulation run by skipping offending operations. It does not require any special hardware extension and provides a fully customizable checkpoint frequency selection scheme. It is seen to add only a minimal overhead on overall hardware emulation speed.
{"title":"Automatic error recovery in targetless logic emulation","authors":"Somnath Banerjee, T. Gupta","doi":"10.1109/ASQED.2009.5206235","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206235","url":null,"abstract":"Targetless logic emulation refers to a verification system in which there are no external hardware targets interfacing with the emulator. In such systems input stimuli to the DUT come either from a user provided vector file or a HDL testbench running on a software simulator and the DUT runs on hardware based logic emulator. Many users use such targetless environment for automated long-running verification tests consisting of huge sets of input stimuli, consequently an automatic recovery method is of significant interest in such systems. The automatic error recovery method shall be able to complete the emulation session gracefully skipping error points and subsequently report various errors and mismatch conditions for user debug. The paper presents a novel methodology and verification infrastructure based on periodic checkpointing, which provides a robust way of error condition detection, subsequent restoration of last saved system state and resume emulation run by skipping offending operations. It does not require any special hardware extension and provides a fully customizable checkpoint frequency selection scheme. It is seen to add only a minimal overhead on overall hardware emulation speed.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115464813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206245
Joo Guan Ooi, Kok Horng Kam
DRAM is an essential memory of a modern computer. Microprocessor loads the data which the user requested into DRAM before processing the data. Hence, DRAM contains important information in a computer. Recently, security researchers disclosed that DRAM is vulnerable to attack. Through Cold Boot Attack, DRAM contents can be recovered even after the computer has been powered off for several minutes [1]. The information obtained can be used to circumvent popular disk encryption system such as FileVault and Bit Locker. In this paper, we proposed an enhanced memory architecture which adds a data scrambling / descrambling layer between the microprocessor and DRAM controller to prevent the original data to be stored as cleartext in the DRAM. The original data will be scrambled before writing to DRAM and hence preventing the Cold Boot Attack. This new layer consists of XOR circuit, Galois Field Multiplication of order 128 (GF128) and a Pseudo Random Number Generator (PRNG). The scrambling scheme was selected in this proposal due to its simplicity for proof of concept. Any other cryptography scheme can replace the scrambling / descrambling blocks according to the required level of data protection. The designed blocks were implemented and tested on the Altera DE2 FPGA board using Nios II system. The results confirm that the use of the scrambling / descrambling blocks provides an easy solution with additional level of protection to secure the contents in the DRAM.
{"title":"A Proof of concept on defending cold boot attack","authors":"Joo Guan Ooi, Kok Horng Kam","doi":"10.1109/ASQED.2009.5206245","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206245","url":null,"abstract":"DRAM is an essential memory of a modern computer. Microprocessor loads the data which the user requested into DRAM before processing the data. Hence, DRAM contains important information in a computer. Recently, security researchers disclosed that DRAM is vulnerable to attack. Through Cold Boot Attack, DRAM contents can be recovered even after the computer has been powered off for several minutes [1]. The information obtained can be used to circumvent popular disk encryption system such as FileVault and Bit Locker. In this paper, we proposed an enhanced memory architecture which adds a data scrambling / descrambling layer between the microprocessor and DRAM controller to prevent the original data to be stored as cleartext in the DRAM. The original data will be scrambled before writing to DRAM and hence preventing the Cold Boot Attack. This new layer consists of XOR circuit, Galois Field Multiplication of order 128 (GF128) and a Pseudo Random Number Generator (PRNG). The scrambling scheme was selected in this proposal due to its simplicity for proof of concept. Any other cryptography scheme can replace the scrambling / descrambling blocks according to the required level of data protection. The designed blocks were implemented and tested on the Altera DE2 FPGA board using Nios II system. The results confirm that the use of the scrambling / descrambling blocks provides an easy solution with additional level of protection to secure the contents in the DRAM.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"225 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122991371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206232
R. Ubar, S. Kostin, J. Raik
The main objective of this work is to combine the concept of fault model free diagnosis simultaneously with cause-effect and effect-cause analysis in digital networks. We consider the diagnosis as a two step task: first, to locate a subset of faulty blocks in a network by using block level fault dictionaries, second, to locate the faulty block in this subset by effect-cause analysis. The size of the fault dictionary depends linearly on the number of blocks to be determined as faulty or not faulty. We propose a measure for evaluating the block-level diagnostic resolution of a given network, and show how this measure can be used for guiding effect-cause diagnostic analysis. Experimental results provide the data which characterize the proposed measure.
{"title":"Combined fault-model free cause-effect and effect-cause fault diagnosis in block-level digital networks","authors":"R. Ubar, S. Kostin, J. Raik","doi":"10.1109/ASQED.2009.5206232","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206232","url":null,"abstract":"The main objective of this work is to combine the concept of fault model free diagnosis simultaneously with cause-effect and effect-cause analysis in digital networks. We consider the diagnosis as a two step task: first, to locate a subset of faulty blocks in a network by using block level fault dictionaries, second, to locate the faulty block in this subset by effect-cause analysis. The size of the fault dictionary depends linearly on the number of blocks to be determined as faulty or not faulty. We propose a measure for evaluating the block-level diagnostic resolution of a given network, and show how this measure can be used for guiding effect-cause diagnostic analysis. Experimental results provide the data which characterize the proposed measure.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116941899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206249
Xitian Li, J. Lillis
A new method employing branch-and-bound for improved final placement is presented for the final step of detailed placement problem where the objective is to optimize (and tradeoff) total bounding box wirelength and timing. First, we view the placement of a cell as a bit-sequence which hierarchically encodes the procedure of constraining the cell to an exact location (exact row and column). Such bit sequences indicate a recursive dissection of the layout area. We argue that the search strategy indicated by the placement encoding has compelling advantages over typical ones in terms of search efficiency. Second, the branch-and-bound method with hierarchical placement encoding can inherently expose the possibly improved configurations and provide a mechanism for exploiting the abundant opportunities for tradeoffs between different design objectives. Our experiments start with the placements of 12 of the largest MCNC benchmarks from VPR [15], iteratively extract and release parts of the cells to larger regions (that defines the search space) and optimally (or nearly optimally) place these cells with respect to the search space. The experiments show that the wire length of the placements can be improved 11% on average with simultaneous reduction in the critical path delay of the routed placements (6.3% on average)
{"title":"A Method for improved final placement employing branch-and-bound with hierarchical placement encoding and tightened bounds","authors":"Xitian Li, J. Lillis","doi":"10.1109/ASQED.2009.5206249","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206249","url":null,"abstract":"A new method employing branch-and-bound for improved final placement is presented for the final step of detailed placement problem where the objective is to optimize (and tradeoff) total bounding box wirelength and timing. First, we view the placement of a cell as a bit-sequence which hierarchically encodes the procedure of constraining the cell to an exact location (exact row and column). Such bit sequences indicate a recursive dissection of the layout area. We argue that the search strategy indicated by the placement encoding has compelling advantages over typical ones in terms of search efficiency. Second, the branch-and-bound method with hierarchical placement encoding can inherently expose the possibly improved configurations and provide a mechanism for exploiting the abundant opportunities for tradeoffs between different design objectives. Our experiments start with the placements of 12 of the largest MCNC benchmarks from VPR [15], iteratively extract and release parts of the cells to larger regions (that defines the search space) and optimally (or nearly optimally) place these cells with respect to the search space. The experiments show that the wire length of the placements can be improved 11% on average with simultaneous reduction in the critical path delay of the routed placements (6.3% on average)","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131210605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206305
Tien-Yeh Li, Chih-Hong Hwang, Yiming Li
In this study, a three-dimensional “atomistic” coupled device-circuit simulation approach is advanced to investigate the process-variation-effect (PVE) and random dopant fluctuation (RDF) induced characteristic fluctuations in planar metal-oxide-semiconductor field-effect-transistor (MOSFET) static random access memory (SRAM) from 65-nm to 16-nm gate length. Our preliminary results show that the RDF dominates the fluctuation of static noise margin (SNM). As the gate length of the planar MOSFETs scales from 65 nm to 16 nm, the normalized RDF-induced SNM fluctuation increases from 4% to 80%. To reduce the device variability induced fluctuation in circuit, a device with vertical-doping-profile and raised Vth is employed. The SNM is 3 times larger than the original 16-nm-gate SRAM. Moreover, the normalized RDF-induced SNM fluctuation is reduced by a factor of 2.67. Additionally, a 16-nm-gate silicon-on-insulator fin-type field-effect-transistor is used to further improve the SNM of SRAM. Due to the superior electrostatic integrity and larger effective device width than planar MOSFETs, the SNM of 16-nm-gate FinFET SRAM is six times larger than the original 16 nm SRAM with five times smaller SNM fluctuation. The study investigates the roll-off characteristics of SNM and provides an insight into design of fluctuation resistant nanoscale SRAM.
{"title":"Process-variation- and random-dopant-induced static noise margin fluctuation in nanoscale CMOS and FinFET SRAM cells","authors":"Tien-Yeh Li, Chih-Hong Hwang, Yiming Li","doi":"10.1109/ASQED.2009.5206305","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206305","url":null,"abstract":"In this study, a three-dimensional “atomistic” coupled device-circuit simulation approach is advanced to investigate the process-variation-effect (PVE) and random dopant fluctuation (RDF) induced characteristic fluctuations in planar metal-oxide-semiconductor field-effect-transistor (MOSFET) static random access memory (SRAM) from 65-nm to 16-nm gate length. Our preliminary results show that the RDF dominates the fluctuation of static noise margin (SNM). As the gate length of the planar MOSFETs scales from 65 nm to 16 nm, the normalized RDF-induced SNM fluctuation increases from 4% to 80%. To reduce the device variability induced fluctuation in circuit, a device with vertical-doping-profile and raised Vth is employed. The SNM is 3 times larger than the original 16-nm-gate SRAM. Moreover, the normalized RDF-induced SNM fluctuation is reduced by a factor of 2.67. Additionally, a 16-nm-gate silicon-on-insulator fin-type field-effect-transistor is used to further improve the SNM of SRAM. Due to the superior electrostatic integrity and larger effective device width than planar MOSFETs, the SNM of 16-nm-gate FinFET SRAM is six times larger than the original 16 nm SRAM with five times smaller SNM fluctuation. The study investigates the roll-off characteristics of SNM and provides an insight into design of fluctuation resistant nanoscale SRAM.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132437502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206234
A. Achath Mohanan, C. Chan, M. Ooi
Semiconductor manufacturing is a very complex and sophisticated process and semiconductor manufacturing data are generally huge. In order to perform knowledge discovery from these huge sets of data, data has to be reduced in dimensions by only selecting certain fields which are of value towards a particular research. Most research is geared towards data mining and less importance is generally given to stages before data mining, namely problem definition, selection addition, preprocessing and data cleaning and transformation. This is undesirable because ad-hoc approaches to standardize the data during these initial stages tend to be inaccurate, any will affect the integrity of data mining performed in later stages. This paper proposes a structured data standardization framework which effectively breaks down huge semiconductor data of high dimensions into smaller values in order to perform knowledge discovery. The framework was effectively applied on two devices as a case study and the resulting processed data was successfully used for yield mining and defect clustering purposes.
{"title":"Structured database standardization framework for data mining of semiconductor manufacturing data","authors":"A. Achath Mohanan, C. Chan, M. Ooi","doi":"10.1109/ASQED.2009.5206234","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206234","url":null,"abstract":"Semiconductor manufacturing is a very complex and sophisticated process and semiconductor manufacturing data are generally huge. In order to perform knowledge discovery from these huge sets of data, data has to be reduced in dimensions by only selecting certain fields which are of value towards a particular research. Most research is geared towards data mining and less importance is generally given to stages before data mining, namely problem definition, selection addition, preprocessing and data cleaning and transformation. This is undesirable because ad-hoc approaches to standardize the data during these initial stages tend to be inaccurate, any will affect the integrity of data mining performed in later stages. This paper proposes a structured data standardization framework which effectively breaks down huge semiconductor data of high dimensions into smaller values in order to perform knowledge discovery. The framework was effectively applied on two devices as a case study and the resulting processed data was successfully used for yield mining and defect clustering purposes.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128125558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206261
A. Fallahpour, M. Ahmadi, R. Ismail
The limitations on carrier drift velocity due to high-field effect and randomly velocity vector in equilibrium is reported. The results are based on asymmetrical distribution function that converts randomness velocity vectors in zero-field to streamlined one in a very high electric field. The ultimate drift velocity is found to be appropriate thermal velocity for a given dimensionality for non-degenerately doped Silicon nanowires. However, the ultimate drift velocity is the Fermi velocity for degenerately doped Silicon nanowires. Other important parameter in carrier transport phenomena, for nanoscale devices is quantum confinement effect that leads to one-dimensional behavior in silicon nanowire.
{"title":"Analytical study of drift velocity in N-type silicon nanowires","authors":"A. Fallahpour, M. Ahmadi, R. Ismail","doi":"10.1109/ASQED.2009.5206261","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206261","url":null,"abstract":"The limitations on carrier drift velocity due to high-field effect and randomly velocity vector in equilibrium is reported. The results are based on asymmetrical distribution function that converts randomness velocity vectors in zero-field to streamlined one in a very high electric field. The ultimate drift velocity is found to be appropriate thermal velocity for a given dimensionality for non-degenerately doped Silicon nanowires. However, the ultimate drift velocity is the Fermi velocity for degenerately doped Silicon nanowires. Other important parameter in carrier transport phenomena, for nanoscale devices is quantum confinement effect that leads to one-dimensional behavior in silicon nanowire.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132042354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206255
R. Sanudin, M. S. Sulong, M. Morsin, M. Wahab
The process of scaling in silicon transistor has consistently resulted in smaller device geometry, higher device density and better performance. In conventional MOSFETs, control of Ioff for scaled devices requires very thin gate dielectrics and high doping concentrations. The industry roadmap predicts the barriers of continuous scaling will be due to physical limitations as well as practical technology. As the downscale of CMOS technology approaches physical limitations, the need arises for alternative device structures. Thus, this paper intends to study the effect of various gate lengths on the NMOS electrical characteristic by means of simulation study.
{"title":"Simulation study on NMOS gate length variation using TCAD tool","authors":"R. Sanudin, M. S. Sulong, M. Morsin, M. Wahab","doi":"10.1109/ASQED.2009.5206255","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206255","url":null,"abstract":"The process of scaling in silicon transistor has consistently resulted in smaller device geometry, higher device density and better performance. In conventional MOSFETs, control of Ioff for scaled devices requires very thin gate dielectrics and high doping concentrations. The industry roadmap predicts the barriers of continuous scaling will be due to physical limitations as well as practical technology. As the downscale of CMOS technology approaches physical limitations, the need arises for alternative device structures. Thus, this paper intends to study the effect of various gate lengths on the NMOS electrical characteristic by means of simulation study.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132114180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206300
R. Vemal, C. Lo, S. Ong, B.S. Lee, C. Yong
Microelectromechanical systems (MEMS) remain one of the fastest growing markets in the semiconductor technology industry. This growth is largely due to the increasing possibility of integration into various applications. These include the automotive industry, process control and automation, scientific and medical instrumentation, telecommunication, commodity products and environmental monitoring. Much of the process technology for MEMS in terms of wafer and package level manufacturing has been sought from the rather established IC (Integrated Circuit) industry. In some cases, the processes and application of materials have been a direct replicate of existing practices. However, the question remains to what extent can we apply the IC replication process for MEMS while taking into consideration the much more delicate nature of MEMS parts for reliability's sake. There needs to be a thorough analysis on these differences to determine if a new standard of manufacturing is needed. If this point is neglected for the sake of cost saving in manufacturing operations, there is a high possibility the integrity of the MEMS parts will suffer with subsequent downstream processing. This literature work aims to provide a much deeper and in-depth understanding in this area from a packaging point-of-view. We will revisit the various processes and fundamental differences between MEMS and IC packaging.
{"title":"MEMS vs. IC manufacturing: Is integration between processes possible","authors":"R. Vemal, C. Lo, S. Ong, B.S. Lee, C. Yong","doi":"10.1109/ASQED.2009.5206300","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206300","url":null,"abstract":"Microelectromechanical systems (MEMS) remain one of the fastest growing markets in the semiconductor technology industry. This growth is largely due to the increasing possibility of integration into various applications. These include the automotive industry, process control and automation, scientific and medical instrumentation, telecommunication, commodity products and environmental monitoring. Much of the process technology for MEMS in terms of wafer and package level manufacturing has been sought from the rather established IC (Integrated Circuit) industry. In some cases, the processes and application of materials have been a direct replicate of existing practices. However, the question remains to what extent can we apply the IC replication process for MEMS while taking into consideration the much more delicate nature of MEMS parts for reliability's sake. There needs to be a thorough analysis on these differences to determine if a new standard of manufacturing is needed. If this point is neglected for the sake of cost saving in manufacturing operations, there is a high possibility the integrity of the MEMS parts will suffer with subsequent downstream processing. This literature work aims to provide a much deeper and in-depth understanding in this area from a packaging point-of-view. We will revisit the various processes and fundamental differences between MEMS and IC packaging.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127390627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206253
Fang Tang, A. Bermak
A novel CMOS current-mediated imager (CMI) is presented with high output linearity. In the proposed structure, the pixel operates in triode region, instead of operating in saturation region for conventional current-mediated imagers. As a consequence, the output current is a linear function of the photocurrent at the sensing node. Such a linear feature reduces the DC current consumption by more than a factor of 10 for high linearity applications. Additionally, the corresponding current source/mirror circuit is also presented, aiming to further minimize the linearity distortion caused by the Vds variation.
{"title":"A low power linear output current-mediated CMOS imager","authors":"Fang Tang, A. Bermak","doi":"10.1109/ASQED.2009.5206253","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206253","url":null,"abstract":"A novel CMOS current-mediated imager (CMI) is presented with high output linearity. In the proposed structure, the pixel operates in triode region, instead of operating in saturation region for conventional current-mediated imagers. As a consequence, the output current is a linear function of the photocurrent at the sensing node. Such a linear feature reduces the DC current consumption by more than a factor of 10 for high linearity applications. Additionally, the corresponding current source/mirror circuit is also presented, aiming to further minimize the linearity distortion caused by the Vds variation.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127305330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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