Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206258
Jae Hoon Kim, Wook Kim, Young Hwan Kim
In this paper, we analyzes the error due to the effects of local random variation on delay and leakage in the gate level statistical modeling. In experiments with various gates, without considering the local random variation showed over 20% of maximum error on the gate delay standard deviation, when compared with the results considering the local random variation. Moreover, in the aspect of leakage, without considering the local random variation causes maximum 10% of mean leakage error and over 300% of standard deviation error, when compared with the results considering the local random variation. Since conventional gate-level statistical model does not consider the local random variation, large local random variation may cause the significant error. Therefore, novel gate-level statistical modeling method considering the local random variation is required.
{"title":"Effect of local random variation on gate-level delay and leakage statistical analysis","authors":"Jae Hoon Kim, Wook Kim, Young Hwan Kim","doi":"10.1109/ASQED.2009.5206258","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206258","url":null,"abstract":"In this paper, we analyzes the error due to the effects of local random variation on delay and leakage in the gate level statistical modeling. In experiments with various gates, without considering the local random variation showed over 20% of maximum error on the gate delay standard deviation, when compared with the results considering the local random variation. Moreover, in the aspect of leakage, without considering the local random variation causes maximum 10% of mean leakage error and over 300% of standard deviation error, when compared with the results considering the local random variation. Since conventional gate-level statistical model does not consider the local random variation, large local random variation may cause the significant error. Therefore, novel gate-level statistical modeling method considering the local random variation is required.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114277501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206257
Yijia Xu, G. Yeap
We present an MTCMOS switch cell power network design approach from a flow perspective. It begins with switch cell configuration exploration during the floorplanning phase. High-level area, congestion and IR-drop tradeoff is made during early design flow. At the chip implementation phase, the switch cells are further optimized by cell sizing and optimization to meet IR-drop and power dissipation targets. Finally, ECO operations are applied near the end of the design flow to accommodate late-stage design changes. This design approach allows for a graceful convergence of MTCMOS switch cells in power network design and reduces uncertainties and iterations during the flow. This is similar to the timing convergence flow that is currently a standard practice in every chip design. We showed, with experimental results, that this was an effective methodology to design power networks with MTCMOS switch cells.
{"title":"An MTCMOS power network design flow","authors":"Yijia Xu, G. Yeap","doi":"10.1109/ASQED.2009.5206257","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206257","url":null,"abstract":"We present an MTCMOS switch cell power network design approach from a flow perspective. It begins with switch cell configuration exploration during the floorplanning phase. High-level area, congestion and IR-drop tradeoff is made during early design flow. At the chip implementation phase, the switch cells are further optimized by cell sizing and optimization to meet IR-drop and power dissipation targets. Finally, ECO operations are applied near the end of the design flow to accommodate late-stage design changes. This design approach allows for a graceful convergence of MTCMOS switch cells in power network design and reduces uncertainties and iterations during the flow. This is similar to the timing convergence flow that is currently a standard practice in every chip design. We showed, with experimental results, that this was an effective methodology to design power networks with MTCMOS switch cells.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120964568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206265
M. Orvatinia, Saeed Gandomkar
A ZnO varistor with a breakdown electric field of 180 Vmm-1 in air ambient has been fabricated by cold-pressing of pure ZnO in form of thick film porous semiconductor. The behavior of the varistor at various temperatures was investigated and its non-linear I–V characteristics were recorded. It was shown that the breakdown voltage shifts to a lower electric field with rise of its operating temperature. The higher temperatures causes to higher changes in the breakdown voltage and lower electric field. Also it revealed that the breakdown voltage of the varistor depends on the number of grain boundaries located between two electrodes of the varistor. The breakdown voltage of the varistor can also be affected by the pollutant gases in environment.
{"title":"I–V characteristics of a ZnO thick-film varistor fabricated by cold-pressing method","authors":"M. Orvatinia, Saeed Gandomkar","doi":"10.1109/ASQED.2009.5206265","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206265","url":null,"abstract":"A ZnO varistor with a breakdown electric field of 180 Vmm-1 in air ambient has been fabricated by cold-pressing of pure ZnO in form of thick film porous semiconductor. The behavior of the varistor at various temperatures was investigated and its non-linear I–V characteristics were recorded. It was shown that the breakdown voltage shifts to a lower electric field with rise of its operating temperature. The higher temperatures causes to higher changes in the breakdown voltage and lower electric field. Also it revealed that the breakdown voltage of the varistor depends on the number of grain boundaries located between two electrodes of the varistor. The breakdown voltage of the varistor can also be affected by the pollutant gases in environment.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122542757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206246
Katrina Lu, D. Pan
Thermal effect is a key factor to interconnect reliability degradation. As technology scales, the distance between the metal layers and substrate continues to shrink and significantly increases the impact of substrate temperature on interconnect reliability. While it is already a concern in 2D ICs, the thermal impact will be more challenging in the emerging 3D ICs architecture. In this paper, we present a reliability-aware global routing with thermal considerations. We propose two techniques, thermal-driven Minimum Spanning Tree (MST) construction and thermal-driven maze routing, to reduce the probability of interconnect failures. Experimental results show that our router effectively reduces the failure rate by approximately 13% on average, with little overhead on the traditional design objectives.
{"title":"Reliability-aware global routing under thermal considerations","authors":"Katrina Lu, D. Pan","doi":"10.1109/ASQED.2009.5206246","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206246","url":null,"abstract":"Thermal effect is a key factor to interconnect reliability degradation. As technology scales, the distance between the metal layers and substrate continues to shrink and significantly increases the impact of substrate temperature on interconnect reliability. While it is already a concern in 2D ICs, the thermal impact will be more challenging in the emerging 3D ICs architecture. In this paper, we present a reliability-aware global routing with thermal considerations. We propose two techniques, thermal-driven Minimum Spanning Tree (MST) construction and thermal-driven maze routing, to reduce the probability of interconnect failures. Experimental results show that our router effectively reduces the failure rate by approximately 13% on average, with little overhead on the traditional design objectives.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132415276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206270
L. K. Yong
It is ubiquitous that high performance integrated circuits designs are commonly suffers from total chip power consumption. Moreover, when we are marching towards deeper sub-micron technology from process scaling, the transistor leakage it self had became more and more dominant to the total component power which is unavoidable. Clever employment of power gating / sleep transistor / MTCMOS technology can help to shut off leakage power from un-use blocks. However at high temperature and fast skew, OFF stage leakage current will still be very significant if wrong implementation strategy was employed. This paper described the circuit analysis, optimization strategies and design methodology to tackle this issue head on. Details break down on the circuit modeling and design trade off on Power Gating FETs was described in this paper including simulation results and equations to aid the illustrations. The OFF stage power saving using MTCMOS was re-evaluated for total leakage minimization.
{"title":"OFF stage leakage analysis from Power Gating application in deep sub-micron technology","authors":"L. K. Yong","doi":"10.1109/ASQED.2009.5206270","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206270","url":null,"abstract":"It is ubiquitous that high performance integrated circuits designs are commonly suffers from total chip power consumption. Moreover, when we are marching towards deeper sub-micron technology from process scaling, the transistor leakage it self had became more and more dominant to the total component power which is unavoidable. Clever employment of power gating / sleep transistor / MTCMOS technology can help to shut off leakage power from un-use blocks. However at high temperature and fast skew, OFF stage leakage current will still be very significant if wrong implementation strategy was employed. This paper described the circuit analysis, optimization strategies and design methodology to tackle this issue head on. Details break down on the circuit modeling and design trade off on Power Gating FETs was described in this paper including simulation results and equations to aid the illustrations. The OFF stage power saving using MTCMOS was re-evaluated for total leakage minimization.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"21 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127563095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206273
Chong-Ling Khoo, H. C. How, Wei Wei Lo, M. Wong
With the increase in data processing speeds, the requirement for a clean reference clock source for high-speed data processing is paramount. A clean reference clock source for a high-speed data system must satisfy the following criteria: generates a clock signal with very fast rising and falling edges, exhibits low intrinsic jitter and does not add additional jitters through the clock distribution network. Generally, the cost of a reference clock source rises with the quality of the clock signal. This paper proposes a low-cost clock cleaner solution for reference clock sources called the Clock Cleaner. The Clock Cleaner provides a wide range of reference clock frequencies with very low phase noise and jitter. The Clock Cleaner offers an affordable and flexible way for electronic system designers to prototype their high-speed applications. This paper presents the implementation of the Clock Cleaner using an Altera Cyclone III FPGA device and a NIOS II processor. This paper also analyzes the Clock Cleaner's phase noise and jitter performance and compares them with two commercial clock generation equipments.
随着数据处理速度的提高，需要一个干净的参考时钟源来进行高速数据处理是至关重要的。用于高速数据系统的干净的参考时钟源必须满足以下标准:产生具有非常快的上升沿和下降沿的时钟信号，具有低的固有抖动，并且不会通过时钟分配网络增加额外的抖动。通常，参考时钟源的成本随着时钟信号的质量而上升。本文为参考时钟源提出了一种低成本的时钟清理方案，称为时钟清理器。时钟清洁器提供广泛的参考时钟频率，相位噪声和抖动非常低。时钟清洁器为电子系统设计人员提供了一种经济实惠且灵活的方式来设计其高速应用程序的原型。本文介绍了使用Altera Cyclone III FPGA器件和NIOS II处理器实现时钟清理器。本文还分析了时钟清洁器的相位噪声和抖动性能，并与两种商用时钟产生设备进行了比较。
{"title":"Low cost clock cleaner solution for reference clock sources","authors":"Chong-Ling Khoo, H. C. How, Wei Wei Lo, M. Wong","doi":"10.1109/ASQED.2009.5206273","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206273","url":null,"abstract":"With the increase in data processing speeds, the requirement for a clean reference clock source for high-speed data processing is paramount. A clean reference clock source for a high-speed data system must satisfy the following criteria: generates a clock signal with very fast rising and falling edges, exhibits low intrinsic jitter and does not add additional jitters through the clock distribution network. Generally, the cost of a reference clock source rises with the quality of the clock signal. This paper proposes a low-cost clock cleaner solution for reference clock sources called the Clock Cleaner. The Clock Cleaner provides a wide range of reference clock frequencies with very low phase noise and jitter. The Clock Cleaner offers an affordable and flexible way for electronic system designers to prototype their high-speed applications. This paper presents the implementation of the Clock Cleaner using an Altera Cyclone III FPGA device and a NIOS II processor. This paper also analyzes the Clock Cleaner's phase noise and jitter performance and compares them with two commercial clock generation equipments.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"62 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130626257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206301
Leaw Pang Tun, L. Peng
Today's electronic products are required to be increasingly small, fast, low power, light weight and feature-rich. These requirements have been converted to the electronic domain as smaller IC package with higher number of I/O. To accommodate higher I/O in a shrinking package size, the pin pitch needs to be reduced tremendously. To align with the drastic growth of package technology, PCB technology needs to advance in the area of design, fabrication and assembly to support the fine pitch package interconnection to PCB. This paper attempts to elaborate the challenges in supporting high density PCB with 0.40 mm pitch BGA from design, fabrication and assembly perspective, as well as discussing the current workarounds and solutions to the challenges and difficulties faced with today PCB technology.
{"title":"Challenges in high density PCB with 0.40 mm pitch BGA - From design, fabrication & assembly perspective","authors":"Leaw Pang Tun, L. Peng","doi":"10.1109/ASQED.2009.5206301","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206301","url":null,"abstract":"Today's electronic products are required to be increasingly small, fast, low power, light weight and feature-rich. These requirements have been converted to the electronic domain as smaller IC package with higher number of I/O. To accommodate higher I/O in a shrinking package size, the pin pitch needs to be reduced tremendously. To align with the drastic growth of package technology, PCB technology needs to advance in the area of design, fabrication and assembly to support the fine pitch package interconnection to PCB. This paper attempts to elaborate the challenges in supporting high density PCB with 0.40 mm pitch BGA from design, fabrication and assembly perspective, as well as discussing the current workarounds and solutions to the challenges and difficulties faced with today PCB technology.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124650832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206299
C. P. Wong, Pui Ling Lee, Wei Wei Lo, M. Wong
This paper analyzes the effects of the PCB signal via depth on the simultaneous switching noise (SSN) in a field programmable gate array (FPGA) device. SSN consists of two distinct components: mutual inductive coupling noise and power distribution network (PDN) noise. This paper presents an experimental study of the PCB signal via depth effects on mutual inductive coupling noise using an Altera FPGA device. This paper also describes the return current path concept and the effect of the return current path on SSN in a multi-layer PCB. The results from this study assist electronic system designers in understanding the PCB signal via depth effects on SSN and identifying strategies for reducing and minimizing SSN.
{"title":"PCB via depth effect on SSN for FPGA","authors":"C. P. Wong, Pui Ling Lee, Wei Wei Lo, M. Wong","doi":"10.1109/ASQED.2009.5206299","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206299","url":null,"abstract":"This paper analyzes the effects of the PCB signal via depth on the simultaneous switching noise (SSN) in a field programmable gate array (FPGA) device. SSN consists of two distinct components: mutual inductive coupling noise and power distribution network (PDN) noise. This paper presents an experimental study of the PCB signal via depth effects on mutual inductive coupling noise using an Altera FPGA device. This paper also describes the return current path concept and the effect of the return current path on SSN in a multi-layer PCB. The results from this study assist electronic system designers in understanding the PCB signal via depth effects on SSN and identifying strategies for reducing and minimizing SSN.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126956744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206307
B. Ebrahimi, A. Afzali-Kusha
In this paper, a comparison between CNFET and Si-MOSFET SRAM cells at 32nm technology node are presented. The designs are based on predictive technology model (PTM) for the Si-MOSFET cell and CNFET Stanford model for the CNFET cell. For practical reasons, in the CNFET case, the substrate of the entire chip is considered to be one node. The effect of the voltage of this node on improving the overall characteristics of the CNFET cell is described. HSPICE simulation results show that CNFET has better performance compared to Si-MOSFET. Finally, the characteristics of the SRAM cell in the presence of fabrication imperfections of CNFET are studied. The write stability of CNFET SRAM is low because of the same current drive capability for both p- and n-CNFETs. For solving this problem, we weaken the pull up transistors by different channel length and CNT diameter with respect to n type transistors.
{"title":"Realistic CNFET based SRAM cell design for better write stability","authors":"B. Ebrahimi, A. Afzali-Kusha","doi":"10.1109/ASQED.2009.5206307","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206307","url":null,"abstract":"In this paper, a comparison between CNFET and Si-MOSFET SRAM cells at 32nm technology node are presented. The designs are based on predictive technology model (PTM) for the Si-MOSFET cell and CNFET Stanford model for the CNFET cell. For practical reasons, in the CNFET case, the substrate of the entire chip is considered to be one node. The effect of the voltage of this node on improving the overall characteristics of the CNFET cell is described. HSPICE simulation results show that CNFET has better performance compared to Si-MOSFET. Finally, the characteristics of the SRAM cell in the presence of fabrication imperfections of CNFET are studied. The write stability of CNFET SRAM is low because of the same current drive capability for both p- and n-CNFETs. For solving this problem, we weaken the pull up transistors by different channel length and CNT diameter with respect to n type transistors.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126921905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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