Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206287
Hui-Wen Cheng, Chih-Hong Hwang, Yiming Li
Fin-type vertical channel Field Effect Transistors (FETs) are promising alternatives for the sub-32-nm CMOS technologies. This work investigates the impact of fin number and structure on Vth degradation and transient behavior of devices and circuits. Vertical channel transistors with different fin aspect ratio (AR = the fin height / the effective fin width) are explored. The multi-fin FinFETs (AR = 2) has a better channel controllability and a larger device width than tri-gate (AR = 1) and quasi-planar (AR = 0.5) MOSFETs. Though the increase of fin aspect ratio provides larger effective device width and driving current, the gate capacitance is increased also and limits the intrinsic device gate delay. The transient characteristics of single-/multi-fin inverter circuits are then examined by adding the load capacitance of circuits (1 and 10 fF). The added capacitance dominates the overall load capacitance and reduces the impact of the device intrinsic capacitance. The delay time is therefore dominated by the driving current of transistor and the multi-fin circuits performed a smaller delay time than the single-fin circuits. Additionally, the large driving capability of FinFET implies the less impact of load capacitance variation resulted from process variation. The multi-fin FinFETs exhibit better channel controllability against intrinsic parameter variation of active transistor and also mitigate the impact of process variation induced load capacitance variation of interconnect.
{"title":"Propagation delay dependence on channel fins and geometry aspect ratio of 16-nm multi-gate MOSFET inverter","authors":"Hui-Wen Cheng, Chih-Hong Hwang, Yiming Li","doi":"10.1109/ASQED.2009.5206287","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206287","url":null,"abstract":"Fin-type vertical channel Field Effect Transistors (FETs) are promising alternatives for the sub-32-nm CMOS technologies. This work investigates the impact of fin number and structure on Vth degradation and transient behavior of devices and circuits. Vertical channel transistors with different fin aspect ratio (AR = the fin height / the effective fin width) are explored. The multi-fin FinFETs (AR = 2) has a better channel controllability and a larger device width than tri-gate (AR = 1) and quasi-planar (AR = 0.5) MOSFETs. Though the increase of fin aspect ratio provides larger effective device width and driving current, the gate capacitance is increased also and limits the intrinsic device gate delay. The transient characteristics of single-/multi-fin inverter circuits are then examined by adding the load capacitance of circuits (1 and 10 fF). The added capacitance dominates the overall load capacitance and reduces the impact of the device intrinsic capacitance. The delay time is therefore dominated by the driving current of transistor and the multi-fin circuits performed a smaller delay time than the single-fin circuits. Additionally, the large driving capability of FinFET implies the less impact of load capacitance variation resulted from process variation. The multi-fin FinFETs exhibit better channel controllability against intrinsic parameter variation of active transistor and also mitigate the impact of process variation induced load capacitance variation of interconnect.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129988163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206244
M. Hussain, M. M. Rahmatullah
Motion estimation is the most computationally demanding task in MPEG-4 based video compression techniques. Motion estimation consumes 70% of the computational capability and its hardware realization contributes up to 60% of chip power. This paper describes our efforts in analyzing power consumption of motion estimation in custom VLSI architecture prototyped as a Configurable System on a Chip (CSoC). This CSoC exploits dynamic partial reconfiguration of FPGA to allow changing search techniques/ search area to facilitate efficient intermode decision. Dynamic partial reconfiguration adds flexibility in terms of chip area at the cost of overhead in time to reconfigure and extra power consumption during dynamic partial reconfiguration. We perform power analysis on hardware by taking configuration and hardware execution power into account and observe how frequency of partial reconfiguration affects net power consumption.
{"title":"Power analysis of hardware based motion estimation in a heterogeneous reconfigurable environment","authors":"M. Hussain, M. M. Rahmatullah","doi":"10.1109/ASQED.2009.5206244","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206244","url":null,"abstract":"Motion estimation is the most computationally demanding task in MPEG-4 based video compression techniques. Motion estimation consumes 70% of the computational capability and its hardware realization contributes up to 60% of chip power. This paper describes our efforts in analyzing power consumption of motion estimation in custom VLSI architecture prototyped as a Configurable System on a Chip (CSoC). This CSoC exploits dynamic partial reconfiguration of FPGA to allow changing search techniques/ search area to facilitate efficient intermode decision. Dynamic partial reconfiguration adds flexibility in terms of chip area at the cost of overhead in time to reconfigure and extra power consumption during dynamic partial reconfiguration. We perform power analysis on hardware by taking configuration and hardware execution power into account and observe how frequency of partial reconfiguration affects net power consumption.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116972484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206284
Wu Xiajun, Xiaojin Zhao, A. Bermak, F. Boussaid
This paper presents a compact Address Event Representation AER-based CMOS image sensor for real-time focal-plane polarization imaging. The image sensor integrates a unique micropolarizer array, patterned using the well-controlled process of UV photolithography. Real-time Stokes parameters extraction is achieved using a novel time-to-first-spike (TFS) pixel architecture. The proposed implementation enables low power operation and efficient readout of polarization information. Moreover, it is scalable and well suited to the next generation of deep submicron CMOS technologies owing to decreased supply voltage and increased noise level.
{"title":"An AER based CMOS polarization image sensor with photo-aligned micropolarizer array","authors":"Wu Xiajun, Xiaojin Zhao, A. Bermak, F. Boussaid","doi":"10.1109/ASQED.2009.5206284","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206284","url":null,"abstract":"This paper presents a compact Address Event Representation AER-based CMOS image sensor for real-time focal-plane polarization imaging. The image sensor integrates a unique micropolarizer array, patterned using the well-controlled process of UV photolithography. Real-time Stokes parameters extraction is achieved using a novel time-to-first-spike (TFS) pixel architecture. The proposed implementation enables low power operation and efficient readout of polarization information. Moreover, it is scalable and well suited to the next generation of deep submicron CMOS technologies owing to decreased supply voltage and increased noise level.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128006796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206268
Satyanarayan Iyer, G. Chennagiri, A. Akhbar, A. Ismail
The growth in demand for memory capacity is surpassing the pace at which memory component manufacturers are able to cost-effectively produce the next generation of monolithic memory devices. This drives the need for utilizing stacked components for memory module assemblies. The introduction of stacked CSP components, which consist of multiple layers of solder balls and is heavier than regular CSP components, requires that the processes used for assembling monolithic components be reviewed and re-optimized to suit its manufacturability and reliability. One of the characteristics to review is the self centering capability, which is an inherent and desirable property of area array devices that can largely compensate for the errors in placement of these components. The added weight of a stacked CSP component could inhibit its self centering characteristic. This paper presents a systematic approach to assess the self centering characteristics of a stacked CSP component. The heaviest available memory component was used for this evaluation. The findings of this assessment is useful in determining the capability requirements for the placement machine and to establish the inspection criteria. Based on the analysis and the results, the stacked CSP component was able to self center when misplaced by 50% along the diagonal.
{"title":"Self centering assessment of stacked CSP memory components","authors":"Satyanarayan Iyer, G. Chennagiri, A. Akhbar, A. Ismail","doi":"10.1109/ASQED.2009.5206268","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206268","url":null,"abstract":"The growth in demand for memory capacity is surpassing the pace at which memory component manufacturers are able to cost-effectively produce the next generation of monolithic memory devices. This drives the need for utilizing stacked components for memory module assemblies. The introduction of stacked CSP components, which consist of multiple layers of solder balls and is heavier than regular CSP components, requires that the processes used for assembling monolithic components be reviewed and re-optimized to suit its manufacturability and reliability. One of the characteristics to review is the self centering capability, which is an inherent and desirable property of area array devices that can largely compensate for the errors in placement of these components. The added weight of a stacked CSP component could inhibit its self centering characteristic. This paper presents a systematic approach to assess the self centering characteristics of a stacked CSP component. The heaviest available memory component was used for this evaluation. The findings of this assessment is useful in determining the capability requirements for the placement machine and to establish the inspection criteria. Based on the analysis and the results, the stacked CSP component was able to self center when misplaced by 50% along the diagonal.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130863640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206396
Chen-Wei Hsu, Jia-Lu Liao, J. Yeh, Ji-Jan Chen, Shi-Yu Huang, J. Liou
In this work, we propose a fast and accurate system-level power estimation methodology. To achieve high accuracy for an in-house digital signal processor, called PAC, we incorporate a hybrid power modeling scheme integrating three different levels of power models (including the instruction-level power model, the memory power model, and the transaction-based power model). These models are built using gate-level simulation first before being applied to the ESL simulation in which SystemC and instruction-set simulator (ISS) can be used to quickly perform the system-level power simulation with some realistic application programs. Within this system-level power modeling and simulation framework, one is able to analyze how memory configuration (e.g., cache sizes) will affect the system's power consumption at a very early design stage.
{"title":"Memory-aware power modeling for PAC DSP core","authors":"Chen-Wei Hsu, Jia-Lu Liao, J. Yeh, Ji-Jan Chen, Shi-Yu Huang, J. Liou","doi":"10.1109/ASQED.2009.5206396","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206396","url":null,"abstract":"In this work, we propose a fast and accurate system-level power estimation methodology. To achieve high accuracy for an in-house digital signal processor, called PAC, we incorporate a hybrid power modeling scheme integrating three different levels of power models (including the instruction-level power model, the memory power model, and the transaction-based power model). These models are built using gate-level simulation first before being applied to the ESL simulation in which SystemC and instruction-set simulator (ISS) can be used to quickly perform the system-level power simulation with some realistic application programs. Within this system-level power modeling and simulation framework, one is able to analyze how memory configuration (e.g., cache sizes) will affect the system's power consumption at a very early design stage.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115942069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206277
Peter Pann
The author describes various procedures to minimize risks involved in prototyping of analogue and mixed signal integrated circuits at external fabs and compares different approaches of minimizing NRE costs. Additionally the author describes Multi Product Wafer (MPW) or Multi Layer Mask (MLM) service and procedures of parallel processing of different design versions on one mask set. Furthermore he gives some guidelines for efficient production ramp-up and yield optimization and opens a discussion on the optimization on back-end assembly and test activities. Finally several online tools provided by foundries from the engineering phase through production will be discussed.
{"title":"Prototyping and testing of analog integrated circuits","authors":"Peter Pann","doi":"10.1109/ASQED.2009.5206277","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206277","url":null,"abstract":"The author describes various procedures to minimize risks involved in prototyping of analogue and mixed signal integrated circuits at external fabs and compares different approaches of minimizing NRE costs. Additionally the author describes Multi Product Wafer (MPW) or Multi Layer Mask (MLM) service and procedures of parallel processing of different design versions on one mask set. Furthermore he gives some guidelines for efficient production ramp-up and yield optimization and opens a discussion on the optimization on back-end assembly and test activities. Finally several online tools provided by foundries from the engineering phase through production will be discussed.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122941214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206304
M. Moradinasab, F. Karbassian, M. Fathipour
In this paper we investigate the effects of supply voltage and the temperature on the characteristics of the Static Random Access Memory (SRAM). Two nanoscale SRAM cells based on Carbon Nanotube Field Effect Transistors (CNFETs) and Silicon MOSFET Transistors (Si-MOSFETs) were investigated for application in 32nm technology node. Simulation studies show that the stability of CNFET SRAM against supply voltage variation and temperature influences is larger than those of its Si-MOSFET SRAM counterpart. Furthermore, the circuit performance affected by these two parameters in a 32k SRAM array was investigated. The results show that the read access time in CNFET SRAM arrays based on chirality vectors bigger than (23,0), is less than conventional MOSFET SRAM array.
{"title":"A comparison study of the effects of supply voltage and temperature on the stability and performance of CNFET and nanoscale Si-MOSFET SRAMs","authors":"M. Moradinasab, F. Karbassian, M. Fathipour","doi":"10.1109/ASQED.2009.5206304","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206304","url":null,"abstract":"In this paper we investigate the effects of supply voltage and the temperature on the characteristics of the Static Random Access Memory (SRAM). Two nanoscale SRAM cells based on Carbon Nanotube Field Effect Transistors (CNFETs) and Silicon MOSFET Transistors (Si-MOSFETs) were investigated for application in 32nm technology node. Simulation studies show that the stability of CNFET SRAM against supply voltage variation and temperature influences is larger than those of its Si-MOSFET SRAM counterpart. Furthermore, the circuit performance affected by these two parameters in a 32k SRAM array was investigated. The results show that the read access time in CNFET SRAM arrays based on chirality vectors bigger than (23,0), is less than conventional MOSFET SRAM array.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"324 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122990288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206289
H. Mostafa, M. Anis, M. Elmasry
In deeply pipelined synchronous systems, any violation of the timing constraints of the flip-flops can cause the overall system to malfunction. Due to CMOS technology scaling, increased process variations result in a large delay variability causing unacceptable loss in the timing yield. Several variation tolerant techniques are introduced to mitigate this variability challenge by improving the timing yield. In the mean time, devices are getting smaller, faster, and operating at lower supply voltages. These reduced capacitances and power supply voltages combined with the increased chip density to perform more functionality increase the soft errors susceptibility and make it one of the essential design challenges. Moreover, there are many flip-flops topologies that vary in their relative performance and power consumption which make the selection decision very difficult to flip-flops designers especially under variability and soft errors challenges. Therefore, a comparative analysis between these different flip-flops topologies considering these scaling challenges is beneficial to guide the flip-flops designers in selecting the best topology for their specific application constraints. This paper presents a comparative analysis of the timing yield improvement impact on flip-flops soft error rate by using the STMicroelectronics 65-nm CMOS technology. The analyzed flip-flops are compared for power and power-delay product (PDP) overheads to achieve this timing yield improvement. Then, they are compared for the soft error susceptibility. Finally, it is shown that the timing yield improvement improves the flip-flops soft error immunity significantly.
{"title":"The impact of timing yield improvement under process variation on flip-flops soft error rate","authors":"H. Mostafa, M. Anis, M. Elmasry","doi":"10.1109/ASQED.2009.5206289","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206289","url":null,"abstract":"In deeply pipelined synchronous systems, any violation of the timing constraints of the flip-flops can cause the overall system to malfunction. Due to CMOS technology scaling, increased process variations result in a large delay variability causing unacceptable loss in the timing yield. Several variation tolerant techniques are introduced to mitigate this variability challenge by improving the timing yield. In the mean time, devices are getting smaller, faster, and operating at lower supply voltages. These reduced capacitances and power supply voltages combined with the increased chip density to perform more functionality increase the soft errors susceptibility and make it one of the essential design challenges. Moreover, there are many flip-flops topologies that vary in their relative performance and power consumption which make the selection decision very difficult to flip-flops designers especially under variability and soft errors challenges. Therefore, a comparative analysis between these different flip-flops topologies considering these scaling challenges is beneficial to guide the flip-flops designers in selecting the best topology for their specific application constraints. This paper presents a comparative analysis of the timing yield improvement impact on flip-flops soft error rate by using the STMicroelectronics 65-nm CMOS technology. The analyzed flip-flops are compared for power and power-delay product (PDP) overheads to achieve this timing yield improvement. Then, they are compared for the soft error susceptibility. Finally, it is shown that the timing yield improvement improves the flip-flops soft error immunity significantly.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121396491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206283
F. Karbassian, M. Moradinasab, M. Fathipour
The carbon nanotube field-effect transistor (CNTFET) is a promising candidate for future electronic devices. Numerical studies are performed to investigate the impact of structural and process parameters on the conventional CNTFETs. The impact of channel length, gate dielectric thickness and permittivity, source/drain dopant concentration, workfunction of the gate, and drain voltage are studied. The drain current of the transistor increases as the nanotube diameter increases or as the gate workfunction decreases. The transistor current is almost independent of source/drain dopant concentration at high dopant densities. But at low dopant concentrations it increases as dopant density increases.
{"title":"Numerical study of scaling issues of C-CNTFETs","authors":"F. Karbassian, M. Moradinasab, M. Fathipour","doi":"10.1109/ASQED.2009.5206283","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206283","url":null,"abstract":"The carbon nanotube field-effect transistor (CNTFET) is a promising candidate for future electronic devices. Numerical studies are performed to investigate the impact of structural and process parameters on the conventional CNTFETs. The impact of channel length, gate dielectric thickness and permittivity, source/drain dopant concentration, workfunction of the gate, and drain voltage are studied. The drain current of the transistor increases as the nanotube diameter increases or as the gate workfunction decreases. The transistor current is almost independent of source/drain dopant concentration at high dopant densities. But at low dopant concentrations it increases as dopant density increases.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125762314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206293
S. Sutanthavibul, Suresh Kumar Perabala
The paper describes a design IP-reuse methodology used in a new Intel Low Cost IA (LCIA) System-on-Chip (SoC) design, call Pineview (PNV). The PNV SoC is used in the next generation Intel Nettop/Netbook platform. The SoC chip integrates several Intel internal Intellectual Property (IP) blocks on the same die: mainly two Atom CPU cores, a Graphic engine, a memory controller, and IO interfaces. The IP-reuse methodology provides high design efficiency and productivity. It also allows flexibility and customization for lower power consumption and a floorplan optimization needed for the Nettop/Netbook market segment. The paper also provides an overview of the PNV based Nettop/Netbook platform architecture. It also explains IP-reuse methodology and full chip integration which is performed by a design team in Intel Penang Design Center.
{"title":"First Intel Low-Cost IA Atom-based System-On-Chip for Nettop/Netbook","authors":"S. Sutanthavibul, Suresh Kumar Perabala","doi":"10.1109/ASQED.2009.5206293","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206293","url":null,"abstract":"The paper describes a design IP-reuse methodology used in a new Intel Low Cost IA (LCIA) System-on-Chip (SoC) design, call Pineview (PNV). The PNV SoC is used in the next generation Intel Nettop/Netbook platform. The SoC chip integrates several Intel internal Intellectual Property (IP) blocks on the same die: mainly two Atom CPU cores, a Graphic engine, a memory controller, and IO interfaces. The IP-reuse methodology provides high design efficiency and productivity. It also allows flexibility and customization for lower power consumption and a floorplan optimization needed for the Nettop/Netbook market segment. The paper also provides an overview of the PNV based Nettop/Netbook platform architecture. It also explains IP-reuse methodology and full chip integration which is performed by a design team in Intel Penang Design Center.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127598687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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